髙木 直史

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氏名(漢字/フリガナ/アルファベット表記)
髙木 直史/タカギ ナオフミ/Naofumi Takagi
所属部署・職名(部局/所属/講座等/職名)
情報学研究科/通信情報システム専攻コンピュータ工学講座/教授
学部兼担
部局 所属 講座等 職名
工学部 工学部 情報学科
連絡先住所
種別 住所(日本語) 住所(英語)
職場 京都市左京区吉田本町 京都大学総合研究7号館 330号室 Room 330, Research Bld. #7, Yoshida-honmachi, Sakyo-ku, Kyoto
連絡先電話番号
種別 番号
職場 075-753-5373
電子メールアドレス
メールアドレス
takagi @ i.kyoto-u.ac.jp
所属学会(国内)
学会名(日本語) 学会名(英語)
電子情報通信学会 The Institute of Electronics, Information and Communication Engineers
情報処理学会 Information Processing Society of Japan
所属学会(海外)
学会名(英語) 国名
The Institute of Electrical and Electronics Engineers アメリカ合衆国
取得学位
学位名(日本語) 学位名(英語) 大学(日本語) 大学(英語) 取得区分
工学修士 京都大学
工学博士 京都大学
出身大学院・研究科等
大学名(日本語) 大学名(英語) 研究科名(日本語) 研究科名(英語) 専攻名(日本語) 専攻名(英語) 修了区分
京都大学 大学院工学研究科修士課程情報工学専攻 修了
出身学校・専攻等
大学名(日本語) 大学名(英語) 学部名(日本語) 学部名(英語) 学科名(日本語) 学科名(英語) 卒業区分
京都大学 工学部情報工学科 卒業
出身高等学校
高等学校名 ふりがな
大阪府立 北野高等学校 おおさかふりつ きたのこうとうがっこう
職歴
期間 組織名(日本語) 組織名(英語) 職名(日本語) 職名(英語)
1984/04/01〜1991/03/31 京都大学 Kyoto University 助手 Assistant Professor
1991/04/01〜1994/05/31 京都大学 Kyoto University 助教授 Assosiate Professor
1994/06/01〜1998/05/15 名古屋大学 Nagoya University 助教授 Associate Professor
1998/05/16〜2010/03/31 名古屋大学 Nagoya University 教授 Professor
2010/04/01〜 京都大学 Kyoto University 教授 Professor
プロフィール
(日本語)
1983年京都大学大学院工学研究科修士課程修了。工学博士。京都大学助教授、名古屋大学教授を経て、2010年より京都大学大学院情報学研究科(通信情報システム専攻)教授。専門は情報工学の基礎。主に、算術演算回路、ハードウェアアルゴリズム、論理設計の研究に従事。著書として「論理回路」(昭晃堂、1995年)、「算術演算のVLSIアルゴリズム](コロナ社、2005年)等。日本IBM科学賞、科学技術分野の文部科学大臣表彰等を受賞。IEEE、電子情報通信学会、情報処理学会等各会員。
(英語)
Naofumi Takagi received the BE, ME, and PhD degrees in information science from Kyoto University in 1981, 1983, and 1988, respectively. He was an associate professor at Kyoto University, was a professor at Nagoya University, and returned to Kyoto University in 2010 where he is a professor at Graduate School of Informatics. His current interests include computer arithmetic, hardware algorithms, and logic design. He received Japan IBM Science Award in 1995 and The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology of Japan in 2005. He is a senior member of IEEE and IEICE..
個人ホームページ
URL
http://www.lab3.kuis.kyoto-u.ac.jp/~ntakagi/ntakagi.html
研究テーマ
(日本語)
並列計算機構,算術演算回路,ハードウェアアルゴリズム
(英語)
Parallel computing architecture, arithmetic circuits, hardware algorithms
研究分野(キーワード)
キーワード(日本語) キーワード(英語)
情報学 Informatics
計算機科学 Computer Science
研究分野(科研費分類コード)
科研費分類コード
計算機システム・ネットワーク
論文
著者 著者(日本語) 著者(英語) タイトル タイトル(日本語) タイトル(英語) 書誌情報等 書誌情報等(日本語) 書誌情報等(英語) 出版年月 査読の有無 記述言語 掲載種別 公開
廣瀬秀樹,高瀬英希,高木一義,高木直史 廣瀬秀樹,高瀬英希,高木一義,高木直史 HIROSE Hideki, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR IPSJ ESW2017 Research Papers,5-10 IPSJ ESW2017 Research Papers,5-10 IPSJ ESW2017 Research Papers,5-10 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
松本耕太郎,高木一義,高木直史 松本耕太郎,高木一義,高木直史 MATSUMOTO Kotaro, TAKAGI Kazuyoshi, TAKAGI Naofumi Algorithms for Evaluating te Matrix Polynomial I+A+A^2+...+A^{N-1} with Reduced Number of Matrix Multiplications Algorithms for Evaluating te Matrix Polynomial I+A+A^2+...+A^{N-1} with Reduced Number of Matrix Multiplications Algorithms for Evaluating te Matrix Polynomial I+A+A^2+...+A^{N-1} with Reduced Number of Matrix Multiplications IEICE Transactions on Fundamentals,E101-A,2,467-471 IEICE Transactions on Fundamentals,E101-A,2,467-471 IEICE Transactions on Fundamentals,E101-A,2,467-471 2018/02 英語 研究論文(学術雑誌) 公開
佐藤諒,畑中湧貴,安藤友紀,田中雅光,藤巻朗,高木一義,高木直史 佐藤諒,畑中湧貴,安藤友紀,田中雅光,藤巻朗,高木一義,高木直史 SATO Ryo, HATANAKA Yuki, ANDO Yuki, TANAKA Masamitsu, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi High-Speed Operation of Random-Access-Memory-Embedded Microprocessor with Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic High-Speed Operation of Random-Access-Memory-Embedded Microprocessor with Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic High-Speed Operation of Random-Access-Memory-Embedded Microprocessor with Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic IEEE Transactions on Applied Superconductivity,27,4,1300505 IEEE Transactions on Applied Superconductivity,27,4,1300505 IEEE Transactions on Applied Superconductivity,27,4,1300505 2017/06 英語 研究論文(学術雑誌) 公開
唐光明,高木一義,高木直史 唐光明,高木一義,高木直史 TANG Guangming, TAKAGI Kazuyoshi, TAKAGI Naofumi 32x32-bit 4-bit bit-slice integer multiplier for RSFQ microprocessors 32x32-bit 4-bit bit-slice integer multiplier for RSFQ microprocessors 32x32-bit 4-bit bit-slice integer multiplier for RSFQ microprocessors IEEE Transactions on Applied Superconductivity,27,3,5 IEEE Transactions on Applied Superconductivity,27,3,5 IEEE Transactions on Applied Superconductivity,27,3,5 2017/04 英語 研究論文(学術雑誌) 公開
鬼頭信貴,秋元一志,高木直史 鬼頭信貴,秋元一志,高木直史 Kito Nobutaka, AKIMOTO Kazushi, TAKAGI Naofumi Floating-point multiplier with concurrent error detection capability by partial duplication Floating-point multiplier with concurrent error detection capability by partial duplication Floating-point multiplier with concurrent error detection capability by partial duplication IEICE Transactions on Information and Systems,E100-D,3,531-536 IEICE Transactions on Information and Systems,E100-D,3,531-536 IEICE Transactions on Information and Systems,E100-D,3,531-536 2017/03 英語 研究論文(学術雑誌) 公開
安藤友紀 佐藤諒 田中雅光 高木一義 高木直史 藤巻朗 安藤友紀 佐藤諒 田中雅光 高木一義 高木直史 藤巻朗 ANDO Yuki, SATO Ryo, TANAKA Masamitsu, TAKAGI Kazuyoshi, TAKAGI Naofumi, FUJIMAKI Akira Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 IEEE Transactions on Applied Superconductivity,26,5 IEEE Transactions on Applied Superconductivity,26,5 IEEE Transactions on Applied Superconductivity,26,5 2016/08 英語 研究論文(学術雑誌) 公開
唐光明 高木一義 高木直史 唐光明 高木一義 高木直史 TANG Guang-Ming, TAKAGI Kazuyoshi, TAKAGI Naofumi RSFQ 4-bit bit-slice integer multiplier RSFQ 4-bit bit-slice integer multiplier RSFQ 4-bit bit-slice integer multiplier IEICE Transactions on Electronics,E99.C,6,702 IEICE Transactions on Electronics,E99.C,6,702 IEICE Transactions on Electronics,E99.C,6,702 2016/06 英語 研究論文(学術雑誌) 公開
田中雅光 高木一義 高木直史 田中雅光 高木一義 高木直史 TANAKA Masamitsu, TAKAGI Kazuyoshi, TAKAGI Naofumi High-throughput rapid single-flux-quantum circuit implementations for exponential and logarithm computation using the radix-2 signed-digit representation High-throughput rapid single-flux-quantum circuit implementations for exponential and logarithm computation using the radix-2 signed-digit representation High-throughput rapid single-flux-quantum circuit implementations for exponential and logarithm computation using the radix-2 signed-digit representation IEICE Transactions on Electronics,E99.C,6,709 IEICE Transactions on Electronics,E99.C,6,709 IEICE Transactions on Electronics,E99.C,6,709 2016/06 英語 研究論文(学術雑誌) 公開
高瀬英希,青野和巳,松原豊,高木一義,高木直史 高瀬英希,青野和巳,松原豊,高木一義,高木直史 TAKASE Hideki, AONO Kazumi, MATSUBARA Yutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi An evaluation framework of OS-level power managements for the big.LITTLE architecture An evaluation framework of OS-level power managements for the big.LITTLE architecture An evaluation framework of OS-level power managements for the big.LITTLE architecture Proc. 14th IEEE International NEWCAS Conference Proc. 14th IEEE International NEWCAS Conference Proc. 14th IEEE International NEWCAS Conference 2016/06 英語 研究論文(国際会議プロシーディングス) 公開
鬼頭信貴 高木一義 高木直史 鬼頭信貴 高木一義 高木直史 KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi Automatic wire-routing of SFQ digital circuits considering wire-length matching Automatic wire-routing of SFQ digital circuits considering wire-length matching Automatic wire-routing of SFQ digital circuits considering wire-length matching IEEE Transactions on Applied Superconductivity,26,3,1-5 IEEE Transactions on Applied Superconductivity,26,3,1-5 IEEE Transactions on Applied Superconductivity,26,3,1-5 2016/04 英語 研究論文(学術雑誌) 公開
唐光明 高田賢介 田中雅光 藤巻朗 高木一義 高木直史 唐光明 高田賢介 田中雅光 藤巻朗 高木一義 高木直史 TANG Guan-Ming, TAKATA Kensuke, TANAKA Masamitsu, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi 4-bit bit-slice arithmetic logic unit for 32-bit RSFQ microprocessors 4-bit bit-slice arithmetic logic unit for 32-bit RSFQ microprocessors 4-bit bit-slice arithmetic logic unit for 32-bit RSFQ microprocessors IEEE Transactions on Applied Superconductivity,26,1,1-6 IEEE Transactions on Applied Superconductivity,26,1,1-6 IEEE Transactions on Applied Superconductivity,26,1,1-6 2016/01 英語 研究論文(学術雑誌) 公開
川口隆広 高木一義 高木直史 川口隆広 高木一義 高木直史 Kawaguchi Takahiro, TAKAGI Kazuyoshi, TAKAGI Naofumi A verification method for single-flux-quantum circuits using delay-based time frame model A verification method for single-flux-quantum circuits using delay-based time frame model A verification method for single-flux-quantum circuits using delay-based time frame model IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciencies,E98.A,12,2564 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciencies,E98.A,12,2564 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciencies,E98.A,12,2564 2015/12 英語 研究論文(学術雑誌) 公開
HATAYAMA Takuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi HATAYAMA Takuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi HATAYAMA Takuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems IPSJ Transactions on System LSI Design Methodology,8,100-104 IPSJ Transactions on System LSI Design Methodology,8,100-104 IPSJ Transactions on System LSI Design Methodology,8,100-104 2015/08 英語 研究論文(学術雑誌) 公開
安藤友紀 佐藤諒 田中雅光 高木一義 高木直史 安藤友紀 佐藤諒 田中雅光 高木一義 高木直史 ANDO Yuki, SATO Ryo, TANAKA Masamitsu, TAKAGI Kazuyoshi, TAKAGI Naofumi 80-GHz Operation of an 8-Bit RSFQ Arithmetic Logic Unit 80-GHz Operation of an 8-Bit RSFQ Arithmetic Logic Unit 80-GHz Operation of an 8-Bit RSFQ Arithmetic Logic Unit Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) 2015/07 英語 研究論文(国際会議プロシーディングス) 公開
唐光明 高木一義 高木直史 唐光明 高木一義 高木直史 TANG Guang-Ming, TAKAGI Kazuyoshi, TAKAGI Naofumi A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) Proc. of 15th International Superconductive Electronics Conference (ISEC 2015) 2015/07 英語 研究論文(国際会議プロシーディングス) 公開
川口隆広 田中雅光 高木一義 高木直史 川口隆広 田中雅光 高木一義 高木直史 KAWAGUCHI Takahiro, TANAKA Masamitsu, TAKAGI Kazuyoshi, TAKAGI Naofumi Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) 2015/07 英語 研究論文(国際会議プロシーディングス) 公開
田中雅光 高田賢介 川口隆広 安藤友紀 吉川信行 佐藤諒 藤巻朗 高木一義 高木直史 田中雅光 高田賢介 川口隆広 安藤友紀 吉川信行 佐藤諒 藤巻朗 高木一義 高木直史 TANAKA Masamitsu, TAKATA Kensuke, KAWAGUCHI Takahiro, ANDO Yuki, YOSHIKAWA Nobuyuki, SATO Ryo, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) 2015/07 英語 研究論文(国際会議プロシーディングス) 公開
佐藤諒 高田賢介 田中雅光 高木直史 高木一義 藤巻朗 佐藤諒 高田賢介 田中雅光 高木直史 高木一義 藤巻朗 SATO Ryo, TAKATA Kensuke, TANAKA Masamitsu, TAKAGI Naofumi, TAKAGI Kazuyoshi, FUJIMAKI Akira Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) Proc. 15th International Superconductive Electronics Conference (ISEC 2015) 2015/07 英語 研究論文(国際会議プロシーディングス) 公開
KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates IEEE Transactions on Applied Superconductivity,25,3 IEEE Transactions on Applied Superconductivity,25,3 IEEE Transactions on Applied Superconductivity,25,3 2015/06 英語 研究論文(学術雑誌) 公開
X. Peng, Q. Xu, T. Kato Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, M. Hidaka X. Peng, Q. Xu, T. Kato Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, M. Hidaka X. Peng, Q. Xu, T. Kato Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, M. Hidaka High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits IEEE Transactions on Applied Superconductivity,25,3 IEEE Transactions on Applied Superconductivity,25,3 IEEE Transactions on Applied Superconductivity,25,3 2015/06 英語 研究論文(学術雑誌) 公開
HATAYAMA Takuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi HATAYAMA Takuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems Proceedings - 11th International SoC Design Conference,118-119 Proceedings - 11th International SoC Design Conference,118-119 Proceedings - 11th International SoC Design Conference,118-119 2014/12 英語 研究論文(国際会議プロシーディングス) 公開
SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E97.A,12,2498-2506 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E97.A,12,2498-2506 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E97.A,12,2498-2506 2014/12 英語 研究論文(学術雑誌) 公開
AONO Kazumi, IWATA Atsushi, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi AONO Kazumi, IWATA Atsushi, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi AONO Kazumi, IWATA Atsushi, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Minimize the Operation Quality An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Minimize the Operation Quality An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Minimize the Operation Quality Proceedings - 11th International Conference on Embedded Software,546-549 Proceedings - 11th International Conference on Embedded Software,546-549 Proceedings - 11th International Conference on Embedded Software,546-549 2014/08 英語 研究論文(国際会議プロシーディングス) 公開
PENG Xizhu, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, HIDAKA Mutsuo PENG Xizhu, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, HIDAKA Mutsuo PENG Xizhu, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, HIDAKA Mutsuo Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Multipliers Using 10 kA/cm2 Nb Process Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Multipliers Using 10 kA/cm2 Nb Process Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Multipliers Using 10 kA/cm2 Nb Process IEICE Transactions on Electronics,E97-C,3,188-193 IEICE Transactions on Electronics,E97-C,3,188-193 IEICE Transactions on Electronics,E97-C,3,188-193 2014/03 英語 研究論文(学術雑誌) 公開
NAGASAWA Shuichi, HINODE Kenji, SATOH Tetsuro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, YOSHIKAWA Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAGASAWA Shuichi, HINODE Kenji, SATOH Tetsuro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, YOSHIKAWA Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAGASAWA Shuichi, HINODE Kenji, SATOH Tetsuro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, YOSHIKAWA Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation IEICE Transactions on Electronics,E97-C,3,132-140 IEICE Transactions on Electronics,E97-C,3,132-140 IEICE Transactions on Electronics,E97-C,3,132-140 2014/03 英語 研究論文(学術雑誌) 公開
KATAOKA Hiroshi, HONDA Hiroaki, MEHDIPOUR Farhad, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAOKA Hiroshi, HONDA Hiroaki, MEHDIPOUR Farhad, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAOKA Hiroshi, HONDA Hiroaki, MEHDIPOUR Farhad, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, MURAKAMI Kazuaki A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits IEICE Trnsactions on Electronics,E97-C,3,141-148 IEICE Trnsactions on Electronics,E97-C,3,141-148 IEICE Trnsactions on Electronics,E97-C,3,141-148 2014/03 英語 研究論文(学術雑誌) 公開
TAKAGI Kazuyoshi, KITO Nobutaka, TAKAGI Naofumi TAKAGI Kazuyoshi, KITO Nobutaka, TAKAGI Naofumi TAKAGI Kazuyoshi, KITO Nobutaka, TAKAGI Naofumi Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Circuit Description and Design Flow of Superconducting SFQ Logic Circuits IEICE Transactions on Electronics,E97-C,3,149-156 IEICE Transactions on Electronics,E97-C,3,149-156 IEICE Transactions on Electronics,E97-C,3,149-156 2014/03 英語 研究論文(学術雑誌) 公開
FUJIMAKI Akira, TANAKA Masamitsu, KASAGI Ryo, TAKAGI Katsumi, OKADA Masakazu, HAYAKAWA Yuhi, TAKATA Kemsuke, AKAIKE Hiroyuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, TAKAGI Kazuyoshi, TAKAGI Naofumi FUJIMAKI Akira, TANAKA Masamitsu, KASAGI Ryo, TAKAGI Katsumi, OKADA Masakazu, HAYAKAWA Yuhi, TAKATA Kemsuke, AKAIKE Hiroyuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, TAKAGI Kazuyoshi, TAKAGI Naofumi FUJIMAKI Akira, TANAKA Masamitsu, KASAGI Ryo, TAKAGI Katsumi, OKADA Masakazu, HAYAKAWA Yuhi, TAKATA Kemsuke, AKAIKE Hiroyuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, TAKAGI Kazuyoshi, TAKAGI Naofumi Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors IEICE Transactions on Electronics,E97-C,3,157-165 IEICE Transactions on Electronics,E97-C,3,157-165 IEICE Transactions on Electronics,E97-C,3,157-165 2014/03 英語 研究論文(学術雑誌) 公開
A. Suda; H. Takase; K. Takagi; N. Takagi A. Suda; H. Takase; K. Takagi; N. Takagi A. Suda; H. Takase; K. Takagi; N. Takagi A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis Lecture Notes in Computer Science 8285 (Proceedings of ICA3PP 2013),8285 LNCS,PART 1,390-401 Lecture Notes in Computer Science 8285 (Proceedings of ICA3PP 2013),8285 LNCS,PART 1,390-401 Lecture Notes in Computer Science 8285 (Proceedings of ICA3PP 2013),8285 LNCS,PART 1,390-401 2013/12 英語 研究論文(国際会議プロシーディングス) 公開
鬼頭信貴,高木直史 鬼頭信貴,高木直史 KITO Nobutaka, TAKAGI Naofumi Low-overhead fault-secure parallel prefix adder by carry-bit duplication Low-overhead fault-secure parallel prefix adder by carry-bit duplication Low-overhead fault-secure parallel prefix adder by carry-bit duplication IEICE Transactions on Information and Systems,E96-D,9,1962-1970 IEICE Transactions on Information and Systems,E96-D,9,1962-1970 IEICE Transactions on Information and Systems,E96-D,9,1962-1970 2013/09 英語 研究論文(学術雑誌) 公開
KATO T., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shiichi KATO T., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shiichi KATO T., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shiichi 60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm<sup>2</sup> Nb process 60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm<sup>2</sup> Nb process 60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm<sup>2</sup> Nb process 14th International Superconductive Electronics Conference (ISEC 2013) 14th International Superconductive Electronics Conference (ISEC 2013) 14th International Superconductive Electronics Conference (ISEC 2013) 2013/07 英語 研究論文(学術雑誌) 公開
高木直史 高木直史 TAKAGI Naofumi An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits Physica C: Superconductivity and its Applications,484,213-216 Physica C: Superconductivity and its Applications,484,213-216 Physica C: Superconductivity and its Applications,484,213-216 2013/01 英語 研究論文(学術雑誌) 公開
I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi Experimental demonstration of an operand routing network prototype employing clock control and data synchronization Experimental demonstration of an operand routing network prototype employing clock control and data synchronization Experimental demonstration of an operand routing network prototype employing clock control and data synchronization Physics Procedia,36,349-353 Physics Procedia,36,349-353 Physics Procedia,36,349-353 2012/06 英語 研究論文(国際会議プロシーディングス) 公開
K. Kobayashi; N. Takagi; K. Takagi K. Kobayashi; N. Takagi; K. Takagi K. Kobayashi; N. Takagi; K. Takagi Fast inversion algorithm in GF(2 <sup>m</sup>) suitable for implementation with a polynomial multiply instruction on GF(2) Fast inversion algorithm in GF(2 <sup>m</sup>) suitable for implementation with a polynomial multiply instruction on GF(2) Fast inversion algorithm in GF(2 <sup>m</sup>) suitable for implementation with a polynomial multiply instruction on GF(2) IET Computers and Digital Techniques,6,3,180-185 IET Computers and Digital Techniques,6,3,180-185 IET Computers and Digital Techniques,6,3,180-185 2012/05 英語 研究論文(学術雑誌) 公開
K. Nakamura; R. Shimazaki; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; R. Shimazaki; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; R. Shimazaki; M. Yamamoto; K. Takagi; N. Takagi A VLSI architecture with multiple fast store-based block parallel processing for output probability and likelihood score computations in HMM-based isolated word recognition A VLSI architecture with multiple fast store-based block parallel processing for output probability and likelihood score computations in HMM-based isolated word recognition A VLSI architecture with multiple fast store-based block parallel processing for output probability and likelihood score computations in HMM-based isolated word recognition IEICE Transactions on Electronics,E95-C,4,456-467 IEICE Transactions on Electronics,E95-C,4,456-467 IEICE Transactions on Electronics,E95-C,4,456-467 2012/04 英語 研究論文(学術雑誌) 公開
N. Kito; S. Fuji; N. Takagi N. Kito; S. Fuji; N. Takagi N. Kito; S. Fuji; N. Takagi A C-testable multiple-block carry select adder A C-testable multiple-block carry select adder A C-testable multiple-block carry select adder IEICE Transactions on Information and Systems,E95-D,4,1084-1092 IEICE Transactions on Information and Systems,E95-D,4,1084-1092 IEICE Transactions on Information and Systems,E95-D,4,1084-1092 2012/04 英語 研究論文(学術雑誌) 公開
H. Kawashima, N. Takagi H. Kawashima, N. Takagi H. Kawashima, N. Takagi Partial product generation utilizing the sum of operands for reduced area parallel multipliers Partial product generation utilizing the sum of operands for reduced area parallel multipliers Partial product generation utilizing the sum of operands for reduced area parallel multipliers IPSJ Transactions on System LSI Design Methodology,4,131-139 IPSJ Transactions on System LSI Design Methodology,4,131-139 IPSJ Transactions on System LSI Design Methodology,4,131-139 2011/08 英語 研究論文(学術雑誌) 公開
M. Tanaka; H. Akaike; A. Fujimaki; Y. Yamanashi; N. Yoshikawa; S. Nagasawa; K. Takagi; N. Takagi M. Tanaka; H. Akaike; A. Fujimaki; Y. Yamanashi; N. Yoshikawa; S. Nagasawa; K. Takagi; N. Takagi M. Tanaka; H. Akaike; A. Fujimaki; Y. Yamanashi; N. Yoshikawa; S. Nagasawa; K. Takagi; N. Takagi 100-GHz single-flux-quantum bit-serial adder based on 10-kA/cn<sup>2</sup> niobium process 100-GHz single-flux-quantum bit-serial adder based on 10-kA/cn<sup>2</sup> niobium process 100-GHz single-flux-quantum bit-serial adder based on 10-kA/cn<sup>2</sup> niobium process IEEE Transactions on Applied Superconductivity,21,3,Pt.1,792-796 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,792-796 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,792-796 2011/06 英語 研究論文(学術雑誌) 公開
I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; S. Nagasawa; N. Takagi I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; S. Nagasawa; N. Takagi I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; S. Nagasawa; N. Takagi Clock line considerations for an SFQ large scale reconfigurable data paths processor Clock line considerations for an SFQ large scale reconfigurable data paths processor Clock line considerations for an SFQ large scale reconfigurable data paths processor IEEE Transactions on Applied Superconductivity,21,3,Pt.1,809-813 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,809-813 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,809-813 2011/06 英語 研究論文(学術雑誌) 公開
T. Kainuma; Y. Shimamura; F. Miyaoka; Y. Yamanashi; N. Yoshikawa; A. Fujimaki; K. Takagi; N. Takagi; S. Nagasawa T. Kainuma; Y. Shimamura; F. Miyaoka; Y. Yamanashi; N. Yoshikawa; A. Fujimaki; K. Takagi; N. Takagi; S. Nagasawa T. Kainuma; Y. Shimamura; F. Miyaoka; Y. Yamanashi; N. Yoshikawa; A. Fujimaki; K. Takagi; N. Takagi; S. Nagasawa Design and implementation of component circuits of an SFQ half-precision floating-point adder using 10-kA/cm<sup>2</sup> Nb Process Design and implementation of component circuits of an SFQ half-precision floating-point adder using 10-kA/cm<sup>2</sup> Nb Process Design and implementation of component circuits of an SFQ half-precision floating-point adder using 10-kA/cm<sup>2</sup> Nb Process IEEE Transactions on Applied Superconductivity,21,3,Pt.1,827-830 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,827-830 IEEE Transactions on Applied Superconductivity,21,3,Pt.1,827-830 2011/06 英語 研究論文(学術雑誌) 公開
TAKAGI Kazuyoshi, ITO Yuki, TAKESHIMA Shota, TANAKA Masamitsu, TAKAGI Naofumi TAKAGI Kazuyoshi, ITO Yuki, TAKESHIMA Shota, TANAKA Masamitsu, TAKAGI Naofumi TAKAGI Kazuyoshi, ITO Yuki, TAKESHIMA Shota, TANAKA Masamitsu, TAKAGI Naofumi Layout-driven skewed clock tree synthesis for superconducting SFQ circuits Layout-driven skewed clock tree synthesis for superconducting SFQ circuits Layout-driven skewed clock tree synthesis for superconducting SFQ circuits IEICE Transactions on Electronics,E94C,3,288-295 IEICE Transactions on Electronics,E94C,3,288-295 IEICE Transactions on Electronics,E94C,3,288-295 2011/03 英語 研究論文(学術雑誌) 公開
N. Kito; K. Hanai; N. Takagi N. Kito; K. Hanai; N. Takagi N. Kito; K. Hanai; N. Takagi A C-testable 4-2 adder tree for an easily testable high-speed multiplier A C-testable 4-2 adder tree for an easily testable high-speed multiplier A C-testable 4-2 adder tree for an easily testable high-speed multiplier IEICE Transactions on Information and Systems,E93-D,10,2783-2791 IEICE Transactions on Information and Systems,E93-D,10,2783-2791 IEICE Transactions on Information and Systems,E93-D,10,2783-2791 2010/10 英語 研究論文(学術雑誌) 公開
N. Takagi; M. Tanaka N. Takagi; M. Tanaka N. Takagi; M. Tanaka Comparisons of synchronous-clocking SFQ adders Comparisons of synchronous-clocking SFQ adders Comparisons of synchronous-clocking SFQ adders IEICE Transactions on Electronics,E93-C,4,429-434 IEICE Transactions on Electronics,E93-C,4,429-434 IEICE Transactions on Electronics,E93-C,4,429-434 2010/04 英語 研究論文(学術雑誌) 公開
M. Tanaka; K. Obata; Y. Ito; S. Takeshima; M. Sato; K. Takagi; N. Takagi; H. Akaike; A. Fujimaki M. Tanaka; K. Obata; Y. Ito; S. Takeshima; M. Sato; K. Takagi; N. Takagi; H. Akaike; A. Fujimaki M. Tanaka; K. Obata; Y. Ito; S. Takeshima; M. Sato; K. Takagi; N. Takagi; H. Akaike; A. Fujimaki Automated passive-transmission-line routing tool for single-flux-quantum circuits based on a* algorithm Automated passive-transmission-line routing tool for single-flux-quantum circuits based on a* algorithm Automated passive-transmission-line routing tool for single-flux-quantum circuits based on a* algorithm IEICE Transactions on Electronics,E93-C,4,435-439 IEICE Transactions on Electronics,E93-C,4,435-439 IEICE Transactions on Electronics,E93-C,4,435-439 2010/04 英語 研究論文(学術雑誌) 公開
Y. Yamanashi; T. Kainuma; N. Yoshikawa; I. Kataeva; H. Akaike; A. Fujimaki; M. Tanaka; N. Takagi; S. Nagasawa; M. Hidaka Y. Yamanashi; T. Kainuma; N. Yoshikawa; I. Kataeva; H. Akaike; A. Fujimaki; M. Tanaka; N. Takagi; S. Nagasawa; M. Hidaka Y. Yamanashi; T. Kainuma; N. Yoshikawa; I. Kataeva; H. Akaike; A. Fujimaki; M. Tanaka; N. Takagi; S. Nagasawa; M. Hidaka 100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm<sup>2</sup> Nb multi-layer process 100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm<sup>2</sup> Nb multi-layer process 100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm<sup>2</sup> Nb multi-layer process IEICE Transactions on Electronics,E93-C,4,440-444 IEICE Transactions on Electronics,E93-C,4,440-444 IEICE Transactions on Electronics,E93-C,4,440-444 2010/04 英語 研究論文(学術雑誌) 公開
K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi A VLSI architecture for output probability computations of HMM-based recognition systems with store-based block parallel processing A VLSI architecture for output probability computations of HMM-based recognition systems with store-based block parallel processing A VLSI architecture for output probability computations of HMM-based recognition systems with store-based block parallel processing IEICE Transactions on Information and Systems,E93-D,2,300-305 IEICE Transactions on Information and Systems,E93-D,2,300-305 IEICE Transactions on Information and Systems,E93-D,2,300-305 2010/02 英語 研究論文(学術雑誌) 公開
K. Kobayashi; N. Takagi K. Kobayashi; N. Takagi K. Kobayashi; N. Takagi Fast hardware algorithm for division in (2<sup>m</sup>) based on the extended Euclid's algorithm with parallelization of modular reductions Fast hardware algorithm for division in (2<sup>m</sup>) based on the extended Euclid's algorithm with parallelization of modular reductions Fast hardware algorithm for division in (2<sup>m</sup>) based on the extended Euclid's algorithm with parallelization of modular reductions IEEE Transactions on Circuits and Systems II: Express Briefs,56,8,644-648 IEEE Transactions on Circuits and Systems II: Express Briefs,56,8,644-648 IEEE Transactions on Circuits and Systems II: Express Briefs,56,8,644-648 2009/08 英語 研究論文(学術雑誌) 公開
鬼頭信貴,高木直史 鬼頭信貴,高木直史 KITO Nobutaka, TAKAGI Naofumi けた上げ保存加算器で構成された部分積加算部をもつ乗算器のテスト けた上げ保存加算器で構成された部分積加算部をもつ乗算器のテスト Testability of Multipliers with a Partial Product Compressor Consisting of Carry Save Adders 電子情報通信学会論文誌,J92-D,7,994-1002 電子情報通信学会論文誌,J92-D,7,994-1002 Transactions of IEICE,J92-D,7,994-1002 2009/07 日本語 研究論文(学術雑誌) 公開
NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki Nb Multi-Layer Device Fabrication Technology Nb Multi-Layer Device Fabrication Technology Nb Multi-Layer Device Fabrication Technology 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M., FUJIMAKI Akira, IGARASHI M. PARK H., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M., FUJIMAKI Akira, IGARASHI M. PARK H., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M., FUJIMAKI Akira, IGARASHI M. PARK H., YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi Hardware Algorithms for SFQ Arithmetic Circuits Hardware Algorithms for SFQ Arithmetic Circuits Hardware Algorithms for SFQ Arithmetic Circuits 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Inoue; H. Honda; K. Murakami I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Inoue; H. Honda; K. Murakami I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Inoue; H. Honda; K. Murakami An operand routing network for an SFQ reconfigurable Data-Paths processor An operand routing network for an SFQ reconfigurable Data-Paths processor An operand routing network for an SFQ reconfigurable Data-Paths processor IEEE Transactions on Applied Superconductivity,19,3,Pt.1,665-669 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,665-669 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,665-669 2009/06 英語 研究論文(学術雑誌) 公開
H. Hara; K. Obata; H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa H. Hara; K. Obata; H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa H. Hara; K. Obata; H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa Design, implementation and on-chip high-speed test of sfq half-precision floating-point multiplier Design, implementation and on-chip high-speed test of sfq half-precision floating-point multiplier Design, implementation and on-chip high-speed test of sfq half-precision floating-point multiplier IEEE Transactions on Applied Superconductivity,19,3,Pt.1,657-660 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,657-660 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,657-660 2009/06 英語 研究論文(学術雑誌) 公開
H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; K. Obata; Y. Ito; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; K. Obata; Y. Ito; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; M. Tanaka; K. Obata; Y. Ito; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa Design and implementation and on-chip high-speed test of SFQ half-precision floating-point adders Design and implementation and on-chip high-speed test of SFQ half-precision floating-point adders Design and implementation and on-chip high-speed test of SFQ half-precision floating-point adders IEEE Transactions on Applied Superconductivity,19,3,Pt.1,634-639 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,634-639 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,634-639 2009/06 英語 研究論文(学術雑誌) 公開
M. Tanaka; K. Obata; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa M. Tanaka; K. Obata; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa M. Tanaka; K. Obata; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa IEEE Transactions on Applied Superconductivity IEEE Transactions on Applied Superconductivity A high-throughput single-flux quantum floating-point serial divider using the signed-digit representation IEEE Transactions on Applied Superconductivity,19,3,653-656 IEEE Transactions on Applied Superconductivity,19,3,653-656 IEEE Transactions on Applied Superconductivity,19,3,653-656 2009/06 英語 研究論文(学術雑誌) 公開
T. Satoh; K. Hinode; S. Nagasawa; Y. Kitagawa; M. Hidaka; N. Yoshikawa; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi T. Satoh; K. Hinode; S. Nagasawa; Y. Kitagawa; M. Hidaka; N. Yoshikawa; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi T. Satoh; K. Hinode; S. Nagasawa; Y. Kitagawa; M. Hidaka; N. Yoshikawa; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi Planarization process for fabricating multi-layer nb integrated circuits incorporating top active layer Planarization process for fabricating multi-layer nb integrated circuits incorporating top active layer Planarization process for fabricating multi-layer nb integrated circuits incorporating top active layer IEEE Transactions on Applied Superconductivity,19,3,Pt.1,167-170 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,167-170 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,167-170 2009/06 英語 研究論文(学術雑誌) 公開
K. Fujiwara; S. Nagasawa; Y. Hashimoto; M. Hidaka; N. Yoshikawa; M. Tanaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi K. Fujiwara; S. Nagasawa; Y. Hashimoto; M. Hidaka; N. Yoshikawa; M. Tanaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi K. Fujiwara; S. Nagasawa; Y. Hashimoto; M. Hidaka; N. Yoshikawa; M. Tanaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi Research on effective moat configuration for Nb multi-layer device structure Research on effective moat configuration for Nb multi-layer device structure Research on effective moat configuration for Nb multi-layer device structure IEEE Transactions on Applied Superconductivity,19,3,Pt.1,603-606 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,603-606 IEEE Transactions on Applied Superconductivity,19,3,Pt.1,603-606 2009/06 英語 研究論文(学術雑誌) 公開
KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 英語 研究論文(学術雑誌) 公開
H. Akaike; M. Tanaka; K. Takagi; I. Kataeva; R. Kasagi; A. Fujimaki; K. Takagi; M. Igarashi; H. Park; Y. Yamanashi; N. Yoshikawa; K. Fujiwara; S. Nagasawa; M. Hidaka; N. Takagi H. Akaike; M. Tanaka; K. Takagi; I. Kataeva; R. Kasagi; A. Fujimaki; K. Takagi; M. Igarashi; H. Park; Y. Yamanashi; N. Yoshikawa; K. Fujiwara; S. Nagasawa; M. Hidaka; N. Takagi H. Akaike; M. Tanaka; K. Takagi; I. Kataeva; R. Kasagi; A. Fujimaki; K. Takagi; M. Igarashi; H. Park; Y. Yamanashi; N. Yoshikawa; K. Fujiwara; S. Nagasawa; M. Hidaka; N. Takagi Design of single flux quantum cells for a 10-Nb-layer process Design of single flux quantum cells for a 10-Nb-layer process Design of single flux quantum cells for a 10-Nb-layer process Physica C: Superconductivity and its Applications,469,15-20,1670-1673 Physica C: Superconductivity and its Applications,469,15-20,1670-1673 Physica C: Superconductivity and its Applications,469,15-20,1670-1673 2009/05 英語 研究論文(学術雑誌) 公開
S. Nagasawa; T. Satoh; K. Hinode; Y. Kitagawa; M. Hidaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi; N. Yoshikawa S. Nagasawa; T. Satoh; K. Hinode; Y. Kitagawa; M. Hidaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi; N. Yoshikawa S. Nagasawa; T. Satoh; K. Hinode; Y. Kitagawa; M. Hidaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi; N. Yoshikawa New Nb multi-layer fabrication process for large-scale SFQ circuits New Nb multi-layer fabrication process for large-scale SFQ circuits New Nb multi-layer fabrication process for large-scale SFQ circuits Physica C: Superconductivity and its Applications,469,15-20,1578-1584 Physica C: Superconductivity and its Applications,469,15-20,1578-1584 Physica C: Superconductivity and its Applications,469,15-20,1578-1584 2009/05 英語 研究論文(学術雑誌) 公開
K. Obata; K. Takagi; N. Takagi K. Obata; K. Takagi; N. Takagi K. Obata; K. Takagi; N. Takagi A clock scheduling algorithm for high-throughput RSFQ digital circuits A clock scheduling algorithm for high-throughput RSFQ digital circuits A clock scheduling algorithm for high-throughput RSFQ digital circuits IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E91-A,12,3772-3782 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E91-A,12,3772-3782 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E91-A,12,3772-3782 2008/12 英語 研究論文(学術雑誌) 公開
KITO Nobutaka, TAKAGI Naofumi KITO Nobutaka, TAKAGI Naofumi KITO Nobutaka, TAKAGI Naofumi Level-testability of multi-operand adders Level-testability of multi-operand adders Level-testability of multi-operand adders Proceedings - 17th Asian Test Symposium,257-260 Proceedings - 17th Asian Test Symposium,257-260 Proceedings - 17th Asian Test Symposium,257-260 2008/11 英語 研究論文(国際会議プロシーディングス) 公開
K. Kobayashi; N. Takagi K. Kobayashi; N. Takagi K. Kobayashi; N. Takagi A combined circuit for multiplication and inversion in GF(2<sup>m</sup>) A combined circuit for multiplication and inversion in GF(2<sup>m</sup>) A combined circuit for multiplication and inversion in GF(2<sup>m</sup>) IEEE Transactions on Circuits and Systems II: Express Briefs,55,11,1144-1148 IEEE Transactions on Circuits and Systems II: Express Briefs,55,11,1144-1148 IEEE Transactions on Circuits and Systems II: Express Briefs,55,11,1144-1148 2008/11 英語 研究論文(学術雑誌) 公開
熊澤文雄,高木直史 熊澤文雄,高木直史 KUMAZAWA Fumio, TAKAGI Naofumi 複合算術演算の減算シフト型ハードウェアアルゴリズムの設計支援 複合算術演算の減算シフト型ハードウェアアルゴリズムの設計支援 Design Support of Digit-Recurrence Algorithms for Arithmetic Circuits 電子情報通信学会論文誌,J91-A,11,1026-1035 電子情報通信学会論文誌,J91-A,11,1026-1035 Transactions of IEICE,J91-A,11,1026-1035 2008/11 日本語 研究論文(学術雑誌) 公開
鬼頭信貴,高木直史 鬼頭信貴,高木直史 KITO NobutakaTAKAGI Naofumi 種々の部分積加算構造をもつテスト容易な乗算器の設計 種々の部分積加算構造をもつテスト容易な乗算器の設計 A Design Method of Easily Testable Multipliers with Various Structures of Partial Product Adder 電子情報通信学会論文誌,J91-D,10,2478-2486 電子情報通信学会論文誌,J91-D,10,2478-2486 Transactions of IEICE,J91-D,10,2478-2486 2008/10 日本語 研究論文(学術雑誌) 公開
川島裕崇,柴岡雅之,高木直史,高木一義 川島裕崇,柴岡雅之,高木直史,高木一義 KAWASHIMA Hirotaka, SHIBAOKA Masayuki, TAKAGI Naofumi, TAKAGI KAzuyoshi Karatsubaアルゴリズムに基づく小面積乗算器 Karatsubaアルゴリズムに基づく小面積乗算器 Reduced Area Multipliers Based on Karatsuba Algorithm 電子情報通信学会論文誌,J91-A,7,707-715 電子情報通信学会論文誌,J91-A,7,707-715 Transactions of IEICE,J91-A,7,707-715 2008/07 日本語 研究論文(学術雑誌) 公開
K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi K. Nakamura; M. Yamamoto; K. Takagi; N. Takagi Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Proceedings - IEEE International Symposium on Circuits and Systems,2008 Vol.5,1688-1691 Proceedings - IEEE International Symposium on Circuits and Systems,2008 Vol.5,1688-1691 Proceedings - IEEE International Symposium on Circuits and Systems,2008 Vol.5,1688-1691 2008/05 英語 研究論文(国際会議プロシーディングス) 公開
H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi Novel serial-parallel converter using SFQ logic circuits Novel serial-parallel converter using SFQ logic circuits Novel serial-parallel converter using SFQ logic circuits Physica C: Superconductivity and its Applications,20th,1977-1982 Physica C: Superconductivity and its Applications,20th,1977-1982 Physica C: Superconductivity and its Applications,20th,1977-1982 2008/03 英語 研究論文(学術雑誌) 公開
N. Takagi; K. Murakami; A. Fujimaki; N. Yoshikawaj; K. Inoue; H. Honda N. Takagi; K. Murakami; A. Fujimaki; N. Yoshikawaj; K. Inoue; H. Honda N. Takagi; K. Murakami; A. Fujimaki; N. Yoshikawaj; K. Inoue; H. Honda Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits IEICE Transactions on Electronics,E91-C,3,350-355 IEICE Transactions on Electronics,E91-C,3,350-355 IEICE Transactions on Electronics,E91-C,3,350-355 2008/03 英語 研究論文(学術雑誌) 公開
M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi Bipartite modular multiplication method Bipartite modular multiplication method Bipartite modular multiplication method IEEE Transactions on Computers,57,2,157-164 IEEE Transactions on Computers,57,2,157-164 IEEE Transactions on Computers,57,2,157-164 2008/02 英語 研究論文(学術雑誌) 公開
OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quanyum Digital Circuits A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quanyum Digital Circuits A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quanyum Digital Circuits IEICE Transactions on Electronics,E90-C,12,2278-2284 IEICE Transactions on Electronics,E90-C,12,2278-2284 IEICE Transactions on Electronics,E90-C,12,2278-2284 2007/12 英語 研究論文(学術雑誌) 公開
S. Iwasaki; M. Tanaka; Y. Yamanashi; H. Park; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami; H. Honda; K. Inoue S. Iwasaki; M. Tanaka; Y. Yamanashi; H. Park; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami; H. Honda; K. Inoue S. Iwasaki; M. Tanaka; Y. Yamanashi; H. Park; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami; H. Honda; K. Inoue Design of a reconfigurable data-path prototype in the single-flux-quantum circuit Design of a reconfigurable data-path prototype in the single-flux-quantum circuit Design of a reconfigurable data-path prototype in the single-flux-quantum circuit Superconductor Science and Technology,20,11,328-331 Superconductor Science and Technology,20,11,328-331 Superconductor Science and Technology,20,11,328-331 2007/11 英語 研究論文(学術雑誌) 公開
K. Kobayashi; N. Takagi; K. Takagi K. Kobayashi; N. Takagi; K. Takagi K. Kobayashi; N. Takagi; K. Takagi An algorithm for inversion in GF(2<sup>m</sup>) suitable for implementation using a polynomial multiply instruction on GF(2) An algorithm for inversion in GF(2<sup>m</sup>) suitable for implementation using a polynomial multiply instruction on GF(2) An algorithm for inversion in GF(2<sup>m</sup>) suitable for implementation using a polynomial multiply instruction on GF(2) Proceedings - 18th IEEE Symposium on Computer Arithmetic,105-112 Proceedings - 18th IEEE Symposium on Computer Arithmetic,105-112 Proceedings - 18th IEEE Symposium on Computer Arithmetic,105-112 2007/06 英語 研究論文(国際会議プロシーディングス) 公開
K. Obata; K. Takagi; N. Takagi K. Obata; K. Takagi; N. Takagi K. Obata; K. Takagi; N. Takagi Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E90-A,1,257-266 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E90-A,1,257-266 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E90-A,1,257-266 2007/01 英語 研究論文(学術雑誌) 公開
N. Takagi; K. Takagi N. Takagi; K. Takagi N. Takagi; K. Takagi A VLSI algorithm for integer square-rooting A VLSI algorithm for integer square-rooting A VLSI algorithm for integer square-rooting Proceedings - 2006 International Symposium on Intelligent Signal Processing and Communications (ISPACS'06),626-629 Proceedings - 2006 International Symposium on Intelligent Signal Processing and Communications (ISPACS'06),626-629 Proceedings - 2006 International Symposium on Intelligent Signal Processing and Communications (ISPACS'06),626-629 2006/12 英語 研究論文(国際会議プロシーディングス) 公開
Y.-H. Jang; N. Takagi; K. Takagi; Y.-J. Kwon Y.-H. Jang; N. Takagi; K. Takagi; Y.-J. Kwon Y.-H. Jang; N. Takagi; K. Takagi; Y.-J. Kwon New countermeasures against power analysis attacks for koblitz curve cryptosystems New countermeasures against power analysis attacks for koblitz curve cryptosystems New countermeasures against power analysis attacks for koblitz curve cryptosystems Proceedings - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006,1303-1306 Proceedings - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006,1303-1306 Proceedings - 2006 International Conference on Computational Intelligence and Security, ICCIAS 2006,1303-1306 2006/11 英語 研究論文(学術雑誌) 公開
N. Takagi; S. Kadowaki; K. Takagi N. Takagi; S. Kadowaki; K. Takagi N. Takagi; S. Kadowaki; K. Takagi A hardware algorithm for integer division using the SD2 representation A hardware algorithm for integer division using the SD2 representation A hardware algorithm for integer division using the SD2 representation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,10,2874-2881 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,10,2874-2881 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,10,2874-2881 2006/10 英語 研究論文(学術雑誌) 公開
K. Obata; M. Tanaka; Y. Tashiro; Y. Kamiya; N. Irie; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa; H. Terai; S. Yorozu K. Obata; M. Tanaka; Y. Tashiro; Y. Kamiya; N. Irie; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa; H. Terai; S. Yorozu K. Obata; M. Tanaka; Y. Tashiro; Y. Kamiya; N. Irie; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa; H. Terai; S. Yorozu Single-flux-quantum integer multiplier with systolic array structure Single-flux-quantum integer multiplier with systolic array structure Single-flux-quantum integer multiplier with systolic array structure Physica C: Superconductivity and its Applications,18th,1014-1019 Physica C: Superconductivity and its Applications,18th,1014-1019 Physica C: Superconductivity and its Applications,18th,1014-1019 2006/07 英語 研究論文(学術雑誌) 公開
F. Kumazawa; N. Takagi F. Kumazawa; N. Takagi F. Kumazawa; N. Takagi Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,6,1799-1806 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,6,1799-1806 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,6,1799-1806 2006/06 英語 研究論文(学術雑誌) 公開
M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi A hardware algorithm for modular multiplication/division based on the extended euclidean algorithm A hardware algorithm for modular multiplication/division based on the extended euclidean algorithm A hardware algorithm for modular multiplication/division based on the extended euclidean algorithm IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E88-A,12,3610-3617 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E88-A,12,3610-3617 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E88-A,12,3610-3617 2005/12 英語 研究論文(学術雑誌) 公開
KAIHARA Marcelo e., TAKAGI Naofumi KAIHARA Marcelo e., TAKAGI Naofumi Bipartite Modular Multiplication Bipartite Modular Multiplication Bipartite Modular Multiplication Lecture Notes in Computer Science (Proceedings of CHES 2005),3659,201-210 Lecture Notes in Computer Science (Proceedings of CHES 2005),3659,201-210 Lecture Notes in Computer Science (Proceedings of CHES 2005),3659,201-210 2005/08 英語 研究論文(国際会議プロシーディングス) 公開
T. Nishigai, M. Ito, N. Yoshikawa, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, H. Terai, S. Yorozu T. Nishigai, M. Ito, N. Yoshikawa, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, H. Terai, S. Yorozu T. Nishigai, M. Ito, N. Yoshikawa, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, H. Terai, S. Yorozu Advanced Design Approaches for SFQ Logic Circuits Bsed on the Binary Decision Diagram Advanced Design Approaches for SFQ Logic Circuits Bsed on the Binary Decision Diagram Advanced Design Approaches for SFQ Logic Circuits Bsed on the Binary Decision Diagram IEEE Transactions on Applied Superconductivity,15,2,380-383 IEEE Transactions on Applied Superconductivity,15,2,380-383 IEEE Transactions on Applied Superconductivity,15,2,380-383 2005/06 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, KADOWAKI Shunsuke, TAKAGI Kazuyoshi TAKAGI Naofumi, KADOWAKI Shunsuke, TAKAGI Kazuyoshi TAKAGI Naofumi, KADOWAKI Shunsuke, TAKAGI Kazuyoshi A Hardware Algorithm for Integer Division A Hardware Algorithm for Integer Division A Hardware Algorithm for Integer Division Proceedings - 17th IEEE Symposium on Computer Arithmetic,140-146 Proceedings - 17th IEEE Symposium on Computer Arithmetic,140-146 Proceedings - 17th IEEE Symposium on Computer Arithmetic,140-146 2005/06 英語 研究論文(国際会議プロシーディングス) 公開
小畑幸嗣,高木一義,高木直史 小畑幸嗣,高木一義,高木直史 OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi 2x2-Join を用いた二線式RSFQ論理回路設計手法 2x2-Join を用いた二線式RSFQ論理回路設計手法 Design Method of Dual-Rail RSFQ Logic Circuits Using 2x2-Join 電子情報通信学会論文誌,J88-C,3,202-209 電子情報通信学会論文誌,J88-C,3,202-209 Transactions of IEICE,J88-C,3,202-209 2005/03 日本語 研究論文(学術雑誌) 公開
M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi A hardware algorithm for modular multiplication/division A hardware algorithm for modular multiplication/division A hardware algorithm for modular multiplication/division IEEE Transactions on Computers,54,1,12-21 IEEE Transactions on Computers,54,1,12-21 IEEE Transactions on Computers,54,1,12-21 2005/01 英語 研究論文(学術雑誌) 公開
NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems Proceedings - 2004 International SoC Design Conference,109-112 Proceedings - 2004 International SoC Design Conference,109-112 Proceedings - 2004 International SoC Design Conference,109-112 2004/10 英語 研究論文(国際会議プロシーディングス) 公開
N.T. Quach; N. Takagi; M.J. Flynn N.T. Quach; N. Takagi; M.J. Flynn N.T. Quach; N. Takagi; M.J. Flynn Systematic IEEE rounding method for high-speed floating-point multipliers Systematic IEEE rounding method for high-speed floating-point multipliers Systematic IEEE rounding method for high-speed floating-point multipliers IEEE Transactions on Very Large Scale Integration (VLSI) Systems,12,5,511-521 IEEE Transactions on Very Large Scale Integration (VLSI) Systems,12,5,511-521 IEEE Transactions on Very Large Scale Integration (VLSI) Systems,12,5,511-521 2004/05 英語 研究論文(学術雑誌) 公開
M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi M.E. Kaihara; N. Takagi A VLSI algorithm for modular multiplication/division A VLSI algorithm for modular multiplication/division A VLSI algorithm for modular multiplication/division Proceedings - 16th Symposium on Computer Arithmetic,220-227 Proceedings - 16th Symposium on Computer Arithmetic,220-227 Proceedings - 16th Symposium on Computer Arithmetic,220-227 2003/06 英語 研究論文(国際会議プロシーディングス) 公開
熊澤文雄,高木直史,武内大輔,高木一義 熊澤文雄,高木直史,武内大輔,高木一義 KUMAZAWA Fumio, TAKAGI Naofumi, TAKAUCHI Daisuke, TAKAGI Kazuyoshi 浮動小数点ユークリッドノルム計算回路 浮動小数点ユークリッドノルム計算回路 Floating-Point Euclidean Norm Computing Circuit 電子情報通信学会論文誌,J86-A,4,456-464 電子情報通信学会論文誌,J86-A,4,456-464 Transactions of IEICE,J86-A,4,456-464 2003/04 日本語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, MATSUOKA Daisuke, TAKAGI Kazuyoshi TAKAGI Naofumi, MATSUOKA Daisuke, TAKAGI Kazuyoshi TAKAGI Naofumi, MATSUOKA Daisuke, TAKAGI Kazuyoshi Digit-Recurrence Algorithm for Computing Reciprocal Square-Root Digit-Recurrence Algorithm for Computing Reciprocal Square-Root Digit-Recurrence Algorithm for Computing Reciprocal Square-Root IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E86-A,1,221-228 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E86-A,1,221-228 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E86-A,1,221-228 2003/01 英語 研究論文(学術雑誌) 公開
NAKAMURA Kazuhiro, MURAKAMI Noriaki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, MURAKAMI Noriaki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, MURAKAMI Noriaki, TAKAGI Kazuyoshi, TAKAGI Naofumi A Real-Time Lipreading LSI for Word Recognition A Real-Time Lipreading LSI for Word Recognition A Real-Time Lipreading LSI for Word Recognition Proceedings 2002 IEEE Asia-Pacific Conference on ASIC,303-306 Proceedings 2002 IEEE Asia-Pacific Conference on ASIC,303-306 Proceedings 2002 IEEE Asia-Pacific Conference on ASIC,303-306 2002/08 英語 研究論文(国際会議プロシーディングス) 公開
Y. Watanabe; N. Takagi; K. Takagi Y. Watanabe; N. Takagi; K. Takagi Y. Watanabe; N. Takagi; K. Takagi A VLSI algorithm for division in GF(2<sup>m</sup>) based on extended binary GCD algorithm A VLSI algorithm for division in GF(2<sup>m</sup>) based on extended binary GCD algorithm A VLSI algorithm for division in GF(2<sup>m</sup>) based on extended binary GCD algorithm IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E85-A,5,994-999 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E85-A,5,994-999 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E85-A,5,994-999 2002/05 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A hardware algorithm for computing reciprocal square root A hardware algorithm for computing reciprocal square root A hardware algorithm for computing reciprocal square root Proceedings - 15th Symposium on Computer Arithmetic,94-100 Proceedings - 15th Symposium on Computer Arithmetic,94-100 Proceedings - 15th Symposium on Computer Arithmetic,94-100 2001/06 英語 研究論文(国際会議プロシーディングス) 公開
N. Takagi; J.-I. Yoshiki; K. Takagi N. Takagi; J.-I. Yoshiki; K. Takagi N. Takagi; J.-I. Yoshiki; K. Takagi A fast algorithm for multiplicative inversion in GF(2 <sup>m</sup>) using normal basis A fast algorithm for multiplicative inversion in GF(2 <sup>m</sup>) using normal basis A fast algorithm for multiplicative inversion in GF(2 <sup>m</sup>) using normal basis IEEE Transactions on Computers,50,5,394-398 IEEE Transactions on Computers,50,5,394-398 IEEE Transactions on Computers,50,5,394-398 2001/05 英語 研究論文(学術雑誌) 公開
高木直史 高木直史 TAKAGI Naofumi A Digit-Recurrence Algorithm for Cube Rooting A Digit-Recurrence Algorithm for Cube Rooting A Digit-Recurrence Algorithm for Cube Rooting IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E84-A,5,1309-1314 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E84-A,5,1309-1314 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E84-A,5,1309-1314 2001/05 英語 研究論文(学術雑誌) 公開
N. Takagi; S. Kuwahara N. Takagi; S. Kuwahara N. Takagi; S. Kuwahara A VLSI algorithm for computing the Euclidean norm of a 3D vector A VLSI algorithm for computing the Euclidean norm of a 3D vector A VLSI algorithm for computing the Euclidean norm of a 3D vector IEEE Transactions on Computers,49,10,1074-1082 IEEE Transactions on Computers,49,10,1074-1082 IEEE Transactions on Computers,49,10,1074-1082 2000/10 英語 研究論文(学術雑誌) 公開
A. Higuchi; N. Takagi A. Higuchi; N. Takagi A. Higuchi; N. Takagi IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Fast addition algorithm for elliptic curve arithmetic in GF(2<sup>n</sup>) using projective coordinates Information Processing Letters,76,3,101-103 Information Processing Letters,76,3,101-103 Information Processing Letters,76,3,101-103 2000 英語 研究論文(学術雑誌) 公開
高木一義,高木直史 高木一義,高木直史 TAKAGI Kazuyoshi, TAKAGI Naofumi Minimum cut linear arrangement of p-q dgs for VLSI layout of adder trees Minimum cut linear arrangement of p-q dgs for VLSI layout of adder trees Minimum cut linear arrangement of p-q dgs for VLSI layout of adder trees IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E82-A,5,767-774 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E82-A,5,767-774 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E82-A,5,767-774 1999/05 英語 研究論文(学術雑誌) 公開
Naofumi Takagi; Seiji Kuwahara Naofumi Takagi; Seiji Kuwahara Naofumi Takagi; Seiji Kuwahara Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector Proceedings - 14th Symposium on Computer Arithmetic,86-93 Proceedings - 14th Symposium on Computer Arithmetic,86-93 Proceedings - 14th Symposium on Computer Arithmetic,86-93 1999/04 英語 研究論文(国際会議プロシーディングス) 公開
N. Takagi; T. Horiyama N. Takagi; T. Horiyama N. Takagi; T. Horiyama A high-speed reduced-size adder under left-to-right input arrival A high-speed reduced-size adder under left-to-right input arrival A high-speed reduced-size adder under left-to-right input arrival IEEE Transactions on Computers,48,1,76-80 IEEE Transactions on Computers,48,1,76-80 IEEE Transactions on Computers,48,1,76-80 1999/01 英語 研究論文(学術雑誌) 公開
高木直史 高木直史 TAKAGI Naofumi Powering by a table look-up and a multiplication with operand modification Powering by a table look-up and a multiplication with operand modification Powering by a table look-up and a multiplication with operand modification IEEE Transactions on Computers,47,11,1216-1222 IEEE Transactions on Computers,47,11,1216-1222 IEEE Transactions on Computers,47,11,1216-1222 1998/11 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E81-A,5,724-728 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E81-A,5,724-728 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E81-A,5,724-728 1998/05 英語 研究論文(学術雑誌) 公開
Naofumi Takagi Naofumi Takagi Naofumi Takagi Generating a power of an operand by a table look-up and a multiplication Generating a power of an operand by a table look-up and a multiplication Generating a power of an operand by a table look-up and a multiplication Proceedings - 13th Symposium on Computer Arithmetic,126-131 Proceedings - 13th Symposium on Computer Arithmetic,126-131 Proceedings - 13th Symposium on Computer Arithmetic,126-131 1997/07 英語 研究論文(国際会議プロシーディングス) 公開
HAMANO Takafumi, TAKAGI Naofumi, YAJIMA Shuzo, PREPARATA F. P. HAMANO Takafumi, TAKAGI Naofumi, YAJIMA Shuzo, PREPARATA F. P. HAMANO Takafumi, TAKAGI Naofumi, YAJIMA Shuzo, PREPARATA F. P. O(n)-Depth Modular Exponentiation Circuit Algorithm O(n)-Depth Modular Exponentiation Circuit Algorithm O(n)-Depth Modular Exponentiation Circuit Algorithm IEEE Transactions on Computers,46,6,701-704 IEEE Transactions on Computers,46,6,701-704 IEEE Transactions on Computers,46,6,701-704 1997/06 英語 研究論文(学術雑誌) 公開
ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification IEEE Transactions on Computers,46,4,495-498 IEEE Transactions on Computers,46,4,495-498 IEEE Transactions on Computers,46,4,495-498 1997/04 英語 研究論文(学術雑誌) 公開
ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo ITO Masayuki, TAKAGI Naofumi, YAJIMA Shuzo Square Rooting by Iterative Multiply-Additions Square Rooting by Iterative Multiply-Additions Square Rooting by Iterative Multiply-Additions Information Processing Letters,60,5,267-269 Information Processing Letters,60,5,267-269 Information Processing Letters,60,5,267-269 1997/01 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A Hardware Algorithm for Modular Division Based on the Extended Euclidean Algorithm A Hardware Algorithm for Modular Division Based on the Extended Euclidean Algorithm A Hardware Algorithm for Modular Division Based on the Extended Euclidean Algorithm IEICE Transactions on Information and Systems,E79-D,11,1518-1522 IEICE Transactions on Information and Systems,E79-D,11,1518-1522 IEICE Transactions on Information and Systems,E79-D,11,1518-1522 1996/11 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions IEICE Transactions on Information and Systems,E78-D,10,1313-1315 IEICE Transactions on Information and Systems,E78-D,10,1313-1315 IEICE Transactions on Information and Systems,E78-D,10,1313-1315 1995/10 英語 研究論文(学術雑誌) 公開
Hannes Hassler; Naofumi Takagi Hannes Hassler; Naofumi Takagi Hannes Hassler; Naofumi Takagi Function evaluation by table look-up and addition Function evaluation by table look-up and addition Function evaluation by table look-up and addition Proceedings - 12th Symposium on Computer Arithmetic,10-16 Proceedings - 12th Symposium on Computer Arithmetic,10-16 Proceedings - 12th Symposium on Computer Arithmetic,10-16 1995/07 英語 研究論文(国際会議プロシーディングス) 公開
Takafumi Hamano; Naofumi Takagi; Shuzo Yajima; Franco P. Preparata Takafumi Hamano; Naofumi Takagi; Shuzo Yajima; Franco P. Preparata Takafumi Hamano; Naofumi Takagi; Shuzo Yajima; Franco P. Preparata O(n)-depth circuit algorithm for modular exponentiation O(n)-depth circuit algorithm for modular exponentiation O(n)-depth circuit algorithm for modular exponentiation Proceedings - 12th Symposium on Computer Arithmetic,188-192 Proceedings - 12th Symposium on Computer Arithmetic,188-192 Proceedings - 12th Symposium on Computer Arithmetic,188-192 1995/07 英語 研究論文(国際会議プロシーディングス) 公開
Masayuki Ito; Naofumi Takagi; Shuzo Yajima Masayuki Ito; Naofumi Takagi; Shuzo Yajima Masayuki Ito; Naofumi Takagi; Shuzo Yajima Proceedings - 12th Symposium on Computer Arithmetic Proceedings - 12th Symposium on Computer Arithmetic Efficient initial approximation and fast converging methods for division and square root Proceedings - 12th Symposium on Computer Arithmetic,2-9 Proceedings - 12th Symposium on Computer Arithmetic,2-9 Proceedings - 12th Symposium on Computer Arithmetic,2-9 1995/07 英語 研究論文(国際会議プロシーディングス) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A Modular Inversion Hardware Algorithm with a Redundant Binary Representation A Modular Inversion Hardware Algorithm with a Redundant Binary Representation A Modular Inversion Hardware Algorithm with a Redundant Binary Representation IEICE Transactions on Information and Systems,E76-D,8,863-869 IEICE Transactions on Information and Systems,E76-D,8,863-869 IEICE Transactions on Information and Systems,E76-D,8,863-869 1993/08 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A Modular Multiplication Algorithm with Triangle Additions A Modular Multiplication Algorithm with Triangle Additions A Modular Multiplication Algorithm with Triangle Additions Proceedings - 11th Symposium on Computer Arithmetic,272-276 Proceedings - 11th Symposium on Computer Arithmetic,272-276 Proceedings - 11th Symposium on Computer Arithmetic,272-276 1993/06 英語 研究論文(国際会議プロシーディングス) 公開
TAKAGI Naofumi TAKAGI Naofumi TAKAGI Naofumi A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation IEEE Transactions on Computers,41,8,949-956 IEEE Transactions on Computers,41,8,949-956 IEEE Transactions on Computers,41,8,949-956 1992/08 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, YAJIMA Shuzo TAKAGI Naofumi, YAJIMA Shuzo TAKAGI Naofumi, YAJIMA Shuzo Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem IEEE Transactions on Computers,41,7,887-891 IEEE Transactions on Computers,41,7,887-891 IEEE Transactions on Computers,41,7,887-891 1992/07 英語 研究論文(学術雑誌) 公開
武永康彦,高木直史,矢島脩三 武永康彦,高木直史,矢島脩三 TAKENAGA Yasuhiko, TAKAGI Naofumi, YAJIMA Shuzo 連想メモリによるメモリ型並列計算モデルの計算能力 連想メモリによるメモリ型並列計算モデルの計算能力 Computational Power of a Memory-Based Parallel Computation Model with Content Addressable Memory 情報処理学会論文誌,33,4,415-422 情報処理学会論文誌,33,4,415-422 Transactions of IPSJ,33,4,415-422 1992/04 日本語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation IEEE Transactions on Computers,40,9,989-995 IEEE Transactions on Computers,40,9,989-995 IEEE Transactions on Computers,40,9,989-995 1991/09 英語 研究論文(学術雑誌) 公開
Naofumi Takagi Naofumi Takagi Naofumi Takagi Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree Proceedings of SPIE - The International Society for Optical Engineering,1566,244-251 Proceedings of SPIE - The International Society for Optical Engineering,1566,244-251 Proceedings of SPIE - The International Society for Optical Engineering,1566,244-251 1991/07 英語 研究論文(国際会議プロシーディングス) 公開
Naofumi Takagi Naofumi Takagi Naofumi Takagi A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications Proceedings - 10th Symposium on Computer Arithmetic,35-42 Proceedings - 10th Symposium on Computer Arithmetic,35-42 Proceedings - 10th Symposium on Computer Arithmetic,35-42 1991/06 英語 研究論文(国際会議プロシーディングス) 公開
高木直史,武永康彦,矢島脩三 高木直史,武永康彦,矢島脩三 TAKAGI Naofumi, TAKENAGA Yasuhiko, YAJIMA Shuzo メモリ型並列計算モデルとその計算能力 ― スーパコンピュータへの第3のアプローチ ― メモリ型並列計算モデルとその計算能力 ― スーパコンピュータへの第3のアプローチ ― A Memory-Type Parallel Computation Model and Its Computational Power - Yet Another Approach to Supercomputing 情報処理学会論文誌,31,11,1565-1571 情報処理学会論文誌,31,11,1565-1571 Transactions of IPSJ,31,11,1565-1571 1990/11 日本語 研究論文(学術雑誌) 公開
岡部寿男,高木直史,矢島脩三 岡部寿男,高木直史,矢島脩三 OKABE Yasuo, TAKAGI Naofumi, YAJIMA Shuzo 剰余数表示法を用いた初等関数計算の対数段回路アルゴリズム 剰余数表示法を用いた初等関数計算の対数段回路アルゴリズム Log Depth Circuits for Elementary Functions Using Residue Number System 電子情報通信学会論文誌,J73-D-I,9,723-728 電子情報通信学会論文誌,J73-D-I,9,723-728 Transactions of IEICE,J73-D-I,9,723-728 1990/09 日本語 研究論文(学術雑誌) 公開
高木直史,矢島脩三 高木直史,矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo オンライン誤り検出可能な高速配列型除算器 オンライン誤り検出可能な高速配列型除算器 An On-Line Error Detectable High-Speed Array Divider 電子情報通信学会論文誌,J73-D-I,2,148-153 電子情報通信学会論文誌,J73-D-I,2,148-153 Transactions of IEICE,J73-D-I,2,148-153 1990/02 日本語 研究論文(学術雑誌) 公開
越智裕之,高木直史,矢島脩三 越智裕之,高木直史,矢島脩三 OCHI Hiroyuki, TAKAGI Naofumi, YAJIMA Shuzo 共有展開に基づくベクトル計算機向き論理関数素項生成法 共有展開に基づくベクトル計算機向き論理関数素項生成法 Vector Algorithms for Generating Prime Implicants of Logic Functions Based on Consensus Expansion 電子情報通信学会論文誌,J72-D-I,9,652-659 電子情報通信学会論文誌,J72-D-I,9,652-659 Transactions of IEICE,J72-D-I,9,652-659 1989/09 日本語 研究論文(学術雑誌) 公開
Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima On-line error-detectable array divider with a redundant binary representation and a residue code. On-line error-detectable array divider with a redundant binary representation and a residue code. On-line error-detectable array divider with a redundant binary representation and a residue code. Digest of Papers - FTCS (Fault-Tolerant Computing Symposium),174-179 Digest of Papers - FTCS (Fault-Tolerant Computing Symposium),174-179 Digest of Papers - FTCS (Fault-Tolerant Computing Symposium),174-179 1988/10 英語 研究論文(学術雑誌) 公開
石浦菜岐佐,高木直史,矢島脩三 石浦菜岐佐,高木直史,矢島脩三 ISHIURA Nagisa, TAKAGI Naofumi, YAJIMA Shuzo ベクトル計算機上でのソーティング ベクトル計算機上でのソーティング Sorting on a Vector Processor 情報処理学会論文誌,29,4,378-385 情報処理学会論文誌,29,4,378-385 Transactions of IPSJ,29,4,378-385 1988/04 日本語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, OCHI Hiroyuki, YAJIMA Shuzo TAKAGI Naofumi, OCHI Hiroyuki, YAJIMA Shuzo Vector Algorithms for Generating Prime Implicants of Logic Functions Vector Algorithms for Generating Prime Implicants of Logic Functions Vector Algorithms for Generating Prime Implicants of Logic Functions Proceedings - Third International Conference on Supercomputing,3,281-287 Proceedings - Third International Conference on Supercomputing,3,281-287 Proceedings - Third International Conference on Supercomputing,3,281-287 1988 英語 研究論文(国際会議プロシーディングス) 公開
高木直史,矢島脩三 高木直史,矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic IEEE Transactions on Computers,C-36,11,1310-1317 IEEE Transactions on Computers,C-36,11,1310-1317 IEEE Transactions on Computers,C-36,11,1310-1317 1987/11 英語 研究論文(学術雑誌) 公開
大久保雅且,安浦寛人,高木直史,矢島脩三 大久保雅且,安浦寛人,高木直史,矢島脩三 OHKUBO Masaaki, YASUURA Hiroto, TAKAGI Naofumi, YAJIMA Shuzo 連想メモリを利用したハードウェア向き単一化アルゴリズム 連想メモリを利用したハードウェア向き単一化アルゴリズム A Hardware-Oriented Unification Algorithm Using a Cotent Addressable Memory 情報処理学会論文誌,28,9,915-922 情報処理学会論文誌,28,9,915-922 Transactions of IPSJ,28,9,915-922 1987/09 日本語 研究論文(学術雑誌) 公開
Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. Proceedings - Symposium on Computer Arithmetic,80-86 Proceedings - Symposium on Computer Arithmetic,80-86 Proceedings - Symposium on Computer Arithmetic,80-86 1987/05 英語 研究論文(国際会議プロシーディングス) 公開
安浦寛人,高木直史,矢島脩三 安浦寛人,高木直史,矢島脩三 Hiroto Yasuura; Naofumi Takagi; Shuzo Tajima 冗長符号化を利用した高速並列アルゴリズムについて 冗長符号化を利用した高速並列アルゴリズムについて ON HIGH-SPEED PARALLEL ALGORITHMS USING REDUNDANT CODING. 電子情報通信学会論文誌,J70-D,3,525-533 電子情報通信学会論文誌,J70-D,3,525-533 Systems and Computers in Japan,J70-D,3,525-533 1987/03 日本語 研究論文(学術雑誌) 公開
HARATA Y., NAKAMURA Y., NAGASE H., TAKIGAWA M., TAKAGI Naofumi HARATA Y., NAKAMURA Y., NAGASE H., TAKIGAWA M., TAKAGI Naofumi HARATA Y., NAKAMURA Y., NAGASE H., TAKIGAWA M., TAKAGI Naofumi A High-Speed Multiplier Using a Redundant Binary Adder Tree A High-Speed Multiplier Using a Redundant Binary Adder Tree A High-Speed Multiplier Using a Redundant Binary Adder Tree IEEE Journal of Solid-State Circuits,22,1,28-34 IEEE Journal of Solid-State Circuits,22,1,28-34 IEEE Journal of Solid-State Circuits,22,1,28-34 1987/02 英語 研究論文(学術雑誌) 公開
高木直史,浅田徹,矢島脩三 高木直史,浅田徹,矢島脩三 TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo 冗長2進表現を利用した正弦・余弦計算用ハードウェアアルゴリズム 冗長2進表現を利用した正弦・余弦計算用ハードウェアアルゴリズム A Hardware Algorithm for Computing Sine and Cosine Using Redundant Binary Representation 電子通信学会論文誌,J69-D,6,841-847 電子通信学会論文誌,J69-D,6,841-847 Transactions of IECE,J69-D,6,841-847 1986/06 日本語 研究論文(学術雑誌) 公開
高木直史,矢島脩三 高木直史,矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo 冗長2進表現を利用した開平用ハードウェアアルゴリズム 冗長2進表現を利用した開平用ハードウェアアルゴリズム A Square Root Hardware Algorithm Using Redundant Binary Representation 電子通信学会論文誌,J69-D,1,1-10 電子通信学会論文誌,J69-D,1,1-10 Transactions of IECE,J69-D,1,1-10 1986/01 日本語 研究論文(学術雑誌) 公開
高木直史,矢島脩三 高木直史,矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo 冗長2進表現を利用した指数・対数関数計算用ハードウェアアルゴリズム 冗長2進表現を利用した指数・対数関数計算用ハードウェアアルゴリズム Hardware Algorithms for Computing Expornentials and Logarithms Using Redundant Binary Representation 電子通信学会論文誌,J69-D,1,11-20 電子通信学会論文誌,J69-D,1,11-20 Transactions of IECE,J69-D,1,11-20 1986/01 日本語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree IEEE Transactions on Computers,34,9,789-796 IEEE Transactions on Computers,34,9,789-796 IEEE Transactions on Computers,34,9,789-796 1985/09 英語 研究論文(学術雑誌) 公開
TAKAGI Naofumi, WONG C. K. TAKAGI Naofumi, WONG C. K. TAKAGI Naofumi, WONG C. K. A Hardware Sort-Merge System A Hardware Sort-Merge System A Hardware Sort-Merge System IBM Journal of Research and Development,29,1,49-67 IBM Journal of Research and Development,29,1,49-67 IBM Journal of Research and Development,29,1,49-67 1985/01 英語 研究論文(大学、研究機関紀要) 公開
Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. Proceedings - IEEE International Symposium on Circuits and Systems,1321-1324 Proceedings - IEEE International Symposium on Circuits and Systems,1321-1324 Proceedings - IEEE International Symposium on Circuits and Systems,1321-1324 1985 英語 研究論文(国際会議プロシーディングス) 公開
HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi High Speed Multiplier Using Redundant Binary Adder Tree High Speed Multiplier Using Redundant Binary Adder Tree High Speed Multiplier Using Redundant Binary Adder Tree Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84),165-170 Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84),165-170 Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84),165-170 1984/10 英語 研究論文(国際会議プロシーディングス) 公開
高木直史、安浦寛人,泰間健司,早田宏、矢島脩三 高木直史、安浦寛人,泰間健司,早田宏、矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, TAIMA Kenji, HAYATA Hiroshi, YAJIMA Shuzo 並列計数ソ―ティング回路の試作と評価 並列計数ソ―ティング回路の試作と評価 An Implementation and Evaluation of the Parallell Enumeration Sorting Circuit 電子通信学会論文誌,J67-D,5,623-624 電子通信学会論文誌,J67-D,5,623-624 Transactions of IECE,J67-D,5,623-624 1984/05 日本語 研究論文(学術雑誌) 公開
高木直史,安浦寛人,矢島脩三 高木直史,安浦寛人,矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, YAJIMA SHUZO 冗長2進表現を利用したVLSI向き高速除算器 冗長2進表現を利用したVLSI向き高速除算器 A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation 電子通信学会論文誌,J67-D,4,450-457 電子通信学会論文誌,J67-D,4,450-457 Transactions of IECE,J67-D,4,450-457 1984/04 日本語 研究論文(学術雑誌) 公開
高木直史,安浦寛人,矢島脩三 高木直史,安浦寛人,矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo 冗長2進加算木を用いたVLSI向き高速乗算器 冗長2進加算木を用いたVLSI向き高速乗算器 A VLSI-Oriented High-Speed Multiplier Using a Redandant Binary Addition Tree 電子通信学会論文誌,J66-D,6,683-690 電子通信学会論文誌,J66-D,6,683-690 Transaction of IECE,J66-D,6,683-690 1983/06 日本語 研究論文(学術雑誌) 公開
安浦寛人,高木直史,矢島脩三 安浦寛人,高木直史,矢島脩三 YASUURA Hiroto, TAKAGI Naofumi, YAJIMA Shuzo The parallel enumeration sorting scheme for VLSI The parallel enumeration sorting scheme for VLSI The Parallel Enumeration Sorting Scheme for VLSI IEEE Transactions on Computers,31,12,1192-1201 IEEE Transactions on Computers,31,12,1192-1201 IEEE Transactions on Computers,31,12,1192-1201 1982/12 英語 研究論文(学術雑誌) 公開
安浦寛人、高木直史 安浦寛人、高木直史 YASUURA Hiroto, TAKAGI Naofumi 並列計数法による高速ソーティング回路 並列計数法による高速ソーティング回路 A High-Speed Sorting Circuit Using Parallel Enumeration Sort 電子通信学会論文誌,J65-D,2,179-186 電子通信学会論文誌,J65-D,2,179-186 Transactions of IECE,J65-D,2,179-186 1982/02 日本語 研究論文(学術雑誌) 公開
Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima On-line error-detectable high-speed array divider On-line error-detectable high-speed array divider Systems and Computers in Japan,22,1,21-27 ,22,1,21-27 Systems and Computers in Japan,22,1,21-27 1991 英語 公開
Yasuo Okabe; Naofumi Takagi; Shuzo Yajima Yasuo Okabe; Naofumi Takagi; Shuzo Yajima Log-depth circuits for elementary functions using residue number system Log-depth circuits for elementary functions using residue number system Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi),74,8,31-38 ,74,8,31-38 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi),74,8,31-38 1991 英語 公開
Naofumi Takagi; Shuzo Yajima Naofumi Takagi; Shuzo Yajima SQUARE ROOT HARDWARE ALGORITHM USING REDUNDANT BINARY REPRESENTATION. SQUARE ROOT HARDWARE ALGORITHM USING REDUNDANT BINARY REPRESENTATION. Systems and Computers in Japan,17,11,30-41 ,17,11,30-41 Systems and Computers in Japan,17,11,30-41 1986 英語 公開
Naofumi Takagi; Hiroto Yasuura; Shuzo Yajima Naofumi Takagi; Hiroto Yasuura; Shuzo Yajima VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE. VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE. Systems, computers, controls,14,4,19-28 ,14,4,19-28 Systems, computers, controls,14,4,19-28 1983 英語 公開

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藤巻朗,佐藤諒,畑中湧貴,赤池宏之,高木一義,高木直史,田中雅光 藤巻朗,佐藤諒,畑中湧貴,赤池宏之,高木一義,高木直史,田中雅光 FUJIMAKI Akira, SATO Ryo, HATANAKA Yuki, AKAIKE Hiroyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi, TANAKA Masamitsu Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories 10th Superconducting SFQ VLSI Workshop (SSV 2017),22-24 10th Superconducting SFQ VLSI Workshop (SSV 2017),22-24 10th Superconducting SFQ VLSI Workshop (SSV 2017),22-24 2017/02 英語 研究論文 公開
高木直史,高木一義,鬼頭信貴 高木直史,高木一義,鬼頭信貴 TAKAGI Naofumi, TAKAGI Kazuyoshi, KITO Nobutaka Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors 10th Superconducting SFQ VLSI Workshop (SSV 2017),30-33 10th Superconducting SFQ VLSI Workshop (SSV 2017),30-33 10th Superconducting SFQ VLSI Workshop (SSV 2017),30-33 2017/02 英語 研究論文 公開
鬼頭信貴,高木一義,高木直史 鬼頭信貴,高木一義,高木直史 KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi Fast length-matching routing for rapid single flux quantum circuits Fast length-matching routing for rapid single flux quantum circuits Fast length-matching routing for rapid single flux quantum circuits The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (SASIMI2016),135-149 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (SASIMI2016),135-149 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016),135-149 2016/10 英語 研究論文 公開
川口隆弘,高木一義,高木直史 川口隆弘,高木一義,高木直史 KAWAGUCHI Takahiro, TAKAGI KAzuyoshi, TAKAGI Naofumi Static timing analysis of rapid single-flux-quantum circuits Static timing analysis of rapid single-flux-quantum circuits Static timing analysis of rapid single-flux-quantum circuits The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016),341-345 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016),341-345 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016),341-345 2016/10 英語 研究論文 公開
佐藤諒,田中雅光,畑中湧貴,藤巻朗,赤池宏之,高木直史,高木一義 佐藤諒,田中雅光,畑中湧貴,藤巻朗,赤池宏之,高木直史,高木一義 SATO Ryo, TANAKA Masamitsu, HATANAKA Yuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, TAKAGI Kazuyoshi Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs 9th Superconducting SFQ VLSI Workshop (SSV 2016),26-30 9th Superconducting SFQ VLSI Workshop (SSV 2016),26-30 9th Superconducting SFQ VLSI Workshop (SSV 2016),26-30 2016/08 英語 研究論文 公開
唐光明,高木一義,高木直史 唐光明,高木一義,高木直史 Tang Guanming, TAKAGI Kazuyoshi, TAKAGI Naofumi A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor 9th Superconducting SFQ VLSI Workshop (SSV 2016),31-35 9th Superconducting SFQ VLSI Workshop (SSV 2016),31-35 9th Superconducting SFQ VLSI Workshop (SSV 2016),31-35 2016/08 英語 研究論文 公開
鬼頭信貴,松本弦篤,高木一義,高木直史 鬼頭信貴,松本弦篤,高木一義,高木直史 KITO Nobutaka, MATSUMOTO Gentoku, TAKAGI Kazuyoshi, TAKAGI Naofumi Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits 9th Superconducting SFQ VLSI Workshop (SSV 2016),86-89 9th Superconducting SFQ VLSI Workshop (SSV 2016),86-89 9th Superconducting SFQ VLSI Workshop (SSV 2016),86-89 2016/08 英語 研究論文 公開
大畑真也 植田慶太 高木一義 高木直史 大畑真也 植田慶太 高木一義 高木直史 OHATA Masaya, UEDA Keita, TAKAGI Kazuyoshi, TAKAGI Naofumi Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits 8th Superconducting SFQ VLSI Workshop (SSV 2015),140-143 8th Superconducting SFQ VLSI Workshop (SSV 2015),140-143 8th Superconducting SFQ VLSI Workshop (SSV 2015),140-143 2015/07 英語 研究論文 公開
M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing 7th Superconducting SFQ VLSI Workshop (SSV 2014),2-7 7th Superconducting SFQ VLSI Workshop (SSV 2014),2-7 7th Superconducting SFQ VLSI Workshop (SSV 2014),2-7 2014/12 英語 研究論文 公開
G. Tang, K. Takagi, N. Takagi G. Tang, K. Takagi, N. Takagi G. Tang, K. Takagi, N. Takagi Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors 7th Superconducting SFQ VLSI Workshop (SSV 2014),39-44 7th Superconducting SFQ VLSI Workshop (SSV 2014),39-44 7th Superconducting SFQ VLSI Workshop (SSV 2014),39-44 2014/12 英語 研究論文 公開
M. Moriya, K. Takagi, N. Takagi M. Moriya, K. Takagi, N. Takagi M. Moriya, K. Takagi, N. Takagi Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates 7th Superconducting SFQ VLSI Workshop (SSV 2014),67-71 7th Superconducting SFQ VLSI Workshop (SSV 2014),67-71 7th Superconducting SFQ VLSI Workshop (SSV 2014),67-71 2014/12 英語 研究論文 公開
K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi Demonstration of 4-Bit-Parallel Bit-Slice ALU Demonstration of 4-Bit-Parallel Bit-Slice ALU Demonstration of 4-Bit-Parallel Bit-Slice ALU 7th Superconducting SFQ VLSI Workshop (SSV 2014),84-89 7th Superconducting SFQ VLSI Workshop (SSV 2014),84-89 7th Superconducting SFQ VLSI Workshop (SSV 2014),84-89 2014/12 英語 研究論文 公開
R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 7th Superconducting SFQ VLSI Workshop (SSV 2014),90-93 7th Superconducting SFQ VLSI Workshop (SSV 2014),90-93 7th Superconducting SFQ VLSI Workshop (SSV 2014),90-93 2014/12 英語 研究論文 公開
R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi Design of Shift-Register Memories for SFQ Micro Processors COREe Design of Shift-Register Memories for SFQ Micro Processors COREe Design of Shift-Register Memories for SFQ Micro Processors COREe 7th Superconducting SFQ VLSI Workshop (SSV 2014),105-107 7th Superconducting SFQ VLSI Workshop (SSV 2014),105-107 7th Superconducting SFQ VLSI Workshop (SSV 2014),105-107 2014/12 英語 研究論文 公開
Y. Ando, M. Tanaka, K. Takagi, N. Takagi Y. Ando, M. Tanaka, K. Takagi, N. Takagi Y. Ando, M. Tanaka, K. Takagi, N. Takagi Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers 7th Superconducting SFQ VLSI Workshop (SSV 2014),111-115 7th Superconducting SFQ VLSI Workshop (SSV 2014),111-115 7th Superconducting SFQ VLSI Workshop (SSV 2014),111-115 2014/12 英語 研究論文 公開
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi PTL Routing Environment for SFQ Circuits Using a Commercial Router PTL Routing Environment for SFQ Circuits Using a Commercial Router PTL Routing Environment for SFQ Circuits Using a Commercial Router 7th Superconducting SFQ VLSI Workshop (SSV 2014),143-146 7th Superconducting SFQ VLSI Workshop (SSV 2014),143-146 7th Superconducting SFQ VLSI Workshop (SSV 2014),143-146 2014/12 英語 研究論文 公開
N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi Retiming of SFQ Logic Circuits for Reduction of Flip-Flops Retiming of SFQ Logic Circuits for Reduction of Flip-Flops Retiming of SFQ Logic Circuits for Reduction of Flip-Flops 6th Superconducting SFQ VLSI Workshop (SSV 2013),13-18 6th Superconducting SFQ VLSI Workshop (SSV 2013),13-18 6th Superconducting SFQ VLSI Workshop (SSV 2013),13-18 2013/11 英語 研究論文 公開
M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors 6th Superconducting SFQ VLSI Workshop (SSV 2013),19-22 6th Superconducting SFQ VLSI Workshop (SSV 2013),19-22 6th Superconducting SFQ VLSI Workshop (SSV 2013),19-22 2013/11 英語 研究論文 公開
Y. Ohmomo, K. Takagi, N. Takagi Y. Ohmomo, K. Takagi, N. Takagi Y. Ohmomo, K. Takagi, N. Takagi Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors 6th Superconducting SFQ VLSI Workshop (SSV 2013),117-122 6th Superconducting SFQ VLSI Workshop (SSV 2013),117-122 6th Superconducting SFQ VLSI Workshop (SSV 2013),117-122 2013/11 英語 研究論文 公開
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi A Design Framework for SFQ Circuits Using Clockless Gates A Design Framework for SFQ Circuits Using Clockless Gates A Design Framework for SFQ Circuits Using Clockless Gates 6th Superconducting SFQ VLSI Workshop (SSV 2013),123-127 6th Superconducting SFQ VLSI Workshop (SSV 2013),123-127 6th Superconducting SFQ VLSI Workshop (SSV 2013),123-127 2013/11 英語 研究論文 公開
KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),220-225 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),220-225 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),220-225 2013/10 英語 研究論文 公開
SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),322-327 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),322-327 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013),322-327 2013/10 英語 研究論文 公開
T. Kawaguchi, k. Takagi, N. Takagi T. Kawaguchi, k. Takagi, N. Takagi T. Kawaguchi, k. Takagi, N. Takagi A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits 5th Superconducting SFQ VLSI Workshop (SSV 2012),33-36 5th Superconducting SFQ VLSI Workshop (SSV 2012),33-36 5th Superconducting SFQ VLSI Workshop (SSV 2012),33-36 2012/12 英語 研究論文 公開
T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process 5th Superconducting SFQ VLSI Workshop (SSV 2012),45-47 5th Superconducting SFQ VLSI Workshop (SSV 2012),45-47 5th Superconducting SFQ VLSI Workshop (SSV 2012),45-47 2012/12 英語 研究論文 公開
M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation 5th Superconducting SFQ VLSI Workshop (SSV 2012),118-121 5th Superconducting SFQ VLSI Workshop (SSV 2012),118-121 5th Superconducting SFQ VLSI Workshop (SSV 2012),118-121 2012/12 英語 研究論文 公開
X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process 5th Superconducting SFQ VLSI Workshop (SSV 2012),152-154 5th Superconducting SFQ VLSI Workshop (SSV 2012),152-154 5th Superconducting SFQ VLSI Workshop (SSV 2012),152-154 2012/12 英語 研究論文 公開
Y. Hayakawa, K. Takata,M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Y. Hayakawa, K. Takata,M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Y. Hayakawa, K. Takata,M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Low Frequency Test of 4x4 Reconfigurable Data-Path Processors Low Frequency Test of 4x4 Reconfigurable Data-Path Processors Low Frequency Test of 4x4 Reconfigurable Data-Path Processors 5th Superconducting SFQ VLSI Workshop (SSV 2012),162-165 5th Superconducting SFQ VLSI Workshop (SSV 2012),162-165 5th Superconducting SFQ VLSI Workshop (SSV 2012),162-165 2012/12 英語 研究論文 公開
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),319-324 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),319-324 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),319-324 2012/03 英語 研究論文 公開
Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),106-110 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),106-110 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012),106-110 2012/03 英語 研究論文 公開
K. Takagi, N. Takagi K. Takagi, N. Takagi K. Takagi, N. Takagi Design Algorithms for Superconducting SFQ Logic Circuits Design Algorithms for Superconducting SFQ Logic Circuits Design Algorithms for Superconducting SFQ Logic Circuits 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 英語 研究論文 公開
N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 英語 研究論文 公開
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi Design of SFQ Circuits Using Clockless Logic Gates Design of SFQ Circuits Using Clockless Logic Gates Design of SFQ Circuits Using Clockless Logic Gates 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 英語 研究論文 公開
Kazuyoshi Takagi, Motoki Sato Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Motoki Sato Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Motoki Sato Masamitsu Tanaka, Naofumi Takagi A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),208-213 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),208-213 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),208-213 2010/10 英語 研究論文 公開
Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),42-47 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),42-47 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010),42-47 2010/10 英語 研究論文 公開
K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi Timing Optimization Methods for Superconducting SFQ Circuits Timing Optimization Methods for Superconducting SFQ Circuits Timing Optimization Methods for Superconducting SFQ Circuits 3rd Superconducting SFQ VLSI Workshop (SSV 2010),21-24 3rd Superconducting SFQ VLSI Workshop (SSV 2010),21-24 3rd Superconducting SFQ VLSI Workshop (SSV 2010),21-24 2010/01 英語 研究論文 公開
M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers 3rd Superconducting SFQ VLSI Workshop (SSV 2010),53-54 3rd Superconducting SFQ VLSI Workshop (SSV 2010),53-54 3rd Superconducting SFQ VLSI Workshop (SSV 2010),53-54 2010/01 英語 研究論文 公開
M. Sato, M. Tanaka, K. Takagi, N. Takagi M. Sato, M. Tanaka, K. Takagi, N. Takagi M. Sato, M. Tanaka, K. Takagi, N. Takagi A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae 3rd Superconducting SFQ VLSI Workshop (SSV 2010),81-85 3rd Superconducting SFQ VLSI Workshop (SSV 2010),81-85 3rd Superconducting SFQ VLSI Workshop (SSV 2010),81-85 2010/01 英語 研究論文 公開
KOBAYASHI Katsuki, TAKAGI Naofumi KOBAYASHI Katsuki, TAKAGI Naofumi KOBAYASHI Katsuki, TAKAGI Naofumi Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),94-99 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),94-99 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),94-99 2009/03 英語 研究論文 公開
KAWASHIMA Hirotaka, TAKAGI Naofumi KAWASHIMA Hirotaka, TAKAGI Naofumi KAWASHIMA Hirotaka, TAKAGI Naofumi Small Area Multipliers Utilizing the Sum of Operands Small Area Multipliers Utilizing the Sum of Operands Small Area Multipliers Utilizing the Sum of Operands Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),189-194 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),189-194 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009),189-194 2009/03 英語 研究論文 公開
N. Takagi N. Takagi N. Takagi Multiple-valued-digit number representations in arithmetic circuit algorithms Multiple-valued-digit number representations in arithmetic circuit algorithms Multiple-valued-digit number representations in arithmetic circuit algorithms Proceedings of The International Symposium on Multiple-Valued Logic,224-235 Proceedings of The International Symposium on Multiple-Valued Logic,224-235 Proceedings of The International Symposium on Multiple-Valued Logic,224-235 2002/05 英語 公開

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タイトル言語:
講演・口頭発表等
タイトル タイトル(日本語) タイトル(英語) 会議名 会議名(日本語) 会議名(英語) 主催者 主催者(日本語) 主催者(英語) 開催年月日 記述言語 会議種別 公開
Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors The 10th Superconducting SFQ VLSI Workshop (SSV 2017) The 10th Superconducting SFQ VLSI Workshop (SSV 2017) The 10th Superconducting SFQ VLSI Workshop (SSV 2017) 2017/02/20 英語 口頭発表(一般) 公開
Research Results of CREST-JST SFQ-RDP Project and Future Issues Research Results of CREST-JST SFQ-RDP Project and Future Issues Research Results of CREST-JST SFQ-RDP Project and Future Issues The 6th Superconducting SFQ VLSI Workshop (SSV 2013) The 6th Superconducting SFQ VLSI Workshop (SSV 2013) The 6th Superconducting SFQ VLSI Workshop (SSV 2013) JST-ALCA SFQ Project and MEXT SFQ Project JST-ALCA SFQ Project and MEXT SFQ Project 2013/11/22 英語 口頭発表(招待・特別) 公開
An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits 24th International Symposium on Superconductivity 24th International Symposium on Superconductivity 24th International Symposium on Superconductivity International Superconductivity Technology Center (ISTEC) International Superconductivity Technology Center (ISTEC) 2011/10/26 英語 口頭発表(招待・特別) 公開
タイトル言語:
書籍等出版物
著者 著者(日本語) 著者(英語) タイトル タイトル(日本語) タイトル(英語) 出版社 出版社(日本語) 出版社(英語) 出版年月 記述言語 担当区分 公開
高木直史、磯直行 高木直史、磯直行 TAKAGI Naofumi, ISO Naoyuki 新インターユニバーシティ 論理回路 新インターユニバーシティ 論理回路 New Inter-University Logic Circuits オーム社 オーム社 Ohmsha 2010/12 日本語 分担執筆 公開
高木 直史 高木 直史 TAKAGI Naofumi 算術演算のVLSIアルゴリズム 算術演算のVLSIアルゴリズム VLSI Algorithms for Arithmetic Operations コロナ社 コロナ社 Corona Publishing Co., LTD 2005/03 単著 公開
CHEN Waikai Ed., MUROGA Saburo, TAKAGI Naofumi, et al CHEN Waikai Ed., MUROGA Saburo, TAKAGI Naofumi, et al CHEN Waikai Ed., MUROGA Saburo, TAKAGI Naofumi, et al The VLSI Handbook The VLSI Handbook The VLSI Handbook CRC Press (with IEEE Press) CRC Press (with IEEE Press) CRC Press (with IEEE Press) 2000 共著 公開
稲垣康善、高木直史、林照峯、直井徹 稲垣康善、高木直史、林照峯、直井徹 INAGAKI Yasuyoshi, TAKAGI Naofumi, HAYASHI Terumine, NAOI Tohru インターユニバーシティ 論理回路とオートマトン インターユニバーシティ 論理回路とオートマトン Inter-University Logic Circuits and Automata オーム社 オーム社 Ohmsha 1998/01 分担執筆 公開
高木 直史 高木 直史 TAKAGI Naofumi New Text 電子情報系シリーズ 論理回路 New Text 電子情報系シリーズ 論理回路 Logic Circuits 昭晃堂 昭晃堂 Shokodo 1997/04 単著 公開
池田克夫、柴山潔、高木直史他 池田克夫、柴山潔、高木直史他 IKEDA Katsuo, SHIBAYAMA Kiyoshi, TAKAGI Naofumi, et al 情報工学実験 (新コンピュータサイエンス講座) 情報工学実験 (新コンピュータサイエンス講座) Experiments in Information Engineering オーム社 オーム社 1993/03 分担執筆 公開
タイトル言語:
特許
発明者 発明者(日本語) 発明者(英語) 発明の名称 発明の名称(日本語) 発明の名称(英語) 審査の段階 番号 年月 公開
並列係数ソーティング回路 並列係数ソーティング回路 公開
Arithmetic processor and multiplier using redundant signed digit arithmetic Arithmetic processor and multiplier using redundant signed digit arithmetic 公開
Arithmetic processor and divider using redundant signed digit Arithmetic processor and divider using redundant signed digit 公開
Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands 公開
High speed multiplier utilizing signed-digit and carry-save operands High speed multiplier utilizing signed-digit and carry-save operands 公開
Arithmetic processor using singed-digit representation of internal operands Arithmetic processor using singed-digit representation of internal operands 公開
Arithmetic processor using signed-digit representation of external operands Arithmetic processor using signed-digit representation of external operands 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
演算処理装置 演算処理装置 公開
加算装置 加算装置 公開
Method and hardware for computing reciprocal square root and program for the same Method and hardware for computing reciprocal square root and program for the same 公開
平方根の逆数計算方法、計算回路、及びプログラム 平方根の逆数計算方法、計算回路、及びプログラム 公開
剰余系の計算方法及び装置並びにプログラム 剰余系の計算方法及び装置並びにプログラム 公開
再構成可能データパスプロセッサ 再構成可能データパスプロセッサ 公開
剰余系の計算方法及び装置 剰余系の計算方法及び装置 公開
Arithmetic processor and multiplier using redundant signed digit arithmetic Arithmetic processor and multiplier using redundant signed digit arithmetic 公開
Arithmetic processor and divider using redundant signed digit Arithmetic processor and divider using redundant signed digit 公開
Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands 公開
High speed multiplier utilizing signed-digit and carry-save operands High speed multiplier utilizing signed-digit and carry-save operands 公開
Arithmetic processor using singed-digit representation of internal operands Arithmetic processor using singed-digit representation of internal operands 公開
Arithmetic processor using signed-digit representation of external operands Arithmetic processor using signed-digit representation of external operands 公開
Method and hardware for computing reciprocal square root and program for the same Method and hardware for computing reciprocal square root and program for the same 公開

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タイトル言語:
学術賞等
賞の名称(日本語) 賞の名称(英語) 授与組織名(日本語) 授与組織名(英語) 年月
Best Paper Award of 7th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005) Organizing Committee of CHES2005 2005/09/
平成17年度科学技術分野の文部科学大臣表彰 研究部門 文部科学省 2005/04/
第9回 日本IBM科学賞 日本アイ・ビー・エム 1995/11/
情報処理学会 第3回(平成6年度)坂井記念特別賞 情報処理学会 1995/05/
第9回 電気通信普及財団 テレコムシステム技術賞 奨励賞 電気通信普及財団 1994/03/
電子情報通信学会 第6回(平成2年度)篠原記念学術奨励賞 電子情報通信学会 1991/03/
情報処理学会 1988年度論文賞 情報処理学会 1989/05/
電子情報通信学会 1987年度論文賞 電子情報通信学会 1988/05/
Outstanding Paper Award of IEEE International Conference on Computer Design (ICCD'84) Organizing Committee of ICCD'84 1984/11/
Meritorious Service Certificate IEEE Computer Society 2014/04/
Sevice Award ACM 2017/04/
功労賞 電子情報通信学会 基礎・境界ソサイエティ 2017/09/

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外部資金:競争的資金・科学研究費補助金
種別 代表/分担 テーマ(日本語) テーマ(英語) 期間
基盤研究(B) 代表 テスト容易な演算回路の自動合成に関する研究 Research on synthesis of easily-testable arithmetic circuits 2008/04/01〜2011/03/31
基盤研究(B) 代表 データ表現の工夫による高性能・高信頼浮動小数点演算器アレイに関する研究      Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation 2012/04/01〜2015/03/31
基盤研究(B) 代表 浮動小数点関数計算のハードウェアアシストに関する研究 Research on hardware-asist for computation of floating-point functions 2016/04/01〜2020/03/31
基盤研究(B) 代表 浮動小数点関数計算のハードウェアアシストに関する研究 (平成29年度分) 2017/04/01〜2018/03/31
外部資金:競争的資金・科学研究費補助金以外
制度名 代表者名 研究課題(日本語) 研究課題(英語) 期間
JST-CREST 高木直史 単一磁束量子回路による再構成可能な低電力高性能プロセッサ/単一磁束量子論理回路設計及び設計支援技術の開発 Low-power, high-performance, reconfigurable processor using single-flux-quantum circuits / Development of logic design method and design autmation technologies of single-flax-quantum logic circuits 2006/10/〜2013/03/31
JST-ALCA 高木直史 低エネルギー情報ネットワーク用光・磁気・超伝道融合システム/超伝導回路設計用CADの開発 Superconductor Electronic System Combined with Optics and Spintronics / Development of CAD for Superconductive Digital Circuits 2011/10/01〜2017/03/31
担当科目
講義名(日本語) 講義名(英語) 開講期 学部/研究科 年度
Advanced Study in CCE II 通年 情報学研究科 2011/04〜2012/03
通信情報システム特別研究1 通年 情報学研究科 2011/04〜2012/03
通信情報システム特別研究2 通年 情報学研究科 2011/04〜2012/03
Advanced Study in CCE I 通年 情報学研究科 2011/04〜2012/03
計算機アーキテクチャ1(計算機) 後期 工学部 2011/04〜2012/03
計算機アーキテクチャ2(計算機) 前期 工学部 2011/04〜2012/03
論理回路(計算機) 前期 工学部 2011/04〜2012/03
情報と職業 前期 工学部 2011/04〜2012/03
特別研究1(16年以降入学者)(計算機) 前期集中 工学部 2011/04〜2012/03
特別研究1(16年以降入学者)(計算機) 後期集中 工学部 2011/04〜2012/03
特別研究2(16年以降入学者)(計算機) 前期集中 工学部 2011/04〜2012/03
特別研究2(16年以降入学者)(計算機) 後期集中 工学部 2011/04〜2012/03
特別研究1(15年以前入学者)(計算機) 前期集中 工学部 2011/04〜2012/03
特別研究1(15年以前入学者)(計算機) 後期集中 工学部 2011/04〜2012/03
特別研究2(15年以前入学者)(計算機) 前期集中 工学部 2011/04〜2012/03
特別研究2(15年以前入学者)(計算機) 後期集中 工学部 2011/04〜2012/03
並列計算機アーキテクチャ 前期 情報学研究科 2011/04〜2012/03
ハードウェアアリゴリズム 後期 情報学研究科 2011/04〜2012/03
ハードウェアアリゴリズム Hardware Algorithm 後期 情報学研究科 2012/04〜2013/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2012/04〜2013/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2012/04〜2013/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2012/04〜2013/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2012/04〜2013/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2012/04〜2013/03
論理回路 Logic Circuits 前期 工学部 2012/04〜2013/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2012/04〜2013/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2012/04〜2013/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2013/04〜2014/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2013/04〜2014/03
論理回路 Logic Circuits 前期 工学部 2013/04〜2014/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2013/04〜2014/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2013/04〜2014/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2013/04〜2014/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2013/04〜2014/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2014/04〜2015/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2014/04〜2015/03
論理回路 Logic Circuits 前期 工学部 2014/04〜2015/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2014/04〜2015/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04〜2015/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04〜2015/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2014/04〜2015/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2014/04〜2015/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2014/04〜2015/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2014/04〜2015/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2014/04〜2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04〜2015/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04〜2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04〜2016/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04〜2016/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2015/04〜2016/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2015/04〜2016/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2015/04〜2016/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2015/04〜2016/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2015/04〜2016/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2015/04〜2016/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2015/04〜2016/03
論理回路 Logic Circuits 前期 工学部 2015/04〜2016/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2015/04〜2016/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04〜2016/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04〜2016/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04〜2017/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04〜2017/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2016/04〜2017/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2016/04〜2017/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2016/04〜2017/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2016/04〜2017/03
計算機の構成 Computer organization 後期 工学部 2016/04〜2017/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2016/04〜2017/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2016/04〜2017/03
論理システム Logical Systems 前期 工学部 2016/04〜2017/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2016/04〜2017/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 後期集中 情報学研究科 2016/04〜2017/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04〜2017/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04〜2017/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04〜2018/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04〜2018/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2017/04〜2018/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2017/04〜2018/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2017/04〜2018/03
計算機の構成 Computer organization 後期 工学部 2017/04〜2018/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2017/04〜2018/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2017/04〜2018/03
論理システム Logical Systems 前期 工学部 2017/04〜2018/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2017/04〜2018/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 前期集中 情報学研究科 2017/04〜2018/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04〜2018/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04〜2018/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年集中 情報学研究科 2018/04〜2019/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2018/04〜2019/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2018/04〜2019/03
情報と職業 Information and Business 前期 工学部 2018/04〜2019/03
特別研究1 Graduation Thesis 1 前期集中 工学部 2018/04〜2019/03
特別研究1 Graduation Thesis 1 後期集中 工学部 2018/04〜2019/03
特別研究2 Graduation Thesis 2 前期集中 工学部 2018/04〜2019/03
特別研究2 Graduation Thesis 2 後期集中 工学部 2018/04〜2019/03
計算機の構成 Computer organization 後期 工学部 2018/04〜2019/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2018/04〜2019/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2018/04〜2019/03
論理システム Logical Systems 前期 工学部 2018/04〜2019/03

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全学運営(役職等)
役職名 期間
教育用計算機専門委員会 委員 2011/07/01〜2012/03/31
京都大学情報環境整備委員会 委員 2014/10/01〜2015/03/31
教育用計算機専門委員会 委員長 2014/10/01〜
京都大学情報環境整備委員会 委員 2015/04/01〜2016/09/30
情報環境機構 副機構長 2014/10/01〜
京都大学情報環境整備委員会 委員 2016/10/01〜2018/09/30
部局運営(役職等)
役職名 期間
教務委員会委員 2011/04/01〜2012/03/31
専攻長会議 2012/04/01〜2013/03/31
制規委員会委員 2012/04/01〜2013/03/31
情報セキュリティ委員会委員 2012/04/01〜2013/03/31
教務委員会委員 2013/04/01〜2014/03/31
財務委員会委員長 2014/04/01〜2017/03/31
財務委員会委員 2017/04/01〜2018/03/31
企画委員会委員 2018/04/01〜2019/03/33
情報学科長 2018/04/01〜2019/03/31