橋本 昌宜

Last Update: 2021/11/23 18:06:02

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Name(Kanji/Kana/Abecedarium Latinum)
橋本 昌宜/ハシモト マサノリ/Hashimoto, Masanori
Primary Affiliation(Org1/Job title)
Graduate School of Informatics/Professor
Faculty
Org1 Job title
工学部
Contact Address
Type Address(Japanese) Address(English)
Office 京都市左京区吉田本町36-1 36-1 Yoshida-honmachi, Sakyo-ku, Kyoto
Phone
Type Number
Office 075-753-5312
E-mail Address
E-mail address
hashimoto @ i.kyoto-u.ac.jp
Academic Organizations You are Affiliated to in Japan
Organization name(Japanese) Organization name(English)
電子情報通信学会 IEICE
情報処理学会 IPSJ
Academic Organizations Overaseas You are Affiliated to
Organization name Country
IEEE USA
ACM USA
Academic Degree
Field(Japanese) Field(English) University(Japanese) University(English) Method
博士(情報学) Ph.D. in Informatics 京都大学 Kyoto University
修士(工学) Master degree in Engineering 京都大学 Kyoto Unviersity
Academic Resume (Graduate Schools)
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(Japanese) Major(English) Completion Status
京都大学 Kyoto University 大学院工学研究科修士課程電子通信工学専攻 Graduate School of Engineering 修了
京都大学 Kyoto Univesity 大学院情報学研究科博士後期課程通信情報システム専攻 Graduate School of Informatics Department of Communications and Computer Engineering 修了
Academic Resume (Undergraduate School/Majors)
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(s)(Japanese) Major(s)(English) Completion Status
京都大学 Kyoto University 工学部電子工学科 School of Engineering 卒業
Work Experience
Period Organization(Japanese) Organization(English) Job title(Japanese) Job title(English)
2021/04/01- 京都大学 Kyoto Unviersity 教授 Professor
2016/04/01-2021/03/31 大阪大学 Osaka University 教授 Professor
2004/04/01-2016/03/31 大阪大学 Osaka University 助教授/准教授 Associate Professor
2001/04/01-2004/03/31 京都大学 Kyoto University 助手 Research Associate
Personal Website(s) (URL(s))
URL
https://sites.google.com/view/masanorihashimoto/
https://vlsi.cce.i.kyoto-u.ac.jp/
researchmap URL
https://researchmap.jp/masanorihashimoto
Published Papers
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
Ryo Shirai, Yuichi Itoh, Masanori Hashimoto Ryo Shirai, Yuichi Itoh, Masanori Hashimoto Ryo Shirai, Yuichi Itoh, Masanori Hashimoto Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers IEEE Access, 9, 26616-26632 IEEE Access, 9, 26616-26632 IEEE Access, 9, 26616-26632 2021/02 Refereed Research paper(scientific journal) Disclose to all
Proceedings of Asia, South Pacific, Design Automation Conference (ASP-DAC Proceedings of Asia, South Pacific, Design Automation Conference (ASP-DAC Proceedings of Asia, South Pacific, Design Automation Conference (ASP-DAC Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto 2021/01 Refereed English Research paper(international conference proceedings) Disclose to all
Ryutaro DOI, Xu BAI, Toshitsugu SAKAMOTO, Masanori HASHIMOTO Ryutaro DOI, Xu BAI, Toshitsugu SAKAMOTO, Masanori HASHIMOTO Ryutaro DOI, Xu BAI, Toshitsugu SAKAMOTO, Masanori HASHIMOTO A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E103.A, 12, 1447-1455 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E103.A, 12, 1447-1455 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E103.A, 12, 1447-1455 2020/12/01 Refereed Research paper(scientific journal) Disclose to all
T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H, Tanaka, M. Hashimoto T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H, Tanaka, M. Hashimoto T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H, Tanaka, M. Hashimoto Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles IEEE Nuclear and Space Radiation Effects Conference (NSREC) IEEE Nuclear and Space Radiation Effects Conference (NSREC) IEEE Nuclear and Space Radiation Effects Conference (NSREC) 2020/12 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Chen, Masanori Hashimoto Jun Chen, Masanori Hashimoto Jun Chen, Masanori Hashimoto A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges IEEE Transactions on Components, Packaging and Manufacturing Technology, 10, 11, 1769-1781 IEEE Transactions on Components, Packaging and Manufacturing Technology, 10, 11, 1769-1781 IEEE Transactions on Components, Packaging and Manufacturing Technology, 10, 11, 1769-1781 2020/11 Refereed Research paper(scientific journal) Disclose to all
H. Itsuji, T. Uezono, T. Toba, K. Ito, M. Hashimoto H. Itsuji, T. Uezono, T. Toba, K. Ito, M. Hashimoto H. Itsuji, T. Uezono, T. Toba, K. Ito, M. Hashimoto Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing Proceedings of International Test Conference (ITC) Proceedings of International Test Conference (ITC) Proceedings of International Test Conference (ITC) 2020/11 Refereed English Research paper(international conference proceedings) Disclose to all
J. Chen, M. Hashimoto J. Chen, M. Hashimoto J. Chen, M. Hashimoto Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction Proceedings of International Test Conference (ITC) Proceedings of International Test Conference (ITC) Proceedings of International Test Conference (ITC) 2020/11 Refereed English Research paper(international conference proceedings) Disclose to all
K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2020/10 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Zhang, K. Ito, H, Itsuji,T. Uezono, T. Toba, M. Hashimoto Y. Zhang, K. Ito, H, Itsuji,T. Uezono, T. Toba, M. Hashimoto Y. Zhang, K. Ito, H, Itsuji,T. Uezono, T. Toba, M. Hashimoto Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2020/10 Refereed English Research paper(international conference proceedings) Disclose to all
A. Lopez, J. Yu, M. Hashimoto A. Lopez, J. Yu, M. Hashimoto A. Lopez, J. Yu, M. Hashimoto Low-Cost Reservoir Computing Using Cellular Automata and Random Forests Low-Cost Reservoir Computing Using Cellular Automata and Random Forests Low-Cost Reservoir Computing Using Cellular Automata and Random Forests Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2020/10 Refereed English Research paper(international conference proceedings) Disclose to all
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 10, 2572-2587 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 10, 2572-2587 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 10, 2572-2587 2020/10 Refereed English Research paper(scientific journal) Disclose to all
TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training Integration, 74, 19-31 Integration, 74, 19-31 Integration, 74, 19-31 2020/09 Refereed English Research paper(scientific journal) Disclose to all
R. Shimizu, R. Shirai, M. Hashimoto R. Shimizu, R. Shirai, M. Hashimoto R. Shimizu, R. Shirai, M. Hashimoto Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS) Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS) Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS) 2020/08 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Masuda, J, Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto Y. Masuda, J, Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto Y. Masuda, J, Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling International Workshop on Logic and Synthesis (IWLS) International Workshop on Logic and Synthesis (IWLS) International Workshop on Logic and Synthesis (IWLS) 2020/07 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Kato, Masanori Hashimoto, Hideya Matsuyama Takashi Kato, Masanori Hashimoto, Hideya Matsuyama Takashi Kato, Masanori Hashimoto, Hideya Matsuyama Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs IEEE Transactions on Nuclear Science, 67, 7, 1485-1493 IEEE Transactions on Nuclear Science, 67, 7, 1485-1493 IEEE Transactions on Nuclear Science, 67, 7, 1485-1493 2020/07 Refereed English Research paper(scientific journal) Disclose to all
Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs IEEE Transactions on Nuclear Science, 67, 7, 1566-1572 IEEE Transactions on Nuclear Science, 67, 7, 1566-1572 IEEE Transactions on Nuclear Science, 67, 7, 1566-1572 2020/07 Refereed English Research paper(scientific journal) Disclose to all
Takumi Mahara, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Takeshi Y. Saito, Megumi Niikura, Kazuhiko Ninomiya, Dai Tomono, Akira Sato Takumi Mahara, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Takeshi Y. Saito, Megumi Niikura, Kazuhiko Ninomiya, Dai Tomono, Akira Sato Takumi Mahara, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Takeshi Y. Saito, Megumi Niikura, Kazuhiko Ninomiya, Dai Tomono, Akira Sato Irradiation Test of 65-nm Bulk SRAMs With DC Muon Beam at RCNP-MuSIC Facility Irradiation Test of 65-nm Bulk SRAMs With DC Muon Beam at RCNP-MuSIC Facility Irradiation Test of 65-nm Bulk SRAMs With DC Muon Beam at RCNP-MuSIC Facility IEEE Transactions on Nuclear Science, 67, 7, 1555-1559 IEEE Transactions on Nuclear Science, 67, 7, 1555-1559 IEEE Transactions on Nuclear Science, 67, 7, 1555-1559 2020/07 Refereed English Research paper(scientific journal) Disclose to all
X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada 1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy 1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy 1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy Technical Digest of VLSI Symposium on Technology Technical Digest of VLSI Symposium on Technology Technical Digest of VLSI Symposium on Technology 2020/06 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, K. Ito, Y. Mitsuyama, M. Hashimoto W. Liao, K. Ito, Y. Mitsuyama, M. Hashimoto W. Liao, K. Ito, Y. Mitsuyama, M. Hashimoto Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs Proceedings of International Reliability Physics Symposium (IRPS) Proceedings of International Reliability Physics Symposium (IRPS) Proceedings of International Reliability Physics Symposium (IRPS) 2020/04 Refereed English Research paper(international conference proceedings) Disclose to all
S. Abe, T. Sato, J. Kuroda, S. Manabe, Y, Watanabe,W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake S. Abe, T. Sato, J. Kuroda, S. Manabe, Y, Watanabe,W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake S. Abe, T. Sato, J. Kuroda, S. Manabe, Y, Watanabe,W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets Proceedings of International Symposium on Reliability Physics (IRPS) Proceedings of International Symposium on Reliability Physics (IRPS) Proceedings of International Symposium on Reliability Physics (IRPS) 2020/04 Refereed English Research paper(international conference proceedings) Disclose to all
Ryo Shirai, Masanori Hashimoto Ryo Shirai, Masanori Hashimoto Ryo Shirai, Masanori Hashimoto DC Magnetic Field Based 3D Localization With Single Anchor Coil DC Magnetic Field Based 3D Localization With Single Anchor Coil DC Magnetic Field Based 3D Localization With Single Anchor Coil IEEE Sensors Journal, 20, 7, 3902-3913 IEEE Sensors Journal, 20, 7, 3902-3913 IEEE Sensors Journal, 20, 7, 3902-3913 2020/04/01 Refereed English Research paper(scientific journal) Disclose to all
K. Onishi, J. Yu, M. Hashimoto K. Onishi, J. Yu, M. Hashimoto Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS) Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2020/03 Refereed English Research paper(international conference proceedings) Disclose to all
R. Doi, X. Bai, T. Sakamoto, M. Hashimoto R. Doi, X. Bai, T. Sakamoto, M. Hashimoto Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA Proceedings of Design, Automation and Test in Europe Conference (DATE) Proceedings of Design, Automation and Test in Europe Conference (DATE) 2020/03 Refereed English Research paper(international conference proceedings) Disclose to all
H. Awano, M. Hashimoto H. Awano, M. Hashimoto BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA Proceedings of Design, Automation and Test in Europe Conference (DATE) Proceedings of Design, Automation and Test in Europe Conference (DATE) 2020/03 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, X. Bai, N. Banno, M. Tada, T, Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T, Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi M. Hashimoto, X. Bai, N. Banno, M. Tada, T, Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T, Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Technical Digest of International Solid-State Circuits Conference (ISSCC) Technical Digest of International Solid-State Circuits Conference (ISSCC) 2020/02 Refereed English Research paper(international conference proceedings) Disclose to all
Junya Kuroda, Yasuhiro Miyake, Seiya Manabe, Yukinobu Watanabe, Kojiro Ito, Wang Liao, Masanori Hashimoto, Shin-ichiro Abe, Masahide Harada, Kenichi Oikawa Junya Kuroda, Yasuhiro Miyake, Seiya Manabe, Yukinobu Watanabe, Kojiro Ito, Wang Liao, Masanori Hashimoto, Shin-ichiro Abe, Masahide Harada, Kenichi Oikawa Junya Kuroda, Yasuhiro Miyake, Seiya Manabe, Yukinobu Watanabe, Kojiro Ito, Wang Liao, Masanori Hashimoto, Shin-ichiro Abe, Masahide Harada, Kenichi Oikawa Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF IEEE Transactions on Nuclear Science, 67, 7, 1599-1605 IEEE Transactions on Nuclear Science, 67, 7, 1599-1605 IEEE Transactions on Nuclear Science, 67, 7, 1599-1605 2020 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto, W. Liao M. Hashimoto, W. Liao Soft Error and Its Countermeasures in Terrestrial Environment Soft Error and Its Countermeasures in Terrestrial Environment Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) 2020/01 Refereed English Research paper(international conference proceedings) Disclose to all
Z. Yan, Y. Shi, W. Liao, M. Hashimoto, X. Zhou, C. Zhuo Z. Yan, Y. Shi, W. Liao, M. Hashimoto, X. Zhou, C. Zhuo When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) 2020/01 Refereed English Research paper(international conference proceedings) Disclose to all
S. Fukui, J. Yu, M. Hashimoto S. Fukui, J. Yu, M. Hashimoto Distilling Knowledge for Non-Neural Networks Distilling Knowledge for Non-Neural Networks Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC) Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC) 2019/11 Refereed English Research paper(international conference proceedings) Disclose to all
T. Tanio, J. Yu, M. Hashimoto T. Tanio, J. Yu, M. Hashimoto Training Data Reduction Using Support Vectors for Neural Networks Training Data Reduction Using Support Vectors for Neural Networks Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC) Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC) 2019/11 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, Y. Watanabe M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, Y. Watanabe Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation Integration, the VLSI Journal Integration, the VLSI Journal 2019/11 Refereed English Research paper(scientific journal) Disclose to all
S. Sombatsiri, J. Yu, M. Hashimoto, Y. Takeuchi S. Sombatsiri, J. Yu, M. Hashimoto, Y. Takeuchi A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) 2019/10 Refereed English Research paper(international conference proceedings) Disclose to all
J. Kuroda, S. Manabe, Y, Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, Y. Miyake J. Kuroda, S. Manabe, Y, Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, Y. Miyake Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2019/09 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, Y, Watanabe, S. Abe, M. Tampo, S. Takeshita, Y. Miyake W. Liao, M. Hashimoto, S. Manabe, Y, Watanabe, S. Abe, M. Tampo, S. Takeshita, Y. Miyake Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2019/09 Refereed English Research paper(international conference proceedings) Disclose to all
K. Ito, W. Liao, M, Hashimoto, J. Kuroda, S. Manabe, Y, Watanabe, S. Abe, M. Harada, K. Oikawa, Y. Miyake K. Ito, W. Liao, M, Hashimoto, J. Kuroda, S. Manabe, Y, Watanabe, S. Abe, M. Harada, K. Oikawa, Y. Miyake Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2019/09 Refereed English Research paper(international conference proceedings) Disclose to all
T. Mahara, S. Manabe, Y, Watanabe, W. Liao, M, Hashimoto,T, Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, A. Sato T. Mahara, S. Manabe, Y, Watanabe, W. Liao, M, Hashimoto,T, Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, A. Sato Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2019/09 Refereed English Research paper(international conference proceedings) Disclose to all
J. Chen, H. Kando, T, Kanamoto,C. Zhuo, M. Hashimoto J. Chen, H. Kando, T, Kanamoto,C. Zhuo, M. Hashimoto A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions IEEE Transactions on Components, Packaging and Manufacturing Technology IEEE Transactions on Components, Packaging and Manufacturing Technology 2019/09 Refereed English Research paper(scientific journal) Disclose to all
N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices 2019/08 Refereed English Research paper(scientific journal) Disclose to all
T.-Y. Cheng, J. Yu, M. Hashimoto T.-Y. Cheng, J. Yu, M. Hashimoto Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2019/07 Refereed English Research paper(international conference proceedings) Disclose to all
S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2019/07 Refereed English Research paper(scientific journal) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2019/07 Refereed English Research paper(scientific journal) Disclose to all
Y. Masuda, M. Hashimoto Y. Masuda, M. Hashimoto MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences 2019/07 Refereed English Research paper(scientific journal) Disclose to all
S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2019/07 Refereed English Research paper(scientific journal) Disclose to all
T. Nakayama, M. Hashimoto T. Nakayama, M. Hashimoto Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences 2019/07 Refereed English Research paper(scientific journal) Disclose to all
H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M, Hashimoto,T, Sugibayashi, T. Sakamoto, M. Tada Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA Proceedings of Silicon Nanoelectronics Workshop Proceedings of Silicon Nanoelectronics Workshop 2019/06 Refereed English Research paper(international conference proceedings) Disclose to all
J. Chen, M. Hashimoto J. Chen, M. Hashimoto A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) 2019/06 Refereed English Research paper(international conference proceedings) Disclose to all
J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, Y. Momiyama J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, Y. Momiyama Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP 2019/06 Refereed English Disclose to all
W. Liao, M. Hashimoto, S. Manabe, Y, Watanabe, S. Abe, M. Tampo, S. Takeshita, Y. Miyake W. Liao, M. Hashimoto, S. Manabe, Y, Watanabe, S. Abe, M. Tampo, S. Takeshita, Y. Miyake Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs Proceedings of International Reliability Physics Symposium (IRPS) Proceedings of International Reliability Physics Symposium (IRPS) 2019/04 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto W. Liao, M. Hashimoto Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate IEICE Trans. on Electronics IEICE Trans. on Electronics 2019/04 Refereed English Research paper(scientific journal) Disclose to all
西孝将, 増田豊, 橋本昌宜 西孝将, 増田豊, 橋本昌宜 FPGA を用いた動的電源ノイズ下でのエラー予告FF の動作検証 FPGA を用いた動的電源ノイズ下でのエラー予告FF の動作検証 電子情報通信学会総合大会, 60-60 電子情報通信学会総合大会, 60-60 , 60-60 2019/03 Japanese Research paper(research society, symposium, etc.) Disclose to all
P. Chen, R. Shirai, M. Hashimoto P. Chen, R. Shirai, M. Hashimoto Coverage-Scalable Instant Tabletop Positioning System with Self-Localizable Anchor Nodes Coverage-Scalable Instant Tabletop Positioning System with Self-Localizable Anchor Nodes Proceedings of International Conference on Intelligent User Interfaces (IUI) Proceedings of International Conference on Intelligent User Interfaces (IUI) 2019/03 Refereed English Research paper(international conference proceedings) Disclose to all
H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T, Kishimoto,T, Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T, Kishimoto,T, Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars IEEE Transactions on VLSI Systems IEEE Transactions on VLSI Systems 2018/12 Refereed English Research paper(scientific journal) Disclose to all
H. Hihara, A. Iwasaki, M, Hashimoto,H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto H. Hihara, A. Iwasaki, M, Hashimoto,H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture IEEE Embedded Systems Letters IEEE Embedded Systems Letters 2018/12 Refereed English Research paper(scientific journal) Disclose to all
Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, M. Hashimoto Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, M. Hashimoto Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
R. Doi, J. Yu, M. Hashimoto R. Doi, J. Yu, M. Hashimoto Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, M. Hashimoto Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, M. Hashimoto Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
R. Doi, J. Yu, M. Hashimoto R. Doi, J. Yu, M. Hashimoto Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Masuda, T. Onoye, M. Hashimoto Y. Masuda, T. Onoye, M. Hashimoto Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving IEEE Transactions on VLSI Systems IEEE Transactions on VLSI Systems 2018/11 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto, W. Liao, S. Manabe, Y. Watanabe M. Hashimoto, W. Liao, S. Manabe, Y. Watanabe Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2018/10 English Research paper(international conference proceedings) Disclose to all
S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk SRAMs Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2018/09 Refereed English Research paper(scientific journal) Disclose to all
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2018/09 Refereed English Research paper(scientific journal) Disclose to all
S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe S. Abe, W. Liao, S. Manabe, T. Sato, M, Hashimoto,Y. Watanabe Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, S. Abe Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk SRAMs Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2018/09 Refereed English Research paper(scientific journal) Disclose to all
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs IEEE Transactions on Nuclear Science IEEE Transactions on Nuclear Science 2018/09 Refereed English Research paper(scientific journal) Disclose to all
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化 FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
増田豊, 長山準, 武野紘宜, 小川芳正, 籾山陽一, 橋本昌宜 増田豊, 長山準, 武野紘宜, 小川芳正, 籾山陽一, 橋本昌宜 エラー予告FFとレプリカの電圧マージン制御性能の定量的比較 エラー予告FFとレプリカの電圧マージン制御性能の定量的比較 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
土井龍太郎, 劉載勲, 橋本昌宜 土井龍太郎, 劉載勲, 橋本昌宜 ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法 ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
K. Itoh, J. Yu, M. Hashimoto K. Itoh, J. Yu, M. Hashimoto Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2018/08 Refereed English Research paper(international conference proceedings) Disclose to all
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化 FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
増田豊, 長山準, 武野紘宜, 小川芳正, 籾山陽一, 橋本昌宜 増田豊, 長山準, 武野紘宜, 小川芳正, 籾山陽一, 橋本昌宜 エラー予告FFとレプリカの電圧マージン制御性能の定量的比較 エラー予告FFとレプリカの電圧マージン制御性能の定量的比較 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
土井龍太郎, 劉載勲, 橋本昌宜 土井龍太郎, 劉載勲, 橋本昌宜 ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法 ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2018/08 Japanese Research paper(other academic) Disclose to all
K. Itoh, J. Yu, M. Hashimoto K. Itoh, J. Yu, M. Hashimoto Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2018/08 Refereed English Research paper(international conference proceedings) Disclose to all
Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Keita Nakano, Hikaru Sato, Tadahiro Kin, Shin Ichiro Abe, Koji Hamada, Motonobu Tampo, Yasuhiro Miyake Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Keita Nakano, Hikaru Sato, Tadahiro Kin, Shin Ichiro Abe, Koji Hamada, Motonobu Tampo, Yasuhiro Miyake Seiya Manabe, Yukinobu Watanabe, Wang Liao, Masanori Hashimoto, Keita Nakano, Hikaru Sato, Tadahiro Kin, Shin Ichiro Abe, Koji Hamada, Motonobu Tampo, Yasuhiro Miyake Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs IEEE Transactions on Nuclear Science, 65, 8, 1742-1749 IEEE Transactions on Nuclear Science, 65, 8, 1742-1749 IEEE Transactions on Nuclear Science, 65, 8, 1742-1749 2018/08 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu Interconnect Delay Analysis for RRAM Crossbar Based FPGA Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
R. Doi, M. Hashimoto R. Doi, M. Hashimoto SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu Interconnect Delay Analysis for RRAM Crossbar Based FPGA Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
R. Doi, M. Hashimoto R. Doi, M. Hashimoto SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
R. Shirai, T. Hirose, M. Hashimoto R. Shirai, T. Hirose, M. Hashimoto A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes Proceedings of International NEWCAS Conference Proceedings of International NEWCAS Conference 2018/06 Refereed English Research paper(international conference proceedings) Disclose to all
L. Zhang, B. Li, M. Hashimoto, U. Schlichtmann L. Zhang, B. Li, M. Hashimoto, U. Schlichtmann VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units Proceedings of Design Automation Conference (DAC) Proceedings of Design Automation Conference (DAC) 2018/06 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto, Yutaka Masuda Masanori Hashimoto, Yutaka Masuda Masanori Hashimoto, Yutaka Masuda MTTF-aware design methodology for adaptive voltage scaling MTTF-aware design methodology for adaptive voltage scaling MTTF-aware design methodology for adaptive voltage scaling China Semiconductor Technology International Conference 2018, CSTIC 2018, 1-4 China Semiconductor Technology International Conference 2018, CSTIC 2018, 1-4 China Semiconductor Technology International Conference 2018, CSTIC 2018, 1-4 2018/05/29 Refereed English Research paper(international conference proceedings) Disclose to all
Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties Proceedings - International Symposium on Quality Electronic Design, ISQED, 2018-, 425-431 Proceedings - International Symposium on Quality Electronic Design, ISQED, 2018-, 425-431 Proceedings - International Symposium on Quality Electronic Design, ISQED, 2018-, 425-431 2018/05/09 Refereed English Research paper(international conference proceedings) Disclose to all
J. Chen, T, Kanamoto, H. Kando, M. Hashimoto J. Chen, T, Kanamoto, H. Kando, M. Hashimoto An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) 2018/05 Refereed English Research paper(international conference proceedings) Disclose to all
J. Chen, T, Kanamoto, H. Kando, M. Hashimoto J. Chen, T, Kanamoto, H. Kando, M. Hashimoto An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) 2018/05 Refereed English Research paper(international conference proceedings) Disclose to all
T. Nakayama, M. Hashimoto T. Nakayama, M. Hashimoto Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2018/04 Refereed English Research paper(international conference proceedings) Disclose to all
佐藤雅紘, 増田豊, 橋本昌宜 佐藤雅紘, 増田豊, 橋本昌宜 過電圧スケーリングを用いた不正確計算による消費電力削減の検討 過電圧スケーリングを用いた不正確計算による消費電力削減の検討 電子情報通信学会VLSI設計技術研究会 電子情報通信学会VLSI設計技術研究会 2018/03 Japanese Research paper(other academic) Disclose to all
中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜 中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜 ビアスイッチFPGA向け配線遅延解析手法の検討 ビアスイッチFPGA向け配線遅延解析手法の検討 電子情報通信学会 VLSI設計技術研究会 電子情報通信学会 VLSI設計技術研究会 2018/03 Japanese Research paper(other academic) Disclose to all
Yutaka Masuda, Masanori Hashimoto Yutaka Masuda, Masanori Hashimoto Yutaka Masuda, Masanori Hashimoto MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2018-, 159-165 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2018-, 159-165 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2018-, 159-165 2018/02/20 Refereed English Research paper(international conference proceedings) Disclose to all
葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾 葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築 情報処理学会 東北支部研究会, 2017-6, B1-1, 111-114 情報処理学会 東北支部研究会, 2017-6, B1-1, 111-114 , 2017-6, B1-1, 111-114 2018/02 Japanese Disclose to all
Bing Li, Masanori Hashimoto, Ulf Schlichtmann Bing Li, Masanori Hashimoto, Ulf Schlichtmann Bing Li, Masanori Hashimoto, Ulf Schlichtmann From process variations to reliability: A survey of timing of digital circuits in the nanometer era From process variations to reliability: A survey of timing of digital circuits in the nanometer era From process variations to reliability: A survey of timing of digital circuits in the nanometer era IPSJ Transactions on System LSI Design Methodology, 11, 2-15 IPSJ Transactions on System LSI Design Methodology, 11, 2-15 IPSJ Transactions on System LSI Design Methodology, 11, 2-15 2018/02/01 Refereed English Research paper(scientific journal) Disclose to all
Ryutaro Doi, Masanori Hashimoto, Takao Onoye Ryutaro Doi, Masanori Hashimoto, Takao Onoye Ryutaro Doi, Masanori Hashimoto, Takao Onoye An analytic evaluation on soft error immunity enhancement due to temporal triplication An analytic evaluation on soft error immunity enhancement due to temporal triplication An analytic evaluation on soft error immunity enhancement due to temporal triplication International Journal of Embedded Systems, 10, 1, 22-31 International Journal of Embedded Systems, 10, 1, 22-31 International Journal of Embedded Systems, 10, 1, 22-31 2018 Refereed English Research paper(scientific journal) Disclose to all
Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes 2018 16TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 152-156 2018 16TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 152-156 2018 16TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 152-156 2018 Refereed English Research paper(international conference proceedings) Disclose to all
Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto Dedicated antenna less power efficient OOK transmitter for mm-cubic IoT nodes Dedicated antenna less power efficient OOK transmitter for mm-cubic IoT nodes Dedicated antenna less power efficient OOK transmitter for mm-cubic IoT nodes European Microwave Week 2017: "A Prime Year for a Prime Event", EuMW 2017 - Conference Proceedings; 47th European Microwave Conference, EuMC 2017, 2017-January, 101-104 European Microwave Week 2017: "A Prime Year for a Prime Event", EuMW 2017 - Conference Proceedings; 47th European Microwave Conference, EuMC 2017, 2017-January, 101-104 European Microwave Week 2017: "A Prime Year for a Prime Event", EuMW 2017 - Conference Proceedings; 47th European Microwave Conference, EuMC 2017, 2017-January, 101-104 2017/12/19 Refereed English Research paper(international conference proceedings) Disclose to all
白井僚, 廣瀬哲也, 橋本昌宜 白井僚, 廣瀬哲也, 橋本昌宜 IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発 IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発 電子情報通信学会 集積回路研究会 電子情報通信学会 集積回路研究会 2017/12 Refereed Japanese Research paper(other academic) Disclose to all
白井僚, 河野仁, 廣瀬哲也, 橋本昌宜 白井僚, 河野仁, 廣瀬哲也, 橋本昌宜 近傍界磁界通信・電界測距共用mm3級アンテナの実装と評価 近傍界磁界通信・電界測距共用mm3級アンテナの実装と評価 電子情報通信学会 回路とシステム研究会 電子情報通信学会 回路とシステム研究会 2017/12 Japanese Research paper(other academic) Disclose to all
橋本昌宜 橋本昌宜 高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発 高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発 電気関連学会関西連合大会 電気関連学会関西連合大会 2017/11 Japanese Research paper(other academic) Disclose to all
Soichi Hirokawa, Ryo Harada, Kenshiro Sakuta, Yukinobu Watanabe, Masanori Hashimoto Soichi Hirokawa, Ryo Harada, Kenshiro Sakuta, Yukinobu Watanabe, Masanori Hashimoto Soichi Hirokawa, Ryo Harada, Kenshiro Sakuta, Yukinobu Watanabe, Masanori Hashimoto Multiple sensitive volume based soft error rate estimation with machine learning Multiple sensitive volume based soft error rate estimation with machine learning Multiple sensitive volume based soft error rate estimation with machine learning Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 2016-, 1-4 Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 2016-, 1-4 Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 2016-, 1-4 2017/10/31 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto, Wang Liao, Soichi Hirokawa Masanori Hashimoto, Wang Liao, Soichi Hirokawa Masanori Hashimoto, Wang Liao, Soichi Hirokawa Soft error rate estimation with TCAD and machine learning Soft error rate estimation with TCAD and machine learning Soft error rate estimation with TCAD and machine learning International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2017-, 129-132 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2017-, 129-132 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2017-, 129-132 2017/10/25 English Research paper(international conference proceedings) Disclose to all
S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake S. Manabe, Y, Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake Momentum and Supply Voltage Dependencies of SEUs Induced by Low-energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs Momentum and Supply Voltage Dependencies of SEUs Induced by Low-energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2017/10 Refereed English Research paper(international conference proceedings) Disclose to all
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K, Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K, Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2017/10 Refereed English Research paper(international conference proceedings) Disclose to all
Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node Proceedings - IEEE International Symposium on Circuits and Systems Proceedings - IEEE International Symposium on Circuits and Systems Proceedings - IEEE International Symposium on Circuits and Systems 2017/09/25 Refereed English Research paper(international conference proceedings) Disclose to all
Liao Wang, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto Liao Wang, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto Liao Wang, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V - Bulk v Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V - Bulk v Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V - Bulk v Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, 33-36 Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, 33-36 Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, 33-36 2017/08/11 Refereed English Research paper(international conference proceedings) Disclose to all
中山貴博, 橋本昌宜 中山貴博, 橋本昌宜 常温で論理テスト可能な超低温動作VLSIのタイミング設計法の検討 常温で論理テスト可能な超低温動作VLSIのタイミング設計法の検討 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2017/08 Japanese Research paper(other academic) Disclose to all
増田豊, 橋本昌宜 増田豊, 橋本昌宜 エラー予告ベース適応的電圧制御のMTTF考慮設計手法 エラー予告ベース適応的電圧制御のMTTF考慮設計手法 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2017/08 Japanese Research paper(other academic) Disclose to all
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始 容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築 容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2017/08 Japanese Research paper(other academic) Disclose to all
土井龍太郎, 橋本 昌宜 土井龍太郎, 橋本 昌宜 ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証 ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証 情報処理学会DAシンポジウム 情報処理学会DAシンポジウム 2017/08 Japanese Research paper(other academic) Disclose to all
Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto Near-future traffic evaluation based navigation for automated driving vehicles Near-future traffic evaluation based navigation for automated driving vehicles Near-future traffic evaluation based navigation for automated driving vehicles IEEE Intelligent Vehicles Symposium, Proceedings, 1465-1470 IEEE Intelligent Vehicles Symposium, Proceedings, 1465-1470 IEEE Intelligent Vehicles Symposium, Proceedings, 1465-1470 2017/07/28 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes Proceedings of International Conference on ASIC, 2017-October, 1065-1068 Proceedings of International Conference on ASIC, 2017-October, 1065-1068 Proceedings of International Conference on ASIC, 2017-October, 1065-1068 2017/07/01 Refereed English Research paper(international conference proceedings) Disclose to all
Yutaka Masuda, Takao Onoye, Masanori Hashimoto Yutaka Masuda, Takao Onoye, Masanori Hashimoto Yutaka Masuda, Takao Onoye, Masanori Hashimoto Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E100A, 7, 1452-1463 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E100A, 7, 1452-1463 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E100A, 7, 1452-1463 2017/07 Refereed English Research paper(scientific journal) Disclose to all
Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin Minimizing detection-to-boosting latency toward low-power error-resilient circuits Minimizing detection-to-boosting latency toward low-power error-resilient circuits Minimizing detection-to-boosting latency toward low-power error-resilient circuits INTEGRATION-THE VLSI JOURNAL, 58, 236-244 INTEGRATION-THE VLSI JOURNAL, 58, 236-244 INTEGRATION-THE VLSI JOURNAL, 58, 236-244 2017/06 Refereed English Research paper(scientific journal) Disclose to all
K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, M. Hashimoto K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, M. Hashimoto GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction Proceedings of International Conference on Intelligent User Interfaces (IUI) Proceedings of International Conference on Intelligent User Interfaces (IUI) 2017/03 Refereed English Research paper(international conference proceedings) Disclose to all
伴野直樹, 多田宗弘, 岡本浩一郎, 井口憲幸, 阪本利司, 波田博光, 越智裕之, 小野寺秀俊, 橋本昌宜, 杉林直彦 伴野直樹, 多田宗弘, 岡本浩一郎, 井口憲幸, 阪本利司, 波田博光, 越智裕之, 小野寺秀俊, 橋本昌宜, 杉林直彦 低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 電子情報通信学会シリコン材料・デバイス研究会 電子情報通信学会シリコン材料・デバイス研究会 2017/02 Japanese Research paper(other academic) Disclose to all
N. Banno, M. Tilda, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tilda, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tilda, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi 50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic 50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic 50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic Technical Digest - International Electron Devices Meeting, IEDM, 16.4.1-16.4.4 Technical Digest - International Electron Devices Meeting, IEDM, 16.4.1-16.4.4 Technical Digest - International Electron Devices Meeting, IEDM, 16.4.1-16.4.4 2017/01/31 Refereed English Research paper(international conference proceedings) Disclose to all
葛西 孝己, 今井 雅, 黒川 敦, 金本 俊幾, 陳 俊, 橋本 昌宜, 神藤 始 葛西 孝己, 今井 雅, 黒川 敦, 金本 俊幾, 陳 俊, 橋本 昌宜, 神藤 始 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築 電気関係学会東北支部連合大会講演論文集, 2017, 201-201 電気関係学会東北支部連合大会講演論文集, 2017, 201-201 , 2017, 201-201 2017 Japanese Disclose to all
Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto Near-Field Dual-Use Antenna for Magnetic-Field based Communication and Electrical-Field based Distance Sensing in mm(3)-Class Sensor Node Near-Field Dual-Use Antenna for Magnetic-Field based Communication and Electrical-Field based Distance Sensing in mm(3)-Class Sensor Node Near-Field Dual-Use Antenna for Magnetic-Field based Communication and Electrical-Field based Distance Sensing in mm(3)-Class Sensor Node 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 124-127 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 124-127 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 124-127 2017 Refereed English Research paper(international conference proceedings) Disclose to all
Sota Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Sota Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Sota Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices 2017 IEEE WIRELESS POWER TRANSFER CONFERENCE (WPTC 2017) 2017 IEEE WIRELESS POWER TRANSFER CONFERENCE (WPTC 2017) 2017 IEEE WIRELESS POWER TRANSFER CONFERENCE (WPTC 2017) 2017 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Masuda, M. Hashimoto, T. Onoye Y. Masuda, M. Hashimoto, T. Onoye Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation Proceedings of International Conference on Computer-Aided Design (ICCAD) Proceedings of International Conference on Computer-Aided Design (ICCAD) 2016/11 Refereed English Research paper(international conference proceedings) Disclose to all
Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 84-89 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 84-89 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 84-89 2016/10/20 Refereed English Research paper(international conference proceedings) Disclose to all
佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜 佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜 確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察 確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察 2016/09 Japanese Research paper(other academic) Disclose to all
増田豊, 尾上孝雄, 橋本昌宜 増田豊, 尾上孝雄, 橋本昌宜 低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法 低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法 2016/09 Japanese Research paper(other academic) Disclose to all
J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch Proceedings of International Conference on Field Programmable Logic and Applications (FPL) Proceedings of International Conference on Field Programmable Logic and Applications (FPL) 2016/09 Refereed English Research paper(international conference proceedings) Disclose to all
佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜 佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜 確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察 確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察 2016/09 Japanese Research paper(other academic) Disclose to all
増田豊, 尾上孝雄, 橋本昌宜 増田豊, 尾上孝雄, 橋本昌宜 低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法 低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法 2016/09 Japanese Research paper(other academic) Disclose to all
S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, M. Hashimoto S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, M. Hashimoto Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) 2016/09 Refereed English Research paper(international conference proceedings) Disclose to all
橋本昌宜 橋本昌宜 超低電圧SRAMのソフトエラー耐性 超低電圧SRAMのソフトエラー耐性 2016/08 Japanese Research paper(other academic) Disclose to all
H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi Novel processor architecture for onboard infrared sensors Novel processor architecture for onboard infrared sensors Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV 2016/08 English Research paper(international conference proceedings) Disclose to all
橋本昌宜 橋本昌宜 超低電圧SRAMのソフトエラー耐性 超低電圧SRAMのソフトエラー耐性 2016/08 Japanese Research paper(other academic) Disclose to all
Chih-Cheng Hsu, Mark Po-Hung Lint, Masanori Hashimoto Chih-Cheng Hsu, Mark Po-Hung Lint, Masanori Hashimoto Chih-Cheng Hsu, Mark Po-Hung Lint, Masanori Hashimoto Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016 Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016 Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016 2016/06/04 Refereed English Research paper(international conference proceedings) Disclose to all
C.-C. Hsu, M, P.-H. Lin, M. Hashimoto C.-C. Hsu, M, P.-H. Lin, M. Hashimoto Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits Proceedings of System Level Interconnect Prediction (SLIP) Workshop Proceedings of System Level Interconnect Prediction (SLIP) Workshop 2016/06 Refereed English Research paper(international conference proceedings) Disclose to all
N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation 2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Hardware-Simulation Correlation of Timing Error Detection Performance of Software-based Error Detection Mechanisms Hardware-Simulation Correlation of Timing Error Detection Performance of Software-based Error Detection Mechanisms Hardware-Simulation Correlation of Timing Error Detection Performance of Software-based Error Detection Mechanisms 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 84-89 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 84-89 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 84-89 2016 Refereed English Research paper(international conference proceedings) Disclose to all
N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Souta Masuda, Tetsuya Hirose, Yuki Akihara, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512-513 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Yuki Akihara, Tetsuya Hirose, Sota Masuda, Nobutaka Kuroki, Masahiro Numa, Masanori Hashimoto Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338-339 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Hiroki Hihara, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Munehiro Tada Hiroki Hihara, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Munehiro Tada Hiroki Hihara, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Munehiro Tada Novel processor architecture for onboard infrared sensors Novel processor architecture for onboard infrared sensors Novel processor architecture for onboard infrared sensors INFRARED REMOTE SENSING AND INSTRUMENTATION XXIV, 9973 INFRARED REMOTE SENSING AND INSTRUMENTATION XXIV, 9973 INFRARED REMOTE SENSING AND INSTRUMENTATION XXIV, 9973 2016 English Research paper(international conference proceedings) Disclose to all
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2607-2613 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2607-2613 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2607-2613 2015/12 Refereed English Research paper(scientific journal) Disclose to all
Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Proximity distance estimation based on electric field communication between 1 mm(3) sensor nodes Proximity distance estimation based on electric field communication between 1 mm(3) sensor nodes Proximity distance estimation based on electric field communication between 1 mm(3) sensor nodes ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 85, 3, 425-432 ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 85, 3, 425-432 ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 85, 3, 425-432 2015/12 Refereed English Research paper(scientific journal) Disclose to all
N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs 2015 International Electron Devices Meeting, 2016-February, 2.5.1-2.5.4 2015 International Electron Devices Meeting, 2016-February, 2.5.1-2.5.4 2015 International Electron Devices Meeting, 2016-February, 2.5.1-2.5.4 2015/12 Refereed English Research paper(international conference proceedings) Disclose to all
AKIHARA Yuki, HIROSE Tetsuya, TANAKA Yuki, KUROKI Nobutaka, NUMA Masahiro, HASHIMOTO Masanori AKIHARA Yuki, HIROSE Tetsuya, TANAKA Yuki, KUROKI Nobutaka, NUMA Masahiro, HASHIMOTO Masanori AKIHARA Yuki, HIROSE Tetsuya, TANAKA Yuki, KUROKI Nobutaka, NUMA Masahiro, HASHIMOTO Masanori A wireless power transfer system for small-sized sensor applications A wireless power transfer system for small-sized sensor applications A wireless power transfer system for small-sized sensor applications Extended abstract of the 2015 international conference on solid state devices and materials, 154-155 Extended abstract of the 2015 international conference on solid state devices and materials, 154-155 Extended abstract of the 2015 international conference on solid state devices and materials, 154-155 2015/09 Refereed English Research paper(international conference proceedings) Disclose to all
増田豊, 橋本昌宜, 尾上孝雄 増田豊, 橋本昌宜, 尾上孝雄 電源ノイズ起因タイミング故障のデバッグにおけるC 言語ベース故障検出 手法の有効性評価 電源ノイズ起因タイミング故障のデバッグにおけるC 言語ベース故障検出 手法の有効性評価 情報処理学会DA シンポジウム2015論文集, 193-198 情報処理学会DA シンポジウム2015論文集, 193-198 , 193-198 2015/08 Japanese Research paper(research society, symposium, etc.) Disclose to all
AKIHARA Yuki, HIROSE Tetsuya, TANAKA Yuki, KUROKI Nobutaka, NUMA Masahiro, HASHIMOTO Masanori 秋原 優樹, 廣瀬 哲也, 田中 勇気, 黒木 修隆, 沼 昌宏, 橋本 昌宜 AKIHARA Yuki, HIROSE Tetsuya, TANAKA Yuki, KUROKI Nobutaka, NUMA Masahiro, HASHIMOTO Masanori 小型センサデバイスに向けた無線給電システムの設計 小型センサデバイスに向けた無線給電システムの設計 小型センサデバイスに向けた無線給電システムの設計 第28回 回路とシステムワークショップ, 258-263 第28回 回路とシステムワークショップ, 258-263 第28回 回路とシステムワークショップ, 258-263 2015/08 Refereed Japanese Research paper(research society, symposium, etc.) Disclose to all
Soichi Hirokawa, Ryo Harada, Masanori Hashimoto, Takao Onoye Soichi Hirokawa, Ryo Harada, Masanori Hashimoto, Takao Onoye Soichi Hirokawa, Ryo Harada, Masanori Hashimoto, Takao Onoye Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 62, 2, 420-427 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 62, 2, 420-427 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 62, 2, 420-427 2015/04 Refereed English Research paper(scientific journal) Disclose to all
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 731-736 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 731-736 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 731-736 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Miho Ueno, Masanori Hashimoto, Takao Onoye Miho Ueno, Masanori Hashimoto, Takao Onoye Miho Ueno, Masanori Hashimoto, Takao Onoye Real-time On-chip Supply Voltage Sensor and Its Application to Trace-based Timing Error Localization Real-time On-chip Supply Voltage Sensor and Its Application to Trace-based Timing Error Localization Real-time On-chip Supply Voltage Sensor and Its Application to Trace-based Timing Error Localization 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 188-193 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 188-193 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 188-193 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye Stochastic Timing Error Rate Estimation under Process and Temporal Variations Stochastic Timing Error Rate Estimation under Process and Temporal Variations Stochastic Timing Error Rate Estimation under Process and Temporal Variations 2015 IEEE INTERNATIONAL TEST CONFERENCE (ITC) 2015 IEEE INTERNATIONAL TEST CONFERENCE (ITC) 2015 IEEE INTERNATIONAL TEST CONFERENCE (ITC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Yutaka Masuda, Masanori Hashimoto, Takao Onoye Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 315-322 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 315-322 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 315-322 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis The 20th Asia South-Pacific Design Automation Conference, 14-15 The 20th Asia South-Pacific Design Automation Conference, 14-15 The 20th Asia South-Pacific Design Automation Conference, 14-15 2015/01 Refereed English Research paper(international conference proceedings) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye A Process and Temperature Tolerant Oscillator-Based True Random Number Generator A Process and Temperature Tolerant Oscillator-Based True Random Number Generator A Process and Temperature Tolerant Oscillator-Based True Random Number Generator IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2393-2399 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2393-2399 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2393-2399 2014/12 Refereed English Research paper(scientific journal) Disclose to all
Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2518-2529 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2518-2529 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2518-2529 2014/12 Refereed English Research paper(scientific journal) Disclose to all
増田豊, 橋本昌宜, 尾上孝雄 増田豊, 橋本昌宜, 尾上孝雄 電源ノイズ起因電気的故障を対象としたソフトウェアベース高速エラー検 出手法の性能評価 電源ノイズ起因電気的故障を対象としたソフトウェアベース高速エラー検 出手法の性能評価 情報処理学会DA シンポジウム2014論文集, 203-208 情報処理学会DA シンポジウム2014論文集, 203-208 , 203-208 2014/08 Japanese Research paper(research society, symposium, etc.) Disclose to all
Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1483-1491 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1483-1491 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1483-1491 2014/07 Refereed English Research paper(scientific journal) Disclose to all
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1461-1467 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1461-1467 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1461-1467 2014/07 Refereed English Research paper(scientific journal) Disclose to all
Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1468-1482 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1468-1482 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 7, 1468-1482 2014/07 Refereed English Research paper(scientific journal) Disclose to all
佐藤高史, 橋本 昌宜 佐藤高史, 橋本 昌宜 経時劣化概説(招待) 経時劣化概説(招待) 日本信頼性学会誌, 35, 8, 457-458 日本信頼性学会誌, 35, 8, 457-458 , 35, 8, 457-458 2013/12 Refereed Japanese Disclose to all
D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 313-316 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 313-316 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 313-316 2013/11 Refereed English Research paper(international conference proceedings) Disclose to all
Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 8, 1624-1631 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 8, 1624-1631 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 8, 1624-1631 2013/08 Refereed English Research paper(scientific journal) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 8, 8, 1331-1342 IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 8, 8, 1331-1342 IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 8, 8, 1331-1342 2013/08 Refereed English Research paper(scientific journal) Disclose to all
郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄 郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄 郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄 動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討 動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討 動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討 電子情報通信学会技術研究報告, Vol.113, No.52, 113, 52, 41-46 電子情報通信学会技術研究報告, Vol.113, No.52, 113, 52, 41-46 電子情報通信学会技術研究報告, Vol.113, No.52, 113, 52, 41-46 2013/05/13 Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Supply Noise Suppression by Triple-Well Structure Supply Noise Suppression by Triple-Well Structure Supply Noise Suppression by Triple-Well Structure IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21, 4, 781-785 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21, 4, 781-785 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21, 4, 781-785 2013/04 Refereed English Research paper(scientific journal) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Jitter Amplifier for Oscillator-Based True Random Number Generator Jitter Amplifier for Oscillator-Based True Random Number Generator Jitter Amplifier for Oscillator-Based True Random Number Generator IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 3, 684-696 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 3, 684-696 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 3, 684-696 2013/03 Refereed English Research paper(scientific journal) Disclose to all
Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 2, 459-468 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 2, 459-468 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A, 2, 459-468 2013/02 Refereed English Research paper(scientific journal) Disclose to all
Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing 2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 107-114 2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 107-114 2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 107-114 2013 Refereed English Research paper(international conference proceedings) Disclose to all
Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Tatsuya Shinada, Masanori Hashimoto, Takao Onoye Proximity Distance Estimation based on Capacitive Coupling between 1mm(3) Sensor Nodes Proximity Distance Estimation based on Capacitive Coupling between 1mm(3) Sensor Nodes Proximity Distance Estimation based on Capacitive Coupling between 1mm(3) Sensor Nodes 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2013 Refereed English Research paper(international conference proceedings) Disclose to all
Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye HOMJAKOVS Igors, HIROSE Tetsuya, OSAKI Yuji, HASHIMOTO Masanori, ONOYE Takao Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation IEICE Electronics Express, 10, 4, 20130022, 1-6 IEICE Electronics Express, 10, 4, 20130022, 1-6 IEICE Electronics Express, 10, 4, 20130022, 1-6 2013 English Disclose to all
Yasumichi Takai, Masanori Hashimoto, Takao Onoye Yasumichi Takai, Masanori Hashimoto, Takao Onoye Yasumichi Takai, Masanori Hashimoto, Takao Onoye Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2220-2225 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2220-2225 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2220-2225 2012/12 Refereed English Research paper(scientific journal) Disclose to all
Shuta Kimura, Masanori Hashimoto, Takao Onoye Shuta Kimura, Masanori Hashimoto, Takao Onoye Shuta Kimura, Masanori Hashimoto, Takao Onoye A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2292-2300 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2292-2300 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A, 12, 2292-2300 2012/12 Refereed English Research paper(scientific journal) Disclose to all
T. Enami, T. Sato, M. Hashimoto T. Enami, T. Sato, M. Hashimoto T. Enami, T. Sato, M. Hashimoto Power Distribution Network Optimization for Timing Improvement With Statistical Noise Model and Timing Analysis Power Distribution Network Optimization for Timing Improvement With Statistical Noise Model and Timing Analysis Power Distribution Network Optimization for Timing Improvement With Statistical Noise Model and Timing Analysis IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95-A, 12, 2261-2271 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95-A, 12, 2261-2271 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95-A, 12, 2261-2271 2012/12 Refereed English Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. VLSI Syst., 20, 2, 333-343 IEEE Trans. VLSI Syst., 20, 2, 333-343 IEEE Trans. VLSI Syst., 20, 2, 333-343 2012/02 Refereed Disclose to all
Dawood Alnajjar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama Dawood Alnajjar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama Dawood Alnajjar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices 2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG) 2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG) 2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG) 2012 Refereed English Research paper(international conference proceedings) Disclose to all
Shuta Kimura, Masanori Hashimoto, Takao Onoye Shuta Kimura, Masanori Hashimoto, Takao Onoye Shuta Kimura, Masanori Hashimoto, Takao Onoye Body Bias Clustering for Low Test-Cost Post-Silicon Tuning Body Bias Clustering for Low Test-Cost Post-Silicon Tuning Body Bias Clustering for Low Test-Cost Post-Silicon Tuning 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 283-289 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 283-289 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 283-289 2012 Refereed English Research paper(international conference proceedings) Disclose to all
Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose Signal-dependent analog-to-digital converter based on MINIMAX sampling Signal-dependent analog-to-digital converter based on MINIMAX sampling Signal-dependent analog-to-digital converter based on MINIMAX sampling ISOCC 2012 - 2012 International SoC Design Conference, 120-123 ISOCC 2012 - 2012 International SoC Design Conference, 120-123 ISOCC 2012 - 2012 International SoC Design Conference, 120-123 2012 Refereed Research paper(international conference proceedings) Disclose to all
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Stress Probability Computation for Estimating NBTI-Induced Delay Degradation Stress Probability Computation for Estimating NBTI-Induced Delay Degradation Stress Probability Computation for Estimating NBTI-Induced Delay Degradation IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2545-2553 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2545-2553 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2545-2553 2011/12 Refereed English Research paper(scientific journal) Disclose to all
Ken-ichi Shinkai, Masanori Hashimoto, Takao Onoye Ken-ichi Shinkai, Masanori Hashimoto, Takao Onoye Ken-ichi Shinkai, Masanori Hashimoto, Takao Onoye Extracting Device-Parameter Variations with RO-Based Sensors Extracting Device-Parameter Variations with RO-Based Sensors Extracting Device-Parameter Variations with RO-Based Sensors IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2537-2544 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2537-2544 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A, 12, 2537-2544 2011/12 Refereed English Research paper(scientific journal) Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 58, 4, 2097-2102 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 58, 4, 2097-2102 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 58, 4, 2097-2102 2011/08 Refereed English Research paper(scientific journal) Disclose to all
Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 58, 5, 299-303 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 58, 5, 299-303 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 58, 5, 299-303 2011/05 Refereed English Research paper(scientific journal) Disclose to all
Yasumichi Takai, Masanori Hashimoto, Takao Onoye Yasumichi Takai, Masanori Hashimoto, Takao Onoye Yasumichi Takai, Masanori Hashimoto, Takao Onoye Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2011 Refereed English Research paper(international conference proceedings) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling INFORMATION SECURITY APPLICATIONS, 6513, 107-121 INFORMATION SECURITY APPLICATIONS, 6513, 107-121 INFORMATION SECURITY APPLICATIONS, 6513, 107-121 2011 Refereed English Research paper(international conference proceedings) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Jitter Amplifier for Oscillator-Based True Random Number Generator Jitter Amplifier for Oscillator-Based True Random Number Generator Jitter Amplifier for Oscillator-Based True Random Number Generator 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 2011 Refereed English Research paper(international conference proceedings) Disclose to all
Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye Takehiko Amaki, Masanori Hashimoto, Takao Onoye An Oscillator-Based True Random Number Generator with Jitter Amplifier An Oscillator-Based True Random Number Generator with Jitter Amplifier An Oscillator-Based True Random Number Generator with Jitter Amplifier 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 725-728 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 725-728 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 725-728 2011 Refereed English Research paper(international conference proceedings) Disclose to all
Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose HOMJAKOVS Igors, HASHIMOTO Masanori, HIROSE Tetsuya, ONOYE Takao Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose Signal-dependent analog-to-digital conversion based on MINIMAX sampling Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling Signal-dependent analog-to-digital conversion based on MINIMAX sampling Midwest Symposium on Circuits and Systems, E69-A, 2, 459-468 IEICE Transactions on Fundamentals of Electronics, Communications and Computer, E69-A, 2, 459-468 Midwest Symposium on Circuits and Systems, E69-A, 2, 459-468 2011 Refereed English Research paper(international conference proceedings) Disclose to all
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E93A, 12, 2417-2423 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E93A, 12, 2417-2423 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E93A, 12, 2417-2423 2010/12 Refereed English Research paper(scientific journal) Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 18, 7, 1118-1129 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 18, 7, 1118-1129 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 18, 7, 1118-1129 2010/07 Refereed English Research paper(scientific journal) Disclose to all
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto Impact of Self-heating in Wire Interconnection on Timing Impact of Self-heating in Wire Interconnection on Timing Impact of Self-heating in Wire Interconnection on Timing IEICE Transactions on Electronics, E93-C, 3, 388-392 IEICE Transactions on Electronics, E93-C, 3, 388-392 IEICE Transactions on Electronics, E93-C, 3, 388-392 2010/03 Refereed English Disclose to all
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue Modeling the Overshooting Effect for CMOS Inverter Delay Analysis Modeling the Overshooting Effect for CMOS Inverter Delay Analysis Modeling the Overshooting Effect for CMOS Inverter Delay Analysis IEEE Transactions on Computer-Aided Design, 29, 2, 250-260 IEEE Transactions on Computer-Aided Design, 29, 2, 250-260 IEEE Transactions on Computer-Aided Design, 29, 2, 250-260 2010/02 Refereed English Disclose to all
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 646-651 PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 646-651 PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 646-651 2010 Refereed English Research paper(international conference proceedings) Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. Asia South Pacific Design Automation Conference (ASP-DAC), 361-362 Asia South Pacific Design Automation Conference (ASP-DAC), 361-362 Asia South Pacific Design Automation Conference (ASP-DAC), 361-362 2010/01 Refereed Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Transactions, 92-A, 12, 3094-3102 IEICE Transactions, 92-A, 12, 3094-3102 IEICE Transactions, 92-A, 12, 3094-3102 2009/12 Refereed Disclose to all
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 12, 3016-3023 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 12, 3016-3023 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 12, 3016-3023 2009/12 Refereed English Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, 215-218 IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, 215-218 IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, 215-218 2009/09 Refereed Disclose to all
A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto Interconnect Modeling: A Physical Design Perspective (Invited) Interconnect Modeling: A Physical Design Perspective (Invited) Interconnect Modeling: A Physical Design Perspective (Invited) IEEE Transactions on Electron Devices, 56, 9, 1840-1851 IEEE Transactions on Electron Devices, 56, 9, 1840-1851 IEEE Transactions on Electron Devices, 56, 9, 1840-1851 2009/09 Refereed English Disclose to all
Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44, 6, 1745-1755 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44, 6, 1745-1755 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44, 6, 1745-1755 2009/06 Refereed Disclose to all
佐方剛, 黒川敦, 奥村隆昌, 中島英斉, 増田弘生, 佐藤高史, 橋本昌宜, 蜂屋孝太郎, 古川且洋, 田中正和, 高藤浩資, 金本俊幾 佐方剛, 黒川敦, 奥村隆昌, 中島英斉, 増田弘生, 佐藤高史, 橋本昌宜, 蜂屋孝太郎, 古川且洋, 田中正和, 高藤浩資, 金本俊幾 Reduction approach of leak current variation due to process variation 製造ばらつきに起因するリーク電流変動の低減アプローチ Reduction approach of leak current variation due to process variation IEICE (Karuizawa) Workshop on Circuits and Systems, 444-449 電子情報通信学会 回路とシステム(軽井沢)ワークショップ, 444-449 IEICE (Karuizawa) Workshop on Circuits and Systems, 444-449 2009/04 Refereed Japanese Research paper(research society, symposium, etc.) Disclose to all
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 4, 990-997 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 4, 990-997 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, 4, 990-997 2009/04 Refereed English Disclose to all
Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability IEICE TRANSACTIONS ON ELECTRONICS, E92C, 2, 281-285 IEICE TRANSACTIONS ON ELECTRONICS, E92C, 2, 281-285 IEICE TRANSACTIONS ON ELECTRONICS, E92C, 2, 281-285 2009/02 Refereed English Research paper(scientific journal) Disclose to all
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits ISLPED 09, 51-56 ISLPED 09, 51-56 ISLPED 09, 51-56 2009 Refereed English Research paper(international conference proceedings) Disclose to all
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 266-271 IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 266-271 IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 266-271 2009/01 Refereed Disclose to all
Shinya Abe, Masanori Hashimoto, Takao Onoye Shinya Abe, Masanori Hashimoto, Takao Onoye Shinya Abe, Masanori Hashimoto, Takao Onoye Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3481-3487 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3481-3487 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3481-3487 2008/12 Refereed English Research paper(scientific journal) Disclose to all
Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa Area-Efficient Reconfigurable Architecture for Media Processing Area-Efficient Reconfigurable Architecture for Media Processing Area-Efficient Reconfigurable Architecture for Media Processing IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3651-3662 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3651-3662 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3651-3662 2008/12 Refereed English Research paper(scientific journal) Disclose to all
Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI (GLSVLSI), 387-390 ACM Great Lakes Symposium on VLSI (GLSVLSI), 387-390 ACM Great Lakes Symposium on VLSI (GLSVLSI), 387-390 2008/05 Refereed Disclose to all
奥村隆昌, 黒川敦, 増田弘生, 金本俊幾, 佐藤高史, 橋本昌宜, 高藤浩資, 中島英斉, 小野信任 奥村隆昌, 黒川敦, 増田弘生, 金本俊幾, 佐藤高史, 橋本昌宜, 高藤浩資, 中島英斉, 小野信任 Analysis of output transition time variation due to Vth variations Vthばらつきに拠る出力遷移時間ばらつきの解析 Analysis of output transition time variation due to Vth variations IEICE (Workshop) on Circuits and Systems, 21, 299-304 電子情報通信学会 回路とシステム(軽井沢)ワークショップ, 21, 299-304 IEICE (Workshop) on Circuits and Systems, 21, 299-304 2008/04 Refereed Japanese Research paper(research society, symposium, etc.) Disclose to all
Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao Ogasahara Yasuhiro, Hashimoto Masanori, Onoye Takao Measurement and analysis of inductive coupling noise in 90 nm global interconnects Measurement and analysis of inductive coupling noise in 90 nm global interconnects Measurement and analysis of inductive coupling noise in 90 nm global interconnects IEEE JOURNAL OF SOLID-STATE CIRCUITS, 43, 3, 718-728 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 43, 3, 718-728 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 43, 3, 718-728 2008/03 Refereed Disclose to all
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera Timing Analysis Considering Temporal Supply Voltage Fluctuation Timing Analysis Considering Temporal Supply Voltage Fluctuation Timing Analysis Considering Temporal Supply Voltage Fluctuation IEICE Transactions on Information and Systems, E91-D, 3, 655-660 IEICE Transactions on Information and Systems, E91-D, 3, 655-660 IEICE Transactions on Information and Systems, E91-D, 3, 655-660 2008/03 Refereed English Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process 2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 393-396 2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 393-396 2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 393-396 2008 Refereed English Research paper(international conference proceedings) Disclose to all
Shinya Abe, Masanori Hashimoto, Takao Onoye Shinya Abe, Masanori Hashimoto, Takao Onoye Shinya Abe, Masanori Hashimoto, Takao Onoye Clock Skew evaluation considering manufacturing variability in mesh-style clock distribution Clock Skew evaluation considering manufacturing variability in mesh-style clock distribution Clock Skew evaluation considering manufacturing variability in mesh-style clock distribution ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 520-525 ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 520-525 ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 520-525 2008 Refereed English Research paper(international conference proceedings) Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 7-8 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 7-8 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 7-8 2008 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, J. Yamaguchi, H. Onodera M. Hashimoto, J. Yamaguchi, H. Onodera M. Hashimoto, J. Yamaguchi, H. Onodera Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2661-2668 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2661-2668 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2661-2668 2007/12 Refereed English Research paper(scientific journal) Disclose to all
Tsuchiya, Akira, Hashimoto, Masanori, Onodera, Hidetoshi Tsuchiya, Akira, Hashimoto, Masanori, Onodera, Hidetoshi Tsuchiya, Akira, Hashimoto, Masanori, Onodera, Hidetoshi Optimal termination of on-chip transmission-lines for high-speed signaling Optimal termination of on-chip transmission-lines for high-speed signaling Optimal termination of on-chip transmission-lines for high-speed signaling IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1267-1273 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1267-1273 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1267-1273 2007/06 Refereed English Research paper(scientific journal) Disclose to all
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 227-230 Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 227-230 Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 227-230 2007/05 Refereed English Research paper(international conference proceedings) Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross-sectional area and inductive crosstalk effect Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross-sectional area and inductive crosstalk effect Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross-sectional area and inductive crosstalk effect IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 4, 724-731 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 4, 724-731 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 4, 724-731 2007/04 Refereed English Research paper(scientific journal) Disclose to all
H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, M. Hashimoto H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, M. Hashimoto H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, M. Hashimoto Proposal of Metrics for SSTA Accuracy Evaluation Proposal of Metrics for SSTA Accuracy Evaluation Proposal of Metrics for SSTA Accuracy Evaluation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A, 4, 808-814 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A, 4, 808-814 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A, 4, 808-814 2007/04 Refereed English Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Quantitative prediction of on-chip capacitive and inductive crosstalk noise and discussion on wire cross-sectional area toward inductive crosstalk free interconnects Quantitative prediction of on-chip capacitive and inductive crosstalk noise and discussion on wire cross-sectional area toward inductive crosstalk free interconnects Quantitative prediction of on-chip capacitive and inductive crosstalk noise and discussion on wire cross-sectional area toward inductive crosstalk free interconnects PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 70-75 PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 70-75 PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 70-75 2007 Refereed English Research paper(international conference proceedings) Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Dynamic supply noise measurement with all digital gated oscillator for evaluating decoupling capacitance effect Dynamic supply noise measurement with all digital gated oscillator for evaluating decoupling capacitance effect Dynamic supply noise measurement with all digital gated oscillator for evaluating decoupling capacitance effect PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 783-786 PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 783-786 PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 783-786 2007 Refereed English Research paper(international conference proceedings) Disclose to all
Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 10, 868-872 IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 10, 868-872 IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 10, 868-872 2007 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki Special section on VLSI Design and CAD Algorithms Special section on VLSI Design and CAD Algorithms Special section on VLSI Design and CAD Algorithms IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377 2006/12 Research paper(scientific journal) Disclose to all
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3560-3568 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3560-3568 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3560-3568 2006/12 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Interconnect RL extraction based on transfer characteristics of transmission-line Interconnect RL extraction based on transfer characteristics of transmission-line Interconnect RL extraction based on transfer characteristics of transmission-line IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3585-3593 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3585-3593 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3585-3593 2006/12 Refereed English Research paper(scientific journal) Disclose to all
T. Sato, J. Ichimiya, N. Ono, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, M. Hashimoto On-chip Thermal Gradient Analysis Considering Interdependence Between Leakage Power and Temperature On-chip Thermal Gradient Analysis Considering Interdependence Between Leakage Power and Temperature On-chip Thermal Gradient Analysis Considering Interdependence Between Leakage Power and Temperature IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3491-3499 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3491-3499 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3491-3499 2006/12 Refereed English Disclose to all
T. Kouno, M. Hashimoto, H. Onodera T. Kouno, M. Hashimoto, H. Onodera T. Kouno, M. Hashimoto, H. Onodera Input capacitance modeling of logic gates for accurate static timing analysis Input capacitance modeling of logic gates for accurate static timing analysis Input capacitance modeling of logic gates for accurate static timing analysis 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, 453-456 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, 453-456 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, 453-456 2006/11 Refereed English Research paper(international conference proceedings) Disclose to all
小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜 小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜 統計的STAの有効性の検証手法 統計的STAの有効性の検証手法 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006/04 Refereed Japanese Research paper(other academic) Disclose to all
新開 健一, 橋本 昌宜, 黒川 敦, 尾上 孝雄 新開 健一, 橋本 昌宜, 黒川 敦, 尾上 孝雄 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006/04 Refereed Japanese Research paper(other academic) Disclose to all
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄 小笠原 泰弘, 橋本 昌宜, 尾上 孝雄 LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006/04 Refereed Japanese Research paper(other academic) Disclose to all
伊地知 孝仁, 橋本 昌宜, 高橋 真吾, 築山 修治, 白川 功 伊地知 孝仁, 橋本 昌宜, 高橋 真吾, 築山 修治, 白川 功 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 電子情報通信学会 VLSI設計技術研究会 電子情報通信学会 VLSI設計技術研究会 2006/03 Japanese Research paper(other academic) Disclose to all
上村 晋一朗, 土谷 亮, 橋本 昌宜, 小野寺 秀俊 上村 晋一朗, 土谷 亮, 橋本 昌宜, 小野寺 秀俊 ロードマップに準拠したSPICEトランジスタモデルの構築 ロードマップに準拠したSPICEトランジスタモデルの構築 2006年電子情報通信学会総合大会講演論文集 2006年電子情報通信学会総合大会講演論文集 2006/03 Japanese Research paper(other academic) Disclose to all
榎並 孝司, 橋本 昌宜, 尾上 孝雄 榎並 孝司, 橋本 昌宜, 尾上 孝雄 電源ノイズ解析のための回路動作部表現法の評価 電源ノイズ解析のための回路動作部表現法の評価 2006年電子情報通信学会総合大会講演論文集 2006年電子情報通信学会総合大会講演論文集 2006/03 Japanese Disclose to all
Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye A gate delay model focusing on current fluctuation over wide-range of process and environmental variability A gate delay model focusing on current fluctuation over wide-range of process and environmental variability A gate delay model focusing on current fluctuation over wide-range of process and environmental variability IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 215-+ IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 215-+ IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 215-+ 2006 Refereed English Research paper(international conference proceedings) Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Measurement of inductive coupling effect on timing in 90nm global interconnects Measurement of inductive coupling effect on timing in 90nm global interconnects Measurement of inductive coupling effect on timing in 90nm global interconnects PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 721-724 PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 721-724 PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 721-724 2006 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Interconnect RL extraction at a single representative frequency Interconnect RL extraction at a single representative frequency Interconnect RL extraction at a single representative frequency Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 515-520 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 515-520 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 515-520 2006/01 Refereed English Research paper(international conference proceedings) Disclose to all
Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye Ken'ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye A gate delay model focusing on current fluctuation over wide-range of process and environmental variability A gate delay model focusing on current fluctuation over wide-range of process and environmental variability A gate delay model focusing on current fluctuation over wide-range of process and environmental variability IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 47-53 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 47-53 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 47-53 2006 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction International Workshop on Compact Modeling International Workshop on Compact Modeling International Workshop on Compact Modeling 2006/01 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, T Yamamoto, H Onodera M Hashimoto, T Yamamoto, H Onodera M Hashimoto, T Yamamoto, H Onodera Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3375-3381 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3375-3381 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3375-3381 2005/12 Refereed English Research paper(scientific journal) Disclose to all
A. Muramatsu, M. Hashimoto, H. Onodera A. Muramatsu, M. Hashimoto, H. Onodera A. Muramatsu, M. Hashimoto, H. Onodera Effects of on-chip inductance on power distribution grid Effects of on-chip inductance on power distribution grid Effects of on-chip inductance on power distribution grid IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3564-3572 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3564-3572 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3564-3572 2005/12 Refereed English Research paper(scientific journal) Disclose to all
Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions, 88-A, 12, 3453-3462 IEICE Transactions, 88-A, 12, 3453-3462 IEICE Transactions, 88-A, 12, 3453-3462 2005/12 Refereed English Research paper(scientific journal) Disclose to all
T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera Successive pad assignment for minimizing supply voltage drop Successive pad assignment for minimizing supply voltage drop Successive pad assignment for minimizing supply voltage drop IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3429-3436 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3429-3436 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3429-3436 2005/12 Refereed English Research paper(scientific journal) Disclose to all
T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3429-3436 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3429-3436 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3429-3436 2005/12 Refereed English Disclose to all
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3382-3389 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3382-3389 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88-A, 12, 3382-3389 2005/12 Refereed English Disclose to all
土谷 亮, 新名 亮規, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 新名 亮規, 橋本 昌宜, 小野寺 秀俊 CMLを用いたオンチップ長距離高速信号伝送技術の開発 CMLを用いたオンチップ長距離高速信号伝送技術の開発 第9回システムLSIワークショップ 第9回システムLSIワークショップ 2005/11 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera Performance prediction of on-chip high-throughput global signaling Performance prediction of on-chip high-throughput global signaling Performance prediction of on-chip high-throughput global signaling IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 79-82 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 79-82 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 79-82 2005/10 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Design guideline for resistive termination of on-chip high-speed interconnects Design guideline for resistive termination of on-chip high-speed interconnects Design guideline for resistive termination of on-chip high-speed interconnects Proceedings of the Custom Integrated Circuits Conference, 613-616 Proceedings of the Custom Integrated Circuits Conference, 613-616 Proceedings of the Custom Integrated Circuits Conference, 613-616 2005/09 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, 201-202 Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, 201-202 Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, 201-202 2005/05 Refereed English Research paper(international conference proceedings) Disclose to all
土谷亮, 橋本昌宜, 小野寺秀俊 土谷亮, 橋本昌宜, 小野寺秀俊 オンチップ高速信号伝送用線路の解析的性能評価 オンチップ高速信号伝送用線路の解析的性能評価 信学技報, 49-54 信学技報, 49-54 , 49-54 2005/03/11 Japanese Research paper(research society, symposium, etc.) Disclose to all
T. Miyazaki, M. Hashimoto, H. Onodera T. Miyazaki, M. Hashimoto, H. Onodera T. Miyazaki, M. Hashimoto, H. Onodera A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL IEICE Transactions on Electronics, E88C, 3, 437-444 IEICE Transactions on Electronics, E88C, 3, 437-444 IEICE Transactions on Electronics, E88C, 3, 437-444 2005/03 Refereed English Research paper(scientific journal) Disclose to all
M Hashimoto, T Yamamoto, H Onodera M Hashimoto, T Yamamoto, H Onodera M Hashimoto, T Yamamoto, H Onodera Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 402-407 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 402-407 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 402-407 2005 Refereed English Research paper(international conference proceedings) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 オンチップ高速信号伝送における終端抵抗決定手法 オンチップ高速信号伝送における終端抵抗決定手法 第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005. 第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005. 2005 Refereed Japanese Research paper(research society, symposium, etc.) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 配線の伝達特性に基づく抽出周波数決定手法 配線の伝達特性に基づく抽出周波数決定手法 DAシンポジウム 2005, pp.169-174, Aug 2005. DAシンポジウム 2005, pp.169-174, Aug 2005. 2005 Refereed Japanese Research paper(research society, symposium, etc.) Disclose to all
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics 2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005 Refereed English Research paper(international conference proceedings) Disclose to all
A. Shinmyo, M. Hashimoto, H. Onodera A. Shinmyo, M. Hashimoto, H. Onodera A. Shinmyo, M. Hashimoto, H. Onodera Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, D9-D10 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, D9-D10 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, D9-D10 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Return path selection for loop RL extraction Return path selection for loop RL extraction Return path selection for loop RL extraction Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1078-1081 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1078-1081 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1078-1081 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
Y Ogasahara, M Hashimoto, T Onoye Y Ogasahara, M Hashimoto, T Onoye Y Ogasahara, M Hashimoto, T Onoye Measurement and analysis of delay variation due to inductive coupling Measurement and analysis of delay variation due to inductive coupling Measurement and analysis of delay variation due to inductive coupling CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 305-308 CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 305-308 CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 305-308 2005 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, J. Yamaguchi, H. Onodera M. Hashimoto, J. Yamaguchi, H. Onodera M. Hashimoto, J. Yamaguchi, H. Onodera Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 814-820 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 814-820 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 814-820 2004/11 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, A. Tsuchiya, H. Onodera M. Hashimoto, A. Tsuchiya, H. Onodera M. Hashimoto, A. Tsuchiya, H. Onodera On-chip global signaling by wave pipelining On-chip global signaling by wave pipelining On-chip global signaling by wave pipelining IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 311-314 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 311-314 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 311-314 2004/10 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference 2004/10 Refereed English Research paper(international conference proceedings) Disclose to all
金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦 金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 2004/07 Japanese Research paper(other academic) Disclose to all
佐藤 高史, 市宮 淳次, 小野 信任, 蜂屋 孝太郎, 橋本 昌宜 佐藤 高史, 市宮 淳次, 小野 信任, 蜂屋 孝太郎, 橋本 昌宜 フロアプランにおけるオンチップ熱ばらつきの解析と対策 フロアプランにおけるオンチップ熱ばらつきの解析と対策 2004/07 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 配線RL抽出におけるリターンパス選択手法 配線RL抽出におけるリターンパス選択手法 2004/07 Japanese Research paper(other academic) Disclose to all
村松 篤, 橋本 昌宜, 小野寺 秀俊 村松 篤, 橋本 昌宜, 小野寺 秀俊 オンチップインダクタンスを考慮したLSI電源配線網解析 オンチップインダクタンスを考慮したLSI電源配線網解析 2004/07 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- 2004/04 Japanese Research paper(other academic) Disclose to all
M Hashimoto, Y Yamada, H Onodera M Hashimoto, Y Yamada, H Onodera M Hashimoto, Y Yamada, H Onodera Equivalent, waveform propagation for static timing analysis Equivalent, waveform propagation for static timing analysis Equivalent, waveform propagation for static timing analysis IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 23, 4, 498-508 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 23, 4, 498-508 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 23, 4, 498-508 2004/04 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto, Y. Yamada, H. Onodera M. Hashimoto, Y. Yamada, H. Onodera M. Hashimoto, Y. Yamada, H. Onodera Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Trans. on CAD, 23, 4, 498-508 IEEE Trans. on CAD, 23, 4, 498-508 IEEE Trans. on CAD, 23, 4, 498-508 2004/04 Refereed English Research paper(scientific journal) Disclose to all
山口 隼司, 橋本 昌宜, 小野寺 秀俊 山口 隼司, 橋本 昌宜, 小野寺 秀俊 ゲート毎の電源電圧変動を考慮した静的遅延解析法 ゲート毎の電源電圧変動を考慮した静的遅延解析法 2004/03 Japanese Research paper(other academic) Disclose to all
村松 篤, 橋本 昌宜, 小野寺 秀俊 村松 篤, 橋本 昌宜, 小野寺 秀俊 電源電圧変動に対するオンチップ配線インダクタンスの影響 電源電圧変動に対するオンチップ配線インダクタンスの影響 2004/03 Japanese Research paper(other academic) Disclose to all
A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 2004 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, K Fujimori, H Onodera M Hashimoto, K Fujimori, H Onodera M Hashimoto, K Fujimori, H Onodera Automatic generation of standard cell library in VDSM technologies Automatic generation of standard cell library in VDSM technologies Automatic generation of standard cell library in VDSM technologies ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 36-41 ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 36-41 ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 36-41 2004 Refereed English Research paper(international conference proceedings) Disclose to all
T Miyazaki, M Hashimoto, H Onodera T Miyazaki, M Hashimoto, H Onodera T Miyazaki, M Hashimoto, H Onodera A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 545-546 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 545-546 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 545-546 2004 Refereed English Research paper(international conference proceedings) Disclose to all
A Tsuchiya, M Hashimoto, H Onodera A Tsuchiya, M Hashimoto, H Onodera A Tsuchiya, M Hashimoto, H Onodera Representative frequency for interconnect R(f)L(f)C extraction Representative frequency for interconnect R(f)L(f)C extraction Representative frequency for interconnect R(f)L(f)C extraction ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 2004 Refereed English Research paper(international conference proceedings) Disclose to all
A Tsuchiya, M Hashimoto, H Onodera A Tsuchiya, M Hashimoto, H Onodera A Tsuchiya, M Hashimoto, H Onodera Representative frequency for interconnect R(f)L(f)C extraction Representative frequency for interconnect R(f)L(f)C extraction Representative frequency for interconnect R(f)L(f)C extraction ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 691-696 2004 English Research paper(international conference proceedings) Disclose to all
M Hashimoto, Y Hayashi, H Onodera M Hashimoto, Y Hayashi, H Onodera M Hashimoto, Y Hayashi, H Onodera Experimental study on cell-base high-performance datapath design Experimental study on cell-base high-performance datapath design Experimental study on cell-base high-performance datapath design IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 3204-3207 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 3204-3207 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 3204-3207 2003/12 English Research paper(scientific journal) Disclose to all
M Hashimoto, M Takahashi, H Onodera M Hashimoto, M Takahashi, H Onodera M Hashimoto, M Takahashi, H Onodera Crosstalk noise estimation for generic RC trees Crosstalk noise estimation for generic RC trees Crosstalk noise estimation for generic RC trees IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 2965-2973 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 2965-2973 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 12, 2965-2973 2003/12 English Research paper(scientific journal) Disclose to all
村松 篤, 橋本 昌宜, 小野寺 秀俊 村松 篤, 橋本 昌宜, 小野寺 秀俊 電源配線の等価回路簡略化による電源解析高速化の検討 電源配線の等価回路簡略化による電源解析高速化の検討 2003/11 Japanese Research paper(other academic) Disclose to all
宮崎 崇仁, 橋本 昌宜, 小野寺 秀俊 宮崎 崇仁, 橋本 昌宜, 小野寺 秀俊 デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー , 27, 49, 29-34 , 27, 49, 29-34 , 27, 49, 29-34 2003/09 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 オンチップ高速信号配線における波形歪みの影響 オンチップ高速信号配線における波形歪みの影響 2003/09 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 直交配線を持つオンチップ伝送線路の特性評価 直交配線を持つオンチップ伝送線路の特性評価 2003/07 Japanese Research paper(other academic) Disclose to all
T. Kanamoto, T. Sato, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, M. Hashimoto 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜 T. Kanamoto, T. Sato, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, M. Hashimoto A Statistical Methodology for Screening Inductance Dominated Interconnects in Timing Analysis 遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法 A Statistical Methodology for Screening Inductance Dominated Interconnects in Timing Analysis IPSJ Transactions, 44, 5, 1301-1310 情報処理学会論文誌, 44, 5, 1301-1310 IPSJ Transactions, 44, 5, 1301-1310 2003/05 Japanese Research paper(scientific journal) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 配線R(f)L(f)C抽出のための代表周波数決定手法 配線R(f)L(f)C抽出のための代表周波数決定手法 2003/04 Japanese Research paper(other academic) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Frequency Determination for Interconnect RLC Extraction Frequency Determination for Interconnect RLC Extraction Frequency Determination for Interconnect RLC Extraction Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies 2003/04 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Yamada, M. Hashimoto, H. Onodera Y. Yamada, M. Hashimoto, H. Onodera Y. Yamada, M. Hashimoto, H. Onodera Slew Calculation against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis Slew Calculation against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis Slew Calculation against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies 2003/04 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, Y. Yamada, H. Onodera M. Hashimoto, Y. Yamada, H. Onodera M. Hashimoto, Y. Yamada, H. Onodera Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Proc. ACM/IEEE International Symposium on Physical Design Proc. ACM/IEEE International Symposium on Physical Design Proc. ACM/IEEE International Symposium on Physical Design 2003/04 Refereed English Research paper(international conference proceedings) Disclose to all
村松 篤, 橋本 昌宜, 小野寺 秀俊 村松 篤, 橋本 昌宜, 小野寺 秀俊 オンチップデカップリング容量の最適寄生抵抗値の決定法 オンチップデカップリング容量の最適寄生抵抗値の決定法 2003/03 Japanese Research paper(other academic) Disclose to all
宮崎 崇仁, 新名 亮規, 橋本 昌宜, 小野寺 秀俊 宮崎 崇仁, 新名 亮規, 橋本 昌宜, 小野寺 秀俊 オンチップオシロ用サンプルホールド回路の広周波数帯域化 オンチップオシロ用サンプルホールド回路の広周波数帯域化 2003/03 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 信号配線と下層配線との結合に対する直交配線の影響 信号配線と下層配線との結合に対する直交配線の影響 2003/03 Japanese Research paper(other academic) Disclose to all
橋本 昌宜 橋本 昌宜 LSI物理設計におけるSignal Integrity問題 LSI物理設計におけるSignal Integrity問題 2003/03 Japanese Research paper(other academic) Disclose to all
山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応-- 静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応-- 2003/01 Japanese Research paper(other academic) Disclose to all
M Hashimoto, K Fujimori, H Onodera M Hashimoto, K Fujimori, H Onodera M Hashimoto, K Fujimori, H Onodera Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 mu m technologies Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 mu m technologies Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 mu m technologies ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 589-590 ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 589-590 ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 589-590 2003 Refereed English Research paper(international conference proceedings) Disclose to all
T Sato, T Kanamoto, A Kurokawa, Y Kawakami, H Oka, T Kitaura, H Kobayashi, M Hashimoto T Sato, T Kanamoto, A Kurokawa, Y Kawakami, H Oka, T Kitaura, H Kobayashi, M Hashimoto T Sato, T Kanamoto, A Kurokawa, Y Kawakami, H Oka, T Kitaura, H Kobayashi, M Hashimoto Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 149-155 ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 149-155 ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 149-155 2003 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, H Onodera M Hashimoto, H Onodera M Hashimoto, H Onodera Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 12, 2799-2802 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 12, 2799-2802 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 12, 2799-2802 2002/12 English Research paper(scientific journal) Disclose to all
山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 容量性クロストークを考慮した高精度タイミング解析に関する研究 容量性クロストークを考慮した高精度タイミング解析に関する研究 2002/11 Japanese Research paper(other academic) Disclose to all
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜 インダクタンスに起因する配線遅延変動の統計的予測手法 インダクタンスに起因する配線遅延変動の統計的予測手法 2002/09 Japanese Research paper(other academic) Disclose to all
橋本 昌宜 橋本 昌宜 京大版スタンダードセルライブラリ 京大版スタンダードセルライブラリ 2002/09 Japanese Research paper(other academic) Disclose to all
平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊 平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊 長距離高速信号伝送を可能にするVLSI配線構造の検討 長距離高速信号伝送を可能にするVLSI配線構造の検討 2002/07 Japanese Research paper(other academic) Disclose to all
山口 隼司, 橋本 昌宜, 小野寺 秀俊 山口 隼司, 橋本 昌宜, 小野寺 秀俊 IRドロップを考慮した電源線構造の最適化手法 IRドロップを考慮した電源線構造の最適化手法 , 2002, 10, 253-258 , 2002, 10, 253-258 , 2002, 10, 253-258 2002/07 Japanese Research paper(other academic) Disclose to all
金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜 金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜 0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法 0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法 2002/07 Japanese Research paper(other academic) Disclose to all
林 宙輝, 橋本 昌宜, 小野寺 秀俊 林 宙輝, 橋本 昌宜, 小野寺 秀俊 セルベース設計環境を用いた高性能データパス設計法の検討 セルベース設計環境を用いた高性能データパス設計法の検討 2002/07 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, Y. Hayashi, H. Onodera M. Hashimoto, Y. Hayashi, H. Onodera M. Hashimoto, Y. Hayashi, H. Onodera Experimental Study on Cell-Base High-Performance Datapath Design Experimental Study on Cell-Base High-Performance Datapath Design Experimental Study on Cell-Base High-Performance Datapath Design Proc. IEEE/ACM International Workshop on Logic & Synthesis Proc. IEEE/ACM International Workshop on Logic & Synthesis Proc. IEEE/ACM International Workshop on Logic & Synthesis 2002/06 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera 土谷 亮, 橋本 昌宜, 小野寺 秀俊 A. Tsuchiya, M. Hashimoto, H. Onodera Driver Sizing for High-Performace Interconnects Considering Transmission-Line Effects VLSI 配線の伝送線路特性を考慮した駆動力決定手法 Driver Sizing for High-Performace Interconnects Considering Transmission-Line Effects IPSJ Transactions, 43, 5, 1338-1347 情報処理学会論文誌, 43, 5, 1338-1347 IPSJ Transactions, 43, 5, 1338-1347 2002/05 Japanese Research paper(scientific journal) Disclose to all
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜 インダクタンスが配線遅延に及ぼす影響の定量的評価方法 インダクタンスが配線遅延に及ぼす影響の定量的評価方法 2002/04 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, M. Takahashi, H. Onodera M. Hashimoto, M. Takahashi, H. Onodera M. Hashimoto, M. Takahashi, H. Onodera Crosstalk Noise Optimization by Post-Layout Transistor Sizing Crosstalk Noise Optimization by Post-Layout Transistor Sizing Crosstalk Noise Optimization by Post-Layout Transistor Sizing Proc. ACM/IEEE International Symposium on Physical Design Proc. ACM/IEEE International Symposium on Physical Design Proc. ACM/IEEE International Symposium on Physical Design 2002/04 Refereed English Research paper(international conference proceedings) Disclose to all
藤森 一憲, 橋本 昌宜, 小野寺 秀俊 藤森 一憲, 橋本 昌宜, 小野寺 秀俊 駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発 駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発 , 101, 696, 9-16 , 101, 696, 9-16 , 101, 696, 9-16 2002/03 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 LSI配線インダクタンスに対する直交配線の影響 LSI配線インダクタンスに対する直交配線の影響 2002/03 Japanese Research paper(other academic) Disclose to all
山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 山田 祐嗣, 橋本 昌宜, 小野寺 秀俊 ゲート出力波形導出時の誤差要因とその影響の評価 ゲート出力波形導出時の誤差要因とその影響の評価 2002/03 Japanese Research paper(other academic) Disclose to all
M Hashimoto, D Hiramatsu, A Tsuchiya, H Onodera M Hashimoto, D Hiramatsu, A Tsuchiya, H Onodera M Hashimoto, D Hiramatsu, A Tsuchiya, H Onodera Interconnect structures for high-speed long-distance signal transmission Interconnect structures for high-speed long-distance signal transmission Interconnect structures for high-speed long-distance signal transmission 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 426-430 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 426-430 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 426-430 2002 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, H Onodera M Hashimoto, H Onodera M Hashimoto, H Onodera Post-layout transistor sizing for power reduction in cell-base design Post-layout transistor sizing for power reduction in cell-base design Post-layout transistor sizing for power reduction in cell-base design IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 11, 2769-2777 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 11, 2769-2777 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 11, 2769-2777 2001/11 Refereed English Research paper(scientific journal) Disclose to all
橋本 昌宜, 高橋 正郎, 小野寺 秀俊 橋本 昌宜, 高橋 正郎, 小野寺 秀俊 ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法 ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法 , 117, 117, 39-44 , 117, 117, 39-44 , 117, 117, 39-44 2001/11 Japanese Research paper(other academic) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera A. Tsuchiya, M. Hashimoto, H. Onodera Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies Proc. Workshop on Synthesis and System Integration of Mixed Technologies 2001/10 Refereed English Research paper(international conference proceedings) Disclose to all
橋本 昌宜, 高橋 正郎, 小野寺 秀俊 橋本 昌宜, 高橋 正郎, 小野寺 秀俊 ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法 ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法 , 117, 117, 39-44 , 117, 117, 39-44 , 117, 117, 39-44 2001/09 Japanese Research paper(other academic) Disclose to all
高橋 正郎, 橋本 昌宜, 小野寺 秀俊 高橋 正郎, 橋本 昌宜, 小野寺 秀俊 波形重ね合せによるクロストーク遅延変動量の見積もり手法 波形重ね合せによるクロストーク遅延変動量の見積もり手法 2001/09 Japanese Research paper(other academic) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 長距離高速配線における RC モデルに基づく回路設計の限界 長距離高速配線における RC モデルに基づく回路設計の限界 2001/09 Japanese Research paper(other academic) Disclose to all
高橋 正郎, 橋本 昌宜, 小野寺 秀俊 高橋 正郎, 橋本 昌宜, 小野寺 秀俊 隣接位置を考慮した解析的クロストークノイズ見積もり手法 隣接位置を考慮した解析的クロストークノイズ見積もり手法 2001/07 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 379-382 Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 379-382 Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 379-382 2001/05 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera Increase in Delay Uncertainty by Performance Optimization Increase in Delay Uncertainty by Performance Optimization Increase in Delay Uncertainty by Performance Optimization Proc. IEEE International Symposium on Circuits and Systems, 85, 12, 2799-2802 Proc. IEEE International Symposium on Circuits and Systems, 85, 12, 2799-2802 Proc. IEEE International Symposium on Circuits and Systems, 85, 12, 2799-2802 2001/05 Refereed English Research paper(international conference proceedings) Disclose to all
高橋 正郎, 橋本 昌宜, 小野寺 秀俊 高橋 正郎, 橋本 昌宜, 小野寺 秀俊 隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 --- 隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 --- 2001/03 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 高橋 正郎, 小野寺 秀俊 橋本 昌宜, 高橋 正郎, 小野寺 秀俊 隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用--- 隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用--- 2001/03 Japanese Research paper(other academic) Disclose to all
M Hashimoto, H Onodera M Hashimoto, H Onodera M Hashimoto, H Onodera Post-layout transistor sizing for power reduction in cell-based design Post-layout transistor sizing for power reduction in cell-based design Post-layout transistor sizing for power reduction in cell-based design PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 2001 English Research paper(international conference proceedings) Disclose to all
M Takahashi, M Hashimoto, H Onodera M Takahashi, M Hashimoto, H Onodera M Takahashi, M Hashimoto, H Onodera Crosstalk noise estimation for generic RC trees Crosstalk noise estimation for generic RC trees Crosstalk noise estimation for generic RC trees 2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 110-116 2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 110-116 2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 110-116 2001 Refereed English Research paper(international conference proceedings) Disclose to all
H Onodera, M Hashimoto, T Hashimoto H Onodera, M Hashimoto, T Hashimoto H Onodera, M Hashimoto, T Hashimoto ASIC design methodology with on-demand library generation ASIC design methodology with on-demand library generation ASIC design methodology with on-demand library generation 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 57-60 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 57-60 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 57-60 2001 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, H Onodera M Hashimoto, H Onodera M Hashimoto, H Onodera Post-layout transistor sizing for power reduction in cell-based design Post-layout transistor sizing for power reduction in cell-based design Post-layout transistor sizing for power reduction in cell-based design PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 359-365 2001 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems 2000/12 Refereed English Research paper(international conference proceedings) Disclose to all
M Hashimoto, H Onodera M Hashimoto, H Onodera M Hashimoto, H Onodera A performance optimization method by gate resizing based on statistical static timing analysis A performance optimization method by gate resizing based on statistical static timing analysis A performance optimization method by gate resizing based on statistical static timing analysis IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E83A, 12, 2558-2568 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E83A, 12, 2558-2568 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E83A, 12, 2558-2568 2000/12 English Research paper(scientific journal) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 パスバランス回路における遅延不確かさの統計的解析 パスバランス回路における遅延不確かさの統計的解析 , 100, 474, 17-22 , 100, 474, 17-22 , 100, 474, 17-22 2000/11 Japanese Research paper(other academic) Disclose to all
橋本 昌宜 橋本 昌宜 オンデマンドライブラリを用いた最適LSI設計手法 オンデマンドライブラリを用いた最適LSI設計手法 2000/09 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 パスバランス回路における遅延不確かさの統計的解析 パスバランス回路における遅延不確かさの統計的解析 , 100, 474, 17-22 , 100, 474, 17-22 , 100, 474, 17-22 2000/09 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法 セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法 2000/07 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法 静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法 2000/04 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis Proc. Workshop on Synthesis and System Integration of Mixed Technologies, 83, 12, 2558-2568 Proc. Workshop on Synthesis and System Integration of Mixed Technologies, 83, 12, 2558-2568 Proc. Workshop on Synthesis and System Integration of Mixed Technologies, 83, 12, 2558-2568 2000/04 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera M. Hashimoto, H. Onodera A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis Proc. ACM International Symposium on Physical Design Proc. ACM International Symposium on Physical Design Proc. ACM International Symposium on Physical Design 2000/04 Refereed English Research paper(international conference proceedings) Disclose to all
橋本 昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺 秀俊 橋本 昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺 秀俊 オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 , 99, 660, 31-38 , 99, 660, 31-38 , 99, 660, 31-38 2000/03 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 静的統計遅延解析を用いた最悪遅延時間計算手法 静的統計遅延解析を用いた最悪遅延時間計算手法 2000/03 Japanese Research paper(other academic) Disclose to all
T Iwahashi, T Shibayama, M Hashimoto, K Kobayashi, H Onodera T Iwahashi, T Shibayama, M Hashimoto, K Kobayashi, H Onodera T Iwahashi, T Shibayama, M Hashimoto, K Kobayashi, H Onodera Vector quantization processor for mobile video communication Vector quantization processor for mobile video communication Vector quantization processor for mobile video communication 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 75-79 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 75-79 13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 75-79 2000 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera 橋本昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺秀俊 Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 1999/11/01 Japanese Research paper(research society, symposium, etc.) Disclose to all
橋本 昌宜, 橋本 鉄太郎, 西川 亮太, 福田 大輔, 黒田 慎介, 菅 俊介, 神原 弘之, 小野寺 秀俊 橋本 昌宜, 橋本 鉄太郎, 西川 亮太, 福田 大輔, 黒田 慎介, 菅 俊介, 神原 弘之, 小野寺 秀俊 オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 , 99, 660, 31-38 , 99, 660, 31-38 , 99, 660, 31-38 1999/11 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊 橋本 昌宜, 小野寺 秀俊 スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討 スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討 1999/09 Japanese Research paper(other academic) Disclose to all
M. Hashimoto, H. Onodera, K. Tamaru M. Hashimoto, H. Onodera, K. Tamaru M. Hashimoto, H. Onodera, K. Tamaru A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design Proc. IEEE/ACM Design Automation Conference Proc. IEEE/ACM Design Automation Conference Proc. IEEE/ACM Design Automation Conference 1999/06 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto, H. Onodera, K. Tamaru 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 M. Hashimoto, H. Onodera, K. Tamaru A Power Optimization Method Considering Glitch Reduction by Gate Sizing グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 A Power Optimization Method Considering Glitch Reduction by Gate Sizing IPSJ Transactions 情報処理学会論文誌 IPSJ Transactions 1999/04 Japanese Research paper(scientific journal) Disclose to all
M Hashimoto, H Onodera, K Tamaru M Hashimoto, H Onodera, K Tamaru M Hashimoto, H Onodera, K Tamaru A power and delay optimization method using input reordering in cell-based CMOS circuits A power and delay optimization method using input reordering in cell-based CMOS circuits A power and delay optimization method using input reordering in cell-based CMOS circuits IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 1, 159-166 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 1, 159-166 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 1, 159-166 1999/01 Refereed English Research paper(scientific journal) Disclose to all
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用--- グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用--- 1998/09 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 1998/07 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 論理シミュレーションを用いた消費電力見積もりの高精度化手法 論理シミュレーションを用いた消費電力見積もりの高精度化手法 1998/03 Japanese Research paper(other academic) Disclose to all
M Hasimoto, H Onodera, K Tamaru M Hasimoto, H Onodera, K Tamaru M Hasimoto, H Onodera, K Tamaru A power optimization method considering glitch reduction by gate sizing A power optimization method considering glitch reduction by gate sizing A power optimization method considering glitch reduction by gate sizing 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 40, 4, 221-226 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 40, 4, 221-226 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 40, 4, 221-226 1998 Refereed English Research paper(international conference proceedings) Disclose to all
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 入力端子接続最適化による遅延時間と消費電力の最適化手法 入力端子接続最適化による遅延時間と消費電力の最適化手法 1997/09 Japanese Research paper(other academic) Disclose to all
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 橋本 昌宜, 小野寺 秀俊, 田丸 啓吉 入力端子接続最適化による消費電力削減手法 入力端子接続最適化による消費電力削減手法 1997/07 Japanese Research paper(other academic) Disclose to all
M Hashimoto, H Onodera, K Tamaru M Hashimoto, H Onodera, K Tamaru M Hashimoto, H Onodera, K Tamaru Input reordering for power and delay optimization Input reordering for power and delay optimization Input reordering for power and delay optimization TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 194-198 TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 194-198 TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 194-198 1997 Refereed English Research paper(international conference proceedings) Disclose to all

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Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
増田豊, 橋本昌宜 増田豊, 橋本昌宜 性能ばらつきを克服する適応的電圧制御の設計と製造後テスト手法 性能ばらつきを克服する適応的電圧制御の設計と製造後テスト手法 電子情報通信学 会LSI とシステムのワークショップ 電子情報通信学 会LSI とシステムのワークショップ 2018/05 Japanese Research paper, summary (national conference and other science council) Disclose to all
Y. Masuda, M. Hashimoto Y. Masuda, M. Hashimoto Y. Masuda, M. Hashimoto Design and test of adaptively voltage scaled circuits Design and test of adaptively voltage scaled circuits Design and test of adaptively voltage scaled circuits SIGDA Student Research Forum at 23rd Asia and South Pacic Design Automation Conference SIGDA Student Research Forum at 23rd Asia and South Pacic Design Automation Conference SIGDA Student Research Forum at 23rd Asia and South Pacic Design Automation Conference 2018/01 Refereed English Article, review, commentary, editorial, etc.(other) Disclose to all
増田豊, 橋本昌宜, 尾上孝雄 増田豊, 橋本昌宜, 尾上孝雄 マージンの最小化に向けた適応的速度制御の設計と性能評価 マージンの最小化に向けた適応的速度制御の設計と性能評価 STARC フォーラム2015 STARC フォーラム2015 2015/11 Japanese Research paper, summary (national conference and other science council) Disclose to all
Sato Masahiro, Izuka Syoichi, Awano Hiromitsu, Hashimoto Masanori, Onoye Takao 佐藤 雅紘, 飯塚 翔一, 粟野 皓光, 橋本 昌宜, 尾上 孝雄 Sato Masahiro, Izuka Syoichi, Awano Hiromitsu, Hashimoto Masanori, Onoye Takao A-3-5 On Stochastic modeling of NBTI induced threshold voltage variation A-3-5 NBTIによる閾値電圧変化の確率的モデル化に関する一考察(A-3.VLSI設計技術,一般セッション) A-3-5 On Stochastic modeling of NBTI induced threshold voltage variation Proceedings of the IEICE General Conference, 2015, 84-84 電子情報通信学会総合大会講演論文集, 2015, 84-84 Proceedings of the IEICE General Conference, 2015, 84-84 2015/02/24 Japanese Disclose to all
Masuda Ryohei, Hashimoto Masanori, Onoye Takao 益田 涼平, 橋本 昌宣, 尾上 孝雄 Masuda Ryohei, Hashimoto Masanori, Onoye Takao B-18-48 Performance evaluation of human detection with thermopile infrared sensor B-18-48 サーモパイル型赤外線センサを用いた人感センサの性能評価(B-18.知的環境とセンサネットワーク,一般セッション) B-18-48 Performance evaluation of human detection with thermopile infrared sensor Proceedings of the IEICE General Conference, 2015, 2, 595-595 電子情報通信学会総合大会講演論文集, 2015, 2, 595-595 Proceedings of the IEICE General Conference, 2015, 2, 595-595 2015/02/24 Japanese Disclose to all
鵜川 翔平, 信田 龍哉, 橋本 昌宜, 伊藤 雄一, 尾上 孝雄 鵜川 翔平, 信田 龍哉, 橋本 昌宜, 伊藤 雄一, 尾上 孝雄 クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定 クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定 研究報告ヒューマンコンピュータインタラクション(HCI), 2015, 11, 1-7 研究報告ヒューマンコンピュータインタラクション(HCI), 2015, 11, 1-7 , 2015, 11, 1-7 2015/01/07 Japanese Disclose to all
DOI Ryutaro, HASHIMOTO Masanori, ONOYE Takao 土井 龍太郎, 橋本 昌宜, 尾上 孝雄 DOI Ryutaro, HASHIMOTO Masanori, ONOYE Takao An analytic evaluation on soft error immunity enhancement due to temporal triplication 時間的三重化によるソフトエラー耐性向上の解析的評価 (VLSI設計技術) -- (デザインガイア2014 : VLSI設計の新しい大地) An analytic evaluation on soft error immunity enhancement due to temporal triplication Technical report of IEICE. VLD, 114, 328, 263-268 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 328, 263-268 Technical report of IEICE. VLD, 114, 328, 263-268 2014/11/26 Japanese Disclose to all
KONO Jin, UKAWA Shohei, SHINADA Tatsuya, TSUKAMOTO Mizuho, TANAKA Yuki, NAKAJIMA Kosuke, ITOH Yuichi, HIROSE Tetsuya, HASHIMOTO Masanori 河野 仁, 鵜川 翔平, 信田 龍哉, 塚元 瑞穂, 田中 勇気, 中島 康祐, 伊藤 雄一, 廣瀬 哲也, 橋本 昌宜 KONO Jin, UKAWA Shohei, SHINADA Tatsuya, TSUKAMOTO Mizuho, TANAKA Yuki, NAKAJIMA Kosuke, ITOH Yuichi, HIROSE Tetsuya, HASHIMOTO Masanori リアルタイム3次元モデリングシステムiClayの実現に向けた1mm3級センサノードの要素技術開発 リアルタイム3次元モデリングシステムiClayの実現に向けた1mm3級センサノードの要素技術開発 リアルタイム3次元モデリングシステムiClayの実現に向けた1mm3級センサノードの要素技術開発 電子情報通信学会 集積回路研究専門委員会 LSIとシステムのワークショップ2014, 1-18 電子情報通信学会 集積回路研究専門委員会 LSIとシステムのワークショップ2014, 1-18 電子情報通信学会 集積回路研究専門委員会 LSIとシステムのワークショップ2014, 1-18 2014/05 Japanese Lecture material (seminar, tutorial, course, lecture, etc.) Disclose to all
KONOURA HIROAKI, MITSUYAMA YUKIO, HASHIMOTO MASANORI, ONOYE TAKAO 郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄 KONOURA HIROAKI, MITSUYAMA YUKIO, HASHIMOTO MASANORI, ONOYE TAKAO Placement and routing for enhancing fault avoidance by dynamically partial reconfiguration 動的部分再構成による故障回避に適した配置配線手法の検討 (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014) Placement and routing for enhancing fault avoidance by dynamically partial reconfiguration IEICE technical report. Dependable computing, 113, 498, 115-120 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113, 498, 115-120 IEICE technical report. Dependable computing, 113, 498, 115-120 2014/03/15 Japanese Disclose to all
UKAWA Shohei, SHINADA Tatsuya, ITOH Yuichi, HASHIMOTO Masanori, ONOYE Takao 鵜川 翔平, 信田 龍哉, 伊藤 雄一, 橋本 昌宜, 尾上 孝雄 UKAWA Shohei, SHINADA Tatsuya, ITOH Yuichi, HASHIMOTO Masanori, ONOYE Takao Evaluating a sequential 3D node localization method based on node-to-node distance information ノード間距離情報に基づいた逐次的3次元ノード位置推定手法の検討 (回路とシステム) Evaluating a sequential 3D node localization method based on node-to-node distance information IEICE technical report. Circuits and systems, 113, 463, 199-204 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113, 463, 199-204 IEICE technical report. Circuits and systems, 113, 463, 199-204 2014/03/06 Japanese Disclose to all
HASHIMOTO Masanori 橋本 昌宜 HASHIMOTO Masanori Adaptive Performance Compensation with On-Chip Variation Monitoring オンチップばらつきモニタリングによる適応的性能補償 (集積回路) Adaptive Performance Compensation with On-Chip Variation Monitoring Technical report of IEICE. ICD, 113, 419, 1-6 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113, 419, 1-6 Technical report of IEICE. ICD, 113, 419, 1-6 2014/01/28 Japanese Disclose to all
SATO Takashi, HASHIMOTO Masanori 佐藤 高史, 橋本 昌宜 SATO Takashi, HASHIMOTO Masanori 5.1 Time Dependent Degradation(5. Time-Dependent Degradation in Device Characteristics,<Special Survey>Dependable VLSI System) 5.1 経時劣化概説(第5章:素子特性経時劣化,<特集>ディペンダブルVLSIシステム) 5.1 Time Dependent Degradation(5. Time-Dependent Degradation in Device Characteristics,<Special Survey>Dependable VLSI System) The journal of Reliability Engineering Association of Japan, 35, 8, 457-458 日本信頼性学会誌 : 信頼性, 35, 8, 457-458 The journal of Reliability Engineering Association of Japan, 35, 8, 457-458 2013/12/01 Japanese Disclose to all
T. Sato, M. Hashimoto T. Sato, M. Hashimoto T. Sato, M. Hashimoto Time Dependent Degradation (Invited) Time Dependent Degradation (Invited) Time Dependent Degradation (Invited) The Journal of Reliability Engineering Association of Japan, 35, 8, 457-458 The Journal of Reliability Engineering Association of Japan, 35, 8, 457-458 The Journal of Reliability Engineering Association of Japan, 35, 8, 457-458 2013/12 Refereed English Disclose to all
ONOYE Takao, HASHIMOTO Masanori, MITSUYAMA Yukio, ALNAJJAR Dawood, KONOURA Hiroaki 尾上 孝雄, 橋本 昌宜, 密山 幸男, ALNAJJAR Dawood, 郡浦 宏明 ONOYE Takao, HASHIMOTO Masanori, MITSUYAMA Yukio, ALNAJJAR Dawood, KONOURA Hiroaki Toward VLSI Reliability Enhancement by Reconfigurable Architecture VLSIの信頼性を向上させる再構成可能アーキテクチャ(デザインガイア2013-VLSI設計の新しい大地-) Toward VLSI Reliability Enhancement by Reconfigurable Architecture IEICE technical report. Dependable computing, 113, 321, 183-183 電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング, 113, 321, 183-183 IEICE technical report. Dependable computing, 113, 321, 183-183 2013/11/20 Japanese Disclose to all
SHINADA Tatsuya, HASHIMOTO Masanori, ONOYE Takao 信田 龍哉, 橋本 昌宜, 尾上 孝雄 SHINADA Tatsuya, HASHIMOTO Masanori, ONOYE Takao A Study on Electrode Configuration for Distance Estimation based on Capacitive Coupling between Sensor Nodes センサノード間静電容量結合に基づく距離推定に向けた電極形状の検討 (通信方式) A Study on Electrode Configuration for Distance Estimation based on Capacitive Coupling between Sensor Nodes IEICE technical report. Communication systems, 112, 486, 131-136 電子情報通信学会技術研究報告 : 信学技報, 112, 486, 131-136 IEICE technical report. Communication systems, 112, 486, 131-136 2013/03/14 Japanese Disclose to all
HIGUCHI Yuma, HASHIMOTO Masanori, ONOYE Takao 樋口 裕磨, 橋本 昌宜, 尾上 孝雄 HIGUCHI Yuma, HASHIMOTO Masanori, ONOYE Takao Self-Compensation of Manufacturing Variability using On-Chip Sensors オンチップセンサを用いたばらつき自己補償手法の検討 (VLSI設計技術) Self-Compensation of Manufacturing Variability using On-Chip Sensors Technical report of IEICE. VLD, 112, 451, 13-17 電子情報通信学会技術研究報告 : 信学技報, 112, 451, 13-17 Technical report of IEICE. VLD, 112, 451, 13-17 2013/03/04 Japanese Disclose to all
AMAKI Takehiko, HASHIMOTO Masanori, MITSUYAMA Yukio, ONOYE Takao 天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄 AMAKI Takehiko, HASHIMOTO Masanori, MITSUYAMA Yukio, ONOYE Takao A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling 確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法 (VLSI設計技術) A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling Technical report of IEICE. VLD, 112, 451, 99-104 電子情報通信学会技術研究報告 : 信学技報, 112, 451, 99-104 Technical report of IEICE. VLD, 112, 451, 99-104 2013/03/04 Japanese Disclose to all
KONOURA Hiroaki, IMAGAWA Takashi, MITSUYAMA Yukio, HASHIMOTO Masanori, ONOYE Takao 郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄 KONOURA Hiroaki, IMAGAWA Takashi, MITSUYAMA Yukio, HASHIMOTO Masanori, ONOYE Takao An observational study on fault-avoidance methods using dynamic partial reconfiguration 動的部分再構成による故障回避に関する一考察 An observational study on fault-avoidance methods using dynamic partial reconfiguration IEICE technical report, 112, 325, 71-76 電子情報通信学会技術研究報告. RECONF, リコンフィギャラブルシステム : IEICE technical report, 112, 325, 71-76 IEICE technical report, 112, 325, 71-76 2012/11/20 Japanese Disclose to all
HARADA Ryo, MITSUYAMA Yukio, HASHIMOTO Masanori, ONOYE Takao 原田 諒, 密山 幸男, 橋本 昌宜, 尾上 孝雄 HARADA Ryo, MITSUYAMA Yukio, HASHIMOTO Masanori, ONOYE Takao neutron Induced Single Event Multiple Transients With Voltage Scaling and body Biasing 中性子起因SEMTの電源電圧及び基板バイアス依存性測定 neutron Induced Single Event Multiple Transients With Voltage Scaling and body Biasing IEICE technical report. Dependable computing, 112, 321, 237-241 電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング : IEICE technical report, 112, 321, 237-241 IEICE technical report. Dependable computing, 112, 321, 237-241 2012/11/19 Japanese Disclose to all
Ueno Miho, Hashimoto Masanori, Onoye Takao 上野 美保, 橋本 昌宜, 尾上 孝雄 Ueno Miho, Hashimoto Masanori, Onoye Takao A-3-6 An On-chip Real-time Supply Voltage Sensor for Debugging Electrical Timing Failures A-3-6 電気的タイミング故障のデバッグ向けオンチップリアルタイム電源電圧センサ(A-3.VLSI設計技術,一般セッション) A-3-6 An On-chip Real-time Supply Voltage Sensor for Debugging Electrical Timing Failures Proceedings of the Society Conference of IEICE, 2012, 53-53 電子情報通信学会ソサイエティ大会講演論文集, 2012, 53-53 Proceedings of the Society Conference of IEICE, 2012, 53-53 2012/08/28 Japanese Disclose to all
小谷 憲, 増田 弘生, 成木 保文, 奥村 隆昌, 城間 誠, 金本 俊幾, 古川 且洋, 山中 俊輝, 小笠原 泰弘, 佐藤 高史, 橋本 昌宜, 黒川 敦, 田中 正和 小谷 憲, 増田 弘生, 成木 保文, 奥村 隆昌, 城間 誠, 金本 俊幾, 古川 且洋, 山中 俊輝, 小笠原 泰弘, 佐藤 高史, 橋本 昌宜, 黒川 敦, 田中 正和 微細CMOSタイミング設計の新しいコーナー削減手法 微細CMOSタイミング設計の新しいコーナー削減手法 DA シンポジウム, 193-198 DA シンポジウム, 193-198 , 193-198 2012/08 Japanese Disclose to all
城間 誠, 山中 俊輝, 小笠原 泰弘, 金本 俊幾, 成木 保文, 奥村 隆昌, 増田 弘生, 古川 且洋, 佐藤 高史, 橋本 昌宜, 黒川 敦, 田中 正和 城間 誠, 山中 俊輝, 小笠原 泰弘, 金本 俊幾, 成木 保文, 奥村 隆昌, 増田 弘生, 古川 且洋, 佐藤 高史, 橋本 昌宜, 黒川 敦, 田中 正和 微細プロセス(22nm世代)における配線コーナー削減手法の検討 微細プロセス(22nm世代)における配線コーナー削減手法の検討 DA シンポジウム, 199-204 DA シンポジウム, 199-204 , 199-204 2012/08 Japanese Disclose to all
Tsukamoto M., Hirose T., Osaki Y., Kuroki N., Numa M., Hashimoto M. 塚元 瑞穂, 廣瀬 哲也, 大崎 勇士, 黒木 修隆, 沼 昌宏, 橋本 昌宜 Tsukamoto M., Hirose T., Osaki Y., Kuroki N., Numa M., Hashimoto M. A-1-20 Improvement of Efficiency by Reduction in Reverse Current of Differential-Drive CMOS Rectifier A-1-20 逆流電流削減による差動型整流回路の変換効率改善(A-1.回路とシステム,一般セッション) A-1-20 Improvement of Efficiency by Reduction in Reverse Current of Differential-Drive CMOS Rectifier Proceedings of the IEICE General Conference, 2012, 20-20 電子情報通信学会総合大会講演論文集, 2012, 20-20 Proceedings of the IEICE General Conference, 2012, 20-20 2012/03/06 Japanese Disclose to all
HOMJAKOVS Igors, HASHIMOTO Masanori, HIROSE Tetsuya, ONOYE Takao HOMJAKOVS Igors, HASHIMOTO Masanori, HIROSE Tetsuya, ONOYE Takao HOMJAKOVS Igors, HASHIMOTO Masanori, HIROSE Tetsuya, ONOYE Takao Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling (集積回路) Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling Technical report of IEICE. ICD, 111, 352, 105-107 電子情報通信学会技術研究報告 : 信学技報, 111, 352, 105-107 Technical report of IEICE. ICD, 111, 352, 105-107 2011/12/15 English Disclose to all
AMAKI Takehiko, HASHIMOTO Masanori, ONOYE Takao 天木 健彦, 橋本 昌宜, 尾上 孝雄 AMAKI Takehiko, HASHIMOTO Masanori, ONOYE Takao An Oscillator-Based True Random Number Generator with Jitter Amplifier ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器 (集積回路) An Oscillator-Based True Random Number Generator with Jitter Amplifier Technical report of IEICE. ICD, 111, 352, 87-92 電子情報通信学会技術研究報告 : 信学技報, 111, 352, 87-92 Technical report of IEICE. ICD, 111, 352, 87-92 2011/12/15 Japanese Disclose to all
HASHIMOTO Masanori 橋本 昌宜 HASHIMOTO Masanori Ultra Low Voltage Subthreshold Circuit Design 超低電圧サブスレショルド回路設計 (ディペンダブルコンピューティング) Ultra Low Voltage Subthreshold Circuit Design IEICE technical report. Dependable computing, 111, 325, 173-178 電子情報通信学会技術研究報告 : 信学技報, 111, 325, 173-178 IEICE technical report. Dependable computing, 111, 325, 173-178 2011/11/28 Japanese Disclose to all
佐方 剛, 成木 保文, 奥村 隆昌, 金本 俊幾, 増田 弘生, 佐藤 高史, 橋本 昌宜, 古川 且洋, 田中 正和, 山中俊輝 佐方 剛, 成木 保文, 奥村 隆昌, 金本 俊幾, 増田 弘生, 佐藤 高史, 橋本 昌宜, 古川 且洋, 田中 正和, 山中俊輝 CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析 CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析 DA シンポジウム, 195-200 DA シンポジウム, 195-200 , 195-200 2011/08 Japanese Disclose to all
増田 弘生, 佐方 剛, 佐藤 高史, 橋本 昌宜, 古川 且洋, 田中 正和, 山中 俊輝, 金本俊幾 増田 弘生, 佐方 剛, 佐藤 高史, 橋本 昌宜, 古川 且洋, 田中 正和, 山中 俊輝, 金本俊幾 RTNを考慮した回路特性ばらつき解析方法の検討 RTNを考慮した回路特性ばらつき解析方法の検討 DA シンポジウム, 209-214 DA シンポジウム, 209-214 , 209-214 2009/08 Japanese Disclose to all
榎並 孝司, 橋本 昌宜, 佐藤 高史 榎並 孝司, 橋本 昌宜, 佐藤 高史 電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法 電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法 信学技報 VLSI設計技術研究会, VLD09-36, 207-212 信学技報 VLSI設計技術研究会, VLD09-36, 207-212 , VLD09-36, 207-212 2009/03 Japanese Disclose to all
T. Enami, M. Hashimoto, T. Sato T. Enami, M. Hashimoto, T. Sato T. Enami, M. Hashimoto, T. Sato Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 420-425 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 420-425 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 420-425 2008/11 Refereed English Disclose to all
増田 弘生, 大川 眞一, 黄田 剛, 奥村 隆昌, 黒川 敦, 増田 弘生, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任 増田 弘生, 大川 眞一, 黄田 剛, 奥村 隆昌, 黒川 敦, 増田 弘生, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任 チップ内システマティックばらつきと回路スキュー特性相関 チップ内システマティックばらつきと回路スキュー特性相関 第21回 回路とシステム軽井沢ワークショップ, 617-622 第21回 回路とシステム軽井沢ワークショップ, 617-622 , 617-622 2008/04 Refereed Japanese Disclose to all
奥村 隆昌, 黒川 敦, 増田 弘生, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任 奥村 隆昌, 黒川 敦, 増田 弘生, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案 第21回 回路とシステム軽井沢ワークショップ, 299-304 第21回 回路とシステム軽井沢ワークショップ, 299-304 , 299-304 2008/04 Refereed Japanese Disclose to all
Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for in-Site Soc Power Integrity Verification Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for in-Site Soc Power Integrity Verification Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for in-Site Soc Power Integrity Verification Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108 Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108 Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108 2008 Disclose to all
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, pp. 107-108, 7-8 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, pp. 107-108, 7-8 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, pp. 107-108, 7-8 2008 English Disclose to all
Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, 10, 868-872 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, 10, 868-872 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, 10, 868-872 2007/10 English Disclose to all
中林 太美世, 黒川 敦, 佐藤 高史, 橋本 昌宜, 増田 弘生 中林 太美世, 黒川 敦, 佐藤 高史, 橋本 昌宜, 増田 弘生 45-65nm ノードにおける遅延ばらつき特性の環境温度依存性 45-65nm ノードにおける遅延ばらつき特性の環境温度依存性 第20回 回路とシステム軽井沢ワークショップ, 691-696 第20回 回路とシステム軽井沢ワークショップ, 691-696 , 691-696 2007/04 Refereed Japanese Disclose to all
高藤 浩資, 小林 宏行, 小野 信任, 増田 弘生, 中島 英斉, 奥村 隆昌, 橋本 昌宜, 佐藤 高史 高藤 浩資, 小林 宏行, 小野 信任, 増田 弘生, 中島 英斉, 奥村 隆昌, 橋本 昌宜, 佐藤 高史 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案 第20回 回路とシステム軽井沢ワークショップ, 709-714 第20回 回路とシステム軽井沢ワークショップ, 709-714 , 709-714 2007/04 Refereed Japanese Disclose to all
小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄 小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄 電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現 電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現 信学技報, ICD2006-174, 19-23 信学技報, ICD2006-174, 19-23 , ICD2006-174, 19-23 2007/01 Japanese Disclose to all
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872 IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872 , vol. 54, no. 10, pp. 868-872 2007 Disclose to all
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation IEEE Custom Integrated Circuits Conference (CICC), 861-864 IEEE Custom Integrated Circuits Conference (CICC), 861-864 IEEE Custom Integrated Circuits Conference (CICC), 861-864 2006/09 Refereed English Disclose to all
小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜 小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜 統計的 STA の精度検証手法 統計的 STA の精度検証手法 DA シンポジウム, 7-12 DA シンポジウム, 7-12 , 7-12 2006/07 Japanese Disclose to all
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction International Workshop on Compact Modeling, pp.51-56 International Workshop on Compact Modeling, pp.51-56 International Workshop on Compact Modeling, pp.51-56 2006 Disclose to all
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 2006 Disclose to all
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 2006 Disclose to all
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction International Workshop on Compact Modeling, pp.51-56 International Workshop on Compact Modeling, pp.51-56 , pp.51-56 2006 Disclose to all
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 , pp.59-64 2006 Disclose to all
画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 電子情報通信学会 VLSI設計技術研究会 電子情報通信学会 VLSI設計技術研究会 2006 Disclose to all
ロードマップに準拠したSPICEトランジスタモデルの構築 ロードマップに準拠したSPICEトランジスタモデルの構築 2006年電子情報通信学会総合大会講演論文集 2006年電子情報通信学会総合大会講演論文集 2006 Disclose to all
電源ノイズ解析のための回路動作部表現法の評価 電源ノイズ解析のための回路動作部表現法の評価 2006年電子情報通信学会総合大会講演論文集 2006年電子情報通信学会総合大会講演論文集 2006 Disclose to all
統計的STAの有効性の検証手法 統計的STAの有効性の検証手法 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction International Workshop on Compact Modeling, pp.51-56 International Workshop on Compact Modeling, pp.51-56 , pp.51-56 2006 Disclose to all
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.59-64 , pp.59-64 2006 Disclose to all
画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術 電子情報通信学会 VLSI設計技術研究会 電子情報通信学会 VLSI設計技術研究会 2006 Disclose to all
ロードマップに準拠したSPICEトランジスタモデルの構築 ロードマップに準拠したSPICEトランジスタモデルの構築 2006年電子情報通信学会総合大会講演論文集 2006年電子情報通信学会総合大会講演論文集 2006 Disclose to all
統計的STAの有効性の検証手法 統計的STAの有効性の検証手法 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測 第19回 回路とシステム(軽井沢)ワークショップ 第19回 回路とシステム(軽井沢)ワークショップ 2006 Disclose to all
S. Uemura, M. Hashimoto, H. Onodera 上村 晋一朗, 橋本昌宜, 小野寺秀俊 S. Uemura, M. Hashimoto, H. Onodera Estimation for Equivalent Parallel Resistance of LC Oscillators Including Resitance Components of MOSFETs LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり Estimation for Equivalent Parallel Resistance of LC Oscillators Including Resitance Components of MOSFETs IEICE Society Conference, C-12-39, 119-119 電子情報通信学会ソサイエティ大会, C-12-39, 119-119 IEICE Society Conference, C-12-39, 119-119 2005/09/21 Japanese Research paper, summary (national conference and other science council) Disclose to all
土谷亮, 橋本昌宜, 小野寺秀俊 土谷亮, 橋本昌宜, 小野寺秀俊 オンチップ伝送線路の基板損失に対する下層配線の影響 オンチップ伝送線路の基板損失に対する下層配線の影響 2005年電子情報通信学会総合大会, 77-77 2005年電子情報通信学会総合大会, 77-77 , 77-77 2005/03/24 Japanese Research paper, summary (national conference and other science council) Disclose to all
T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 723-728 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 723-728 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 723-728 2005/01 Refereed English Disclose to all
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1074-1077 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1074-1077 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1074-1077 2005/01 Refereed English Disclose to all
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera Timing Analysis Considering Temporal Supply Voltage Fluctuation Timing Analysis Considering Temporal Supply Voltage Fluctuation Timing Analysis Considering Temporal Supply Voltage Fluctuation ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1098-1101 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1098-1101 ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 1098-1101 2005/01 Refereed English Disclose to all
Measurement and analysis of delay variation due to inductive coupling Measurement and analysis of delay variation due to inductive coupling Proc. IEEE Custom Integrated Circuits Conference, 305-308 Proc. IEEE Custom Integrated Circuits Conference, 305-308 , 305-308 2005 Disclose to all
CMLを用いたオンチップ長距離高速信号伝送技術の開発 CMLを用いたオンチップ長距離高速信号伝送技術の開発 第9回システムLSIワークショップ 第9回システムLSIワークショップ 2005 Disclose to all
Measurement and analysis of delay variation due to inductive coupling Measurement and analysis of delay variation due to inductive coupling Proc. IEEE Custom Integrated Circuits Conference, 305-308 Proc. IEEE Custom Integrated Circuits Conference, 305-308 , 305-308 2005 Disclose to all
CMLを用いたオンチップ長距離高速信号伝送技術の開発 CMLを用いたオンチップ長距離高速信号伝送技術の開発 第9回システムLSIワークショップ 第9回システムLSIワークショップ 2005 Disclose to all
T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera T. Sato, M. Hashimoto, H. Onodera An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), 66-72 The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), 66-72 The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), 66-72 2004/10 Refereed English Disclose to all
橋本昌宜, 小野寺秀俊 橋本昌宜, 小野寺秀俊 微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応-- 微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応-- 2004年電子情報通信学会ソサイエティ大会講演論文集, 予稿なし 2004年電子情報通信学会ソサイエティ大会講演論文集, 予稿なし , 予稿なし 2004/09/23 Japanese Research paper, summary (national conference and other science council) Disclose to all
Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Trans. on CAD IEEE Trans. on CAD IEEE Trans. on CAD 2004 Disclose to all
Design and Optimization of CMOS Current Mode Logic Dividers Design and Optimization of CMOS Current Mode Logic Dividers Design and Optimization of CMOS Current Mode Logic Dividers Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004 Disclose to all
Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference 2004 Disclose to all
Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Trans. on CAD IEEE Trans. on CAD IEEE Trans. on CAD 2004 Disclose to all
Design and Optimization of CMOS Current Mode Logic Dividers Design and Optimization of CMOS Current Mode Logic Dividers Design and Optimization of CMOS Current Mode Logic Dividers Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004 Disclose to all
Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference 2004 Disclose to all
オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- 2004 Disclose to all
Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Trans. on CAD IEEE Trans. on CAD 2004 Disclose to all
配線RL抽出におけるリターンパス選択手法 配線RL抽出におけるリターンパス選択手法 2004 Disclose to all
遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 2004 Disclose to all
フロアプランにおけるオンチップ熱ばらつきの解析と対策 フロアプランにおけるオンチップ熱ばらつきの解析と対策 2004 Disclose to all
オンチップインダクタンスを考慮したLSI電源配線網解析 オンチップインダクタンスを考慮したLSI電源配線網解析 2004 Disclose to all
A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 2004 English Disclose to all
A Tsuchiya, Y Gotoh, M Hashimoto, H Onodera A Tsuchiya, Y Gotoh, M Hashimoto, H Onodera A Tsuchiya, Y Gotoh, M Hashimoto, H Onodera Performance limitation of on-chip global interconnects for high-speed signaling Performance limitation of on-chip global interconnects for high-speed signaling Performance limitation of on-chip global interconnects for high-speed signaling PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 489-492 PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 489-492 PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 489-492 2004 English Disclose to all
オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 --- 2004 Disclose to all
Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Trans. on CAD IEEE Trans. on CAD 2004 Disclose to all
配線RL抽出におけるリターンパス選択手法 配線RL抽出におけるリターンパス選択手法 2004 Disclose to all
遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価 2004 Disclose to all
フロアプランにおけるオンチップ熱ばらつきの解析と対策 フロアプランにおけるオンチップ熱ばらつきの解析と対策 2004 Disclose to all
オンチップインダクタンスを考慮したLSI電源配線網解析 オンチップインダクタンスを考慮したLSI電源配線網解析 2004 Disclose to all
A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera A Shinmyo, M Hashimoto, H Onodera Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 434-435 2004 English Disclose to all
Performance Limitation of On-chip Global Interconnects for High-speed Signaling Performance Limitation of On-chip Global Interconnects for High-speed Signaling Proc. IEEE Custom Integrated Circuits Conference Proc. IEEE Custom Integrated Circuits Conference 2004 Disclose to all
Masanori HASHIMOTO, Hidetoshi ONODERA 橋本昌宜, 小野寺秀俊 Masanori HASHIMOTO, Hidetoshi ONODERA A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits パスバランス回路における遅延不確かさの統計的解析 A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000/10/01 Japanese Research paper, summary (national conference and other science council) Disclose to all

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Title language:
Books etc
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Publisher Publisher(Japanese) Publisher(English) Publication date Language Type Disclose
T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao Book chapter, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design, VLSI Design and Test for Systems Dependability Book chapter, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M, Hashimoto,T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, M. Sugihara E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M, Hashimoto,T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, M. Sugihara Book chapter, Radiation-Induced Soft Errors, VLSI Design and Test for Systems Dependability Book chapter, Radiation-Induced Soft Errors, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao Book chapter, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design, VLSI Design and Test for Systems Dependability Book chapter, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M, Hashimoto,T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, M. Sugihara E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M, Hashimoto,T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, M. Sugihara Book chapter, Radiation-Induced Soft Errors, VLSI Design and Test for Systems Dependability Book chapter, Radiation-Induced Soft Errors, VLSI Design and Test for Systems Dependability Springer Springer 2018/08 Joint Work Disclose to all
Title language:
External funds: competitive funds and Grants-in-Aid for Scientific Research (Kakenhi)
Type Position Title(Japanese) Title(English) Period
基盤(S) Representative ミューオン起因ソフトエラー評価基盤技術: 実測とシミュレーションに基づく将来予測 Muon-induced soft error evaluation platform: future prediction based on measurement and simulation 2019/06/26-2024/03/31
基盤(B) Assignment 近似コンピューティングを活用した深層ニューラルネットワークアクセラレータの開発 Development of Deep Neural Network Accelerator Utilizing Approximate Computing 2019/04/01-2022/03/31
External funds: other than those above
System Main person Title(Japanese) Title(English) Period
CREST 本間尚文 耐量子計算機性秘匿計算に基づくセキュア情報処理基盤 2019/10/01-2025/03/31
CREST 鈴木秀幸 光ニューラルネットワークの時空間ダイナミクスに基づく計算基盤技術 2019/04/01-2024/03/31
OPERA 中野貴志 安全・安心・スマートな長寿社会実現のための高度な量子アプリケーション技術の創出 2017/10/01-2022/03/31
Teaching subject(s)
Name(Japanese) Name(English) Term Department Period
エレクトロニクス入門(機宇)〈情報〉 Introduction to Electronics 前期 工学部 2021/04-2022/03
ディジタル回路 Digital Circuits 前期 工学部 2021/04-2022/03
論理回路 Logic Circuits 前期 工学部 2021/04-2022/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2021/04-2022/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2021/04-2022/03
Faculty management (title, position)
Title Period
教務委員会委員 2021/04/01-2022/03/31