髙木 直史

Last Update: 2021/06/30 17:54:40

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Name(Kanji/Kana/Abecedarium Latinum)
髙木 直史/タカギ ナオフミ/Takagi, Naofumi
Primary Affiliation(Org1/Job title)
Graduate School of Informatics/Professor
Faculty
Org1 Job title
工学部
Contact Address
Type Address(Japanese) Address(English)
Office 京都市左京区吉田本町 京都大学総合研究7号館 330号室 Room 330, Research Bld. #7, Yoshida-honmachi, Sakyo-ku, Kyoto
Phone
Type Number
Office 075-753-5373
E-mail Address
E-mail address
takagi @ i.kyoto-u.ac.jp
Academic Organizations You are Affiliated to in Japan
Organization name(Japanese) Organization name(English)
電子情報通信学会 The Institute of Electronics, Information and Communication Engineers
情報処理学会 Information Processing Society of Japan
Academic Organizations Overaseas You are Affiliated to
Organization name Country
The Institute of Electrical and Electronics Engineers アメリカ合衆国
Academic Degree
Field(Japanese) Field(English) University(Japanese) University(English) Method
工学修士 京都大学
工学博士 京都大学
Academic Resume (Graduate Schools)
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(Japanese) Major(English) Completion Status
京都大学 大学院工学研究科修士課程情報工学専攻 修了
Academic Resume (Undergraduate School/Majors)
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(s)(Japanese) Major(s)(English) Completion Status
京都大学 工学部情報工学科 卒業
High School
Highschool Kana
大阪府立 北野高等学校 おおさかふりつ きたのこうとうがっこう
Work Experience
Period Organization(Japanese) Organization(English) Job title(Japanese) Job title(English)
1984/04/01-1991/03/31 京都大学 Kyoto University 助手 Assistant Professor
1991/04/01-1994/05/31 京都大学 Kyoto University 助教授 Assosiate Professor
1994/06/01-1998/05/15 名古屋大学 Nagoya University 助教授 Associate Professor
1998/05/16-2010/03/31 名古屋大学 Nagoya University 教授 Professor
2010/04/01- 京都大学 Kyoto University 教授 Professor
Personal Profile
(Japanese)
1983年京都大学大学院工学研究科修士課程修了。工学博士。京都大学助教授、名古屋大学教授を経て、2010年より京都大学大学院情報学研究科(通信情報システム専攻)教授。専門は情報工学の基礎。主に、算術演算回路、ハードウェアアルゴリズム、論理設計の研究に従事。著書として「論理回路」(昭晃堂、1995年)、「算術演算のVLSIアルゴリズム](コロナ社、2005年)等。日本IBM科学賞、科学技術分野の文部科学大臣表彰等を受賞。IEEE、電子情報通信学会、情報処理学会等各会員。
(English)
Naofumi Takagi received the BE, ME, and PhD degrees in information science from Kyoto University in 1981, 1983, and 1988, respectively. He was an associate professor at Kyoto University, was a professor at Nagoya University, and returned to Kyoto University in 2010 where he is a professor at Graduate School of Informatics. His current interests include computer arithmetic, hardware algorithms, and logic design. He received Japan IBM Science Award in 1995 and The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology of Japan in 2005. He is a senior member of IEEE and IEICE..
Language of Instruction
Language(japanese) Language(english) Code
英語 English eng
Personal Website(s) (URL(s))
URL
http://www.lab3.kuis.kyoto-u.ac.jp/~ntakagi/ntakagi.html
researchmap URL
https://researchmap.jp/read0012915
Research Topics
(Japanese)
並列計算機構,算術演算回路,ハードウェアアルゴリズム
(English)
Parallel computing architecture, arithmetic circuits, hardware algorithms
Fields of research (key words)
Key words(Japanese) Key words(English)
情報学 Informatics
計算機科学 Computer Science
Published Papers
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates IEEE Transactions on Applied Superconductivity, 31, 4, 1-7 IEEE Transactions on Applied Superconductivity, 31, 4, 1-7 IEEE Transactions on Applied Superconductivity, 31, 4, 1-7 2021/06 Refereed English Research paper(scientific journal) Disclose to all
Takashi Dejima, Kazuyoshi Takagi, Naofumi Takagi Takashi Dejima, Kazuyoshi Takagi, Naofumi Takagi Takashi Dejima, Kazuyoshi Takagi, Naofumi Takagi A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 2020/10 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 IEEE Transactions on Applied Superconductivity, 30, 7, 1-6 2020/10 Refereed English Research paper(scientific journal) Disclose to all
K Kitamura, K Takagi, N Takagi K Kitamura, K Takagi, N Takagi K Kitamura, K Takagi, N Takagi A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits Journal of Physics: Conference Series, 1590, 012043-012043 Journal of Physics: Conference Series, 1590, 012043-012043 Journal of Physics: Conference Series, 1590, 012043-012043 2020/07 Refereed English Research paper(scientific journal) Disclose to all
Hiroi Imanishi, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Hiroi Imanishi, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Hiroi Imanishi, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Supporting TOPPERS/ASP3 Kernel to mROS to improve its capability Supporting TOPPERS/ASP3 Kernel to mROS to improve its capability Supporting TOPPERS/ASP3 Kernel to mROS to improve its capability Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) 2019/11 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetosh Yugen, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Hidetosh Yugen, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Hidetosh Yugen, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi A functionality expansion of the lightweight runtime environment mROS for user defined message types A functionality expansion of the lightweight runtime environment mROS for user defined message types A functionality expansion of the lightweight runtime environment mROS for user defined message types Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019) 2019/11 Refereed English Research paper(international conference proceedings) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses IPSJ Transactions on System LSI Design Methodology, 12, 78-80 IPSJ Transactions on System LSI Design Methodology, 12, 78-80 IPSJ Transactions on System LSI Design Methodology, 12, 78-80 2019/08 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic ISEC 2019 - International Superconductive Electronics Conference ISEC 2019 - International Superconductive Electronics Conference ISEC 2019 - International Superconductive Electronics Conference 2019/07 Refereed Research paper(international conference proceedings) Disclose to all
KITO Nobutaka, TAKAGI Naofumi 鬼頭信貴, 高木直史 KITO Nobutaka, TAKAGI Naofumi Concurrent Error Detectable Carry Select Adder with Easy Testability Concurrent Error Detectable Carry Select Adder with Easy Testability Concurrent Error Detectable Carry Select Adder with Easy Testability IEEE Transactions on Computers, 68, 7, 1105-1110 IEEE Transactions on Computers, 68, 7, 1105-1110 IEEE Transactions on Computers, 68, 7, 1105-1110 2019/07 Refereed English Research paper(scientific journal) Disclose to all
KITAMURA Kei, TAKAGI Kazuyoshi, TAKAGI Naofumi 北村圭, 高木一義, 高木直史 KITAMURA Kei, TAKAGI Kazuyoshi, TAKAGI Naofumi A Global Routing Method with Wire Length Budgeting for SFQ Logic Cirduits A Global Routing Method with Wire Length Budgeting for SFQ Logic Cirduits A Global Routing Method with Wire Length Budgeting for SFQ Logic Cirduits 12th Superconducting SFQ VLSI Workshop (SSV 2019), 38-43 12th Superconducting SFQ VLSI Workshop (SSV 2019), 38-43 12th Superconducting SFQ VLSI Workshop (SSV 2019), 38-43 2019/01 English Disclose to all
DEJIMA Takashi, TAKAGI Kazuyoshi, TAKAGI Naofumi 出島貴史, 高木一義, 高木直史 DEJIMA Takashi, TAKAGI Kazuyoshi, TAKAGI Naofumi A Hierarchical Placement Method with Cell Clustering for Rapid-Single-Flux-Quantum Ciercuits A Hierarchical Placement Method with Cell Clustering for Rapid-Single-Flux-Quantum Ciercuits A Hierarchical Placement Method with Cell Clustering for Rapid-Single-Flux-Quantum Ciercuits 12th Superconducting SFQ VLSI Workshop (SSV 2019), 33-37 12th Superconducting SFQ VLSI Workshop (SSV 2019), 33-37 12th Superconducting SFQ VLSI Workshop (SSV 2019), 33-37 2019/01 English Disclose to all
KAWAGUCHI Takahiro, TAKAGI Kazuyoshi, TAKAGI Naofumi 川口隆広, 高木一義, 高木直史 KAWAGUCHI Takahiro, TAKAGI Kazuyoshi, TAKAGI Naofumi Encoder/Decoder for the Compound Signal of Data and Clock Encoder/Decoder for the Compound Signal of Data and Clock Encoder/Decoder for the Compound Signal of Data and Clock 12th Superconducting SFQ VLSI Workshop (SSV 2019), 125-128 12th Superconducting SFQ VLSI Workshop (SSV 2019), 125-128 12th Superconducting SFQ VLSI Workshop (SSV 2019), 125-128 2019/01 English Disclose to all
MATSUI Kentaro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi 松井健太郎, 高瀬英希, 高木一義, 高木直史 MATSUI Kentaro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi Core State Aware Slack Gathering Scheduling for Embedded Real-Time Systems Core State Aware Slack Gathering Scheduling for Embedded Real-Time Systems Core State Aware Slack Gathering Scheduling for Embedded Real-Time Systems Asia Pacific Conference on Robot IoT System Development and Platform 2018 Asia Pacific Conference on Robot IoT System Development and Platform 2018 Asia Pacific Conference on Robot IoT System Development and Platform 2018 2018/10 English Disclose to all
Yano Taiki, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi 矢野泰生, 高瀬英希, 高木一義, 高木直史 Yano Taiki, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi A motion planning method for mobile robot considering rotational motion in area coverage task A motion planning method for mobile robot considering rotational motion in area coverage task A motion planning method for mobile robot considering rotational motion in area coverage task Asia Pacific Conference on Robot IoT System Development and Platform 2018 Asia Pacific Conference on Robot IoT System Development and Platform 2018 Asia Pacific Conference on Robot IoT System Development and Platform 2018 2018/10 English Disclose to all
TAKASE Hideki, MORI Tomoya, TAKAGI Kazuyoshi, TAKAGI Naofumi 高瀬英希, 森智也, 高木一義, 高木直史 TAKASE Hideki, MORI Tomoya, TAKAGI Kazuyoshi, TAKAGI Naofumi Work-in-Progress: Design Concept of a Lightweight Runtime Environment for Robot Software Components onto Embedded Devices Work-in-Progress: Design Concept of a Lightweight Runtime Environment for Robot Software Components onto Embedded Devices Work-in-Progress: Design Concept of a Lightweight Runtime Environment for Robot Software Components onto Embedded Devices International Conference on Embedded Software 2018 International Conference on Embedded Software 2018 International Conference on Embedded Software 2018 2018/09 Refereed English Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching IEEE Transactions on Applied Superconductivity, 28, 4 IEEE Transactions on Applied Superconductivity, 28, 4 IEEE Transactions on Applied Superconductivity, 28, 4 2018/06/01 Refereed English Research paper(scientific journal) Disclose to all
HIROSE Hideki, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi 廣瀬秀樹, 高瀬英希, 高木一義, 高木直史 HIROSE Hideki, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR IPSJ ESW2017 Research Papers, 5-10 IPSJ ESW2017 Research Papers, 5-10 IPSJ ESW2017 Research Papers, 5-10 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi Algorithms for evaluating the matrix polynomial I + A + A2 + ⋯ + AN-1 with Reduced Number of Matrix Multiplications Algorithms for evaluating the matrix polynomial I + A + A2 + ⋯ + AN-1 with Reduced Number of Matrix Multiplications Algorithms for evaluating the matrix polynomial I + A + A2 + ⋯ + AN-1 with Reduced Number of Matrix Multiplications IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101A, 2, 467-471 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101A, 2, 467-471 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101A, 2, 467-471 2018/02/01 Refereed English Research paper(scientific journal) Disclose to all
Ryo Sato, Yuki Hatanaka, Yuki Ando, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Ryo Sato, Yuki Hatanaka, Yuki Ando, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Ryo Sato, Yuki Hatanaka, Yuki Ando, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 4, 1300505 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 4, 1300505 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 4, 1300505 2017/06 Refereed English Research paper(scientific journal) Disclose to all
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi 32 x 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors 32 x 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors 32 x 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 3, 1301005 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 3, 1301005 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 27, 3, 1301005 2017/04 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E100D, 3, 531-536 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E100D, 3, 531-536 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E100D, 3, 531-536 2017/03 Refereed English Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, TAKAGI Kazuyoshi, KITO Nobutaka 高木直史, 高木一義, 鬼頭信貴 TAKAGI Naofumi, TAKAGI Kazuyoshi, KITO Nobutaka Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors 10th Superconducting SFQ VLSI Workshop (SSV 2017), 30-33 10th Superconducting SFQ VLSI Workshop (SSV 2017), 30-33 10th Superconducting SFQ VLSI Workshop (SSV 2017), 30-33 2017/02 English Disclose to all
FUJIMAKI Akira, SATO Ryo, HATANAKA Yuki, AKAIKE Hiroyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi, TANAKA Masamitsu 藤巻朗, 佐藤諒, 畑中湧貴, 赤池宏之, 高木一義, 高木直史, 田中雅光 FUJIMAKI Akira, SATO Ryo, HATANAKA Yuki, AKAIKE Hiroyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi, TANAKA Masamitsu Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories 10th Superconducting SFQ VLSI Workshop (SSV 2017), 22-24 10th Superconducting SFQ VLSI Workshop (SSV 2017), 22-24 10th Superconducting SFQ VLSI Workshop (SSV 2017), 22-24 2017/02 English Disclose to all
KAWAGUCHI Takahiro, TAKAGI KAzuyoshi, TAKAGI Naofumi 川口隆弘, 高木一義, 高木直史 KAWAGUCHI Takahiro, TAKAGI KAzuyoshi, TAKAGI Naofumi Static timing analysis of rapid single-flux-quantum circuits Static timing analysis of rapid single-flux-quantum circuits Static timing analysis of rapid single-flux-quantum circuits The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), 341-345 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), 341-345 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), 341-345 2016/10 Refereed English Disclose to all
KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi 鬼頭信貴, 高木一義, 高木直史 KITO Nobutaka, TAKAGI Kazuyoshi, TAKAGI Naofumi Fast length-matching routing for rapid single flux quantum circuits Fast length-matching routing for rapid single flux quantum circuits Fast length-matching routing for rapid single flux quantum circuits The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), 135-149 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (SASIMI2016), 135-149 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), 135-149 2016/10 Refereed English Disclose to all
KITO Nobutaka, MATSUMOTO Gentoku, TAKAGI Kazuyoshi, TAKAGI Naofumi 鬼頭信貴, 松本弦篤, 高木一義, 高木直史 KITO Nobutaka, MATSUMOTO Gentoku, TAKAGI Kazuyoshi, TAKAGI Naofumi Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits 9th Superconducting SFQ VLSI Workshop (SSV 2016), 86-89 9th Superconducting SFQ VLSI Workshop (SSV 2016), 86-89 9th Superconducting SFQ VLSI Workshop (SSV 2016), 86-89 2016/08 English Disclose to all
Tang Guanming, TAKAGI Kazuyoshi, TAKAGI Naofumi 唐光明, 高木一義, 高木直史 Tang Guanming, TAKAGI Kazuyoshi, TAKAGI Naofumi A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor 9th Superconducting SFQ VLSI Workshop (SSV 2016), 31-35 9th Superconducting SFQ VLSI Workshop (SSV 2016), 31-35 9th Superconducting SFQ VLSI Workshop (SSV 2016), 31-35 2016/08 English Disclose to all
SATO Ryo, TANAKA Masamitsu, HATANAKA Yuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, TAKAGI Kazuyoshi 佐藤諒, 田中雅光, 畑中湧貴, 藤巻朗, 赤池宏之, 高木直史, 高木一義 SATO Ryo, TANAKA Masamitsu, HATANAKA Yuki, FUJIMAKI Akira, AKAIKE Hiroyuki, TAKAGI Naofumi, TAKAGI Kazuyoshi Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs 9th Superconducting SFQ VLSI Workshop (SSV 2016), 26-30 9th Superconducting SFQ VLSI Workshop (SSV 2016), 26-30 9th Superconducting SFQ VLSI Workshop (SSV 2016), 26-30 2016/08 English Disclose to all
Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 5, 1301205 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 5, 1301205 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 5, 1301205 2016/08 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 703-709 IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 703-709 IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 703-709 2016/06 Refereed English Research paper(scientific journal) Disclose to all
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi RSFQ 4-bit Bit-Slice Integer Multiplier RSFQ 4-bit Bit-Slice Integer Multiplier RSFQ 4-bit Bit-Slice Integer Multiplier IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 697-702 IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 697-702 IEICE TRANSACTIONS ON ELECTRONICS, E99C, 6, 697-702 2016/06 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 3, 1300305 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 3, 1300305 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 3, 1300305 2016/04 Refereed English Research paper(scientific journal) Disclose to all
Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi An Evaluation Framework of OS-Level Power Managements for the big. LITTLE Architecture An Evaluation Framework of OS-Level Power Managements for the big. LITTLE Architecture An Evaluation Framework of OS-Level Power Managements for the big. LITTLE Architecture 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) 2016 Refereed English Research paper(international conference proceedings) Disclose to all
Guang-Ming Tang, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi 4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors 4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors 4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 1, 1300106 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 1, 1300106 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 26, 1, 1300106 2016/01 Refereed English Research paper(scientific journal) Disclose to all
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2556-2564 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2556-2564 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A, 12, 2556-2564 2015/12 Refereed English Research paper(scientific journal) Disclose to all
OHATA Masaya, UEDA Keita, TAKAGI Kazuyoshi, TAKAGI Naofumi 大畑真也, 植田慶太, 高木一義, 高木直史 OHATA Masaya, UEDA Keita, TAKAGI Kazuyoshi, TAKAGI Naofumi Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits 8th Superconducting SFQ VLSI Workshop (SSV 2015), 140-143 8th Superconducting SFQ VLSI Workshop (SSV 2015), 140-143 8th Superconducting SFQ VLSI Workshop (SSV 2015), 140-143 2015/07 English Disclose to all
Xizhu Peng, Qiuyun Xu, Faichi Kato, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka Xizhu Peng, Qiuyun Xu, Faichi Kato, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka Xizhu Peng, Qiuyun Xu, Faichi Kato, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1301106 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1301106 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1301106 2015/06 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1300905 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1300905 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 25, 3, 1300905 2015/06 Refereed English Research paper(scientific journal) Disclose to all
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi An allocation optimization method for partially-reliable scratch-pad memory in embedded systems An allocation optimization method for partially-reliable scratch-pad memory in embedded systems An allocation optimization method for partially-reliable scratch-pad memory in embedded systems IPSJ Transactions on System LSI Design Methodology, 8, 100-104 IPSJ Transactions on System LSI Design Methodology, 8, 100-104 IPSJ Transactions on System LSI Design Methodology, 8, 100-104 2015/02/01 Refereed English Research paper(scientific journal) Disclose to all
Ryo Sato, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi Ryo Sato, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi Ryo Sato, Kensuke Takata, Masamitsu Tanaka, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Masamitsu Tanaka, Kensuke Takata, Ryo Sato, Akira Fujimaki, Takahiro Kawaguchi, Yuki Ando, Kazuyoshi Takagi, Naofumi Takagi, Nobuyuki Yoshikawa Masamitsu Tanaka, Kensuke Takata, Ryo Sato, Akira Fujimaki, Takahiro Kawaguchi, Yuki Ando, Kazuyoshi Takagi, Naofumi Takagi, Nobuyuki Yoshikawa Masamitsu Tanaka, Kensuke Takata, Ryo Sato, Akira Fujimaki, Takahiro Kawaguchi, Yuki Ando, Kazuyoshi Takagi, Naofumi Takagi, Nobuyuki Yoshikawa Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Takahiro Kawaguchi, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Takahiro Kawaguchi, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Demonstration of an 8-bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells Demonstration of an 8-bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells Demonstration of an 8-bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocessor A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocessor A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocessor 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi 80-GHz Operation of an 8-bit RSFQ Arithmetic Logic Unit 80-GHz Operation of an 8-bit RSFQ Arithmetic Logic Unit 80-GHz Operation of an 8-bit RSFQ Arithmetic Logic Unit 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2015 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi PTL Routing Environment for SFQ Circuits Using a Commercial Router PTL Routing Environment for SFQ Circuits Using a Commercial Router PTL Routing Environment for SFQ Circuits Using a Commercial Router 7th Superconducting SFQ VLSI Workshop (SSV 2014), 143-146 7th Superconducting SFQ VLSI Workshop (SSV 2014), 143-146 7th Superconducting SFQ VLSI Workshop (SSV 2014), 143-146 2014/12 English Disclose to all
Y. Ando, M. Tanaka, K. Takagi, N. Takagi Y. Ando, M. Tanaka, K. Takagi, N. Takagi Y. Ando, M. Tanaka, K. Takagi, N. Takagi Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers 7th Superconducting SFQ VLSI Workshop (SSV 2014), 111-115 7th Superconducting SFQ VLSI Workshop (SSV 2014), 111-115 7th Superconducting SFQ VLSI Workshop (SSV 2014), 111-115 2014/12 English Disclose to all
R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi Design of Shift-Register Memories for SFQ Micro Processors COREe Design of Shift-Register Memories for SFQ Micro Processors COREe Design of Shift-Register Memories for SFQ Micro Processors COREe 7th Superconducting SFQ VLSI Workshop (SSV 2014), 105-107 7th Superconducting SFQ VLSI Workshop (SSV 2014), 105-107 7th Superconducting SFQ VLSI Workshop (SSV 2014), 105-107 2014/12 English Disclose to all
R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi R. Sato, K. Takata, M. Tanaka, A. Fujimaki, K. Takagi, N. Takagi Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3 7th Superconducting SFQ VLSI Workshop (SSV 2014), 90-93 7th Superconducting SFQ VLSI Workshop (SSV 2014), 90-93 7th Superconducting SFQ VLSI Workshop (SSV 2014), 90-93 2014/12 English Disclose to all
K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi K. Takata, M. Tanaka, A. Fujimaki, G. Tang, K. Takagi, N. Takagi Demonstration of 4-Bit-Parallel Bit-Slice ALU Demonstration of 4-Bit-Parallel Bit-Slice ALU Demonstration of 4-Bit-Parallel Bit-Slice ALU 7th Superconducting SFQ VLSI Workshop (SSV 2014), 84-89 7th Superconducting SFQ VLSI Workshop (SSV 2014), 84-89 7th Superconducting SFQ VLSI Workshop (SSV 2014), 84-89 2014/12 English Disclose to all
M. Moriya, K. Takagi, N. Takagi M. Moriya, K. Takagi, N. Takagi M. Moriya, K. Takagi, N. Takagi Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates 7th Superconducting SFQ VLSI Workshop (SSV 2014), 67-71 7th Superconducting SFQ VLSI Workshop (SSV 2014), 67-71 7th Superconducting SFQ VLSI Workshop (SSV 2014), 67-71 2014/12 English Disclose to all
G. Tang, K. Takagi, N. Takagi G. Tang, K. Takagi, N. Takagi G. Tang, K. Takagi, N. Takagi Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors 7th Superconducting SFQ VLSI Workshop (SSV 2014), 39-44 7th Superconducting SFQ VLSI Workshop (SSV 2014), 39-44 7th Superconducting SFQ VLSI Workshop (SSV 2014), 39-44 2014/12 English Disclose to all
M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa M. Tanaka, K. Takata, R. Satoh, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing 7th Superconducting SFQ VLSI Workshop (SSV 2014), 2-7 7th Superconducting SFQ VLSI Workshop (SSV 2014), 2-7 7th Superconducting SFQ VLSI Workshop (SSV 2014), 2-7 2014/12 English Disclose to all
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2498-2506 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2498-2506 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A, 12, 2498-2506 2014/12 Refereed English Research paper(scientific journal) Disclose to all
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10 kA/cm(2) Nb Process Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10 kA/cm(2) Nb Process Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10 kA/cm(2) Nb Process IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 188-193 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 188-193 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 188-193 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 157-165 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 157-165 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 157-165 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Circuit Description and Design Flow of Superconducting SFQ Logic Circuits IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 149-156 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 149-156 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 149-156 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki Murakami Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki Murakami Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki Murakami A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 141-148 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 141-148 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 141-148 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 132-140 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 132-140 IEICE TRANSACTIONS ON ELECTRONICS, E97C, 3, 132-140 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality 2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS), 546-549 2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS), 546-549 2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS), 546-549 2014 Refereed English Research paper(international conference proceedings) Disclose to all
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 118-119 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 118-119 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 118-119 2014 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi A Design Framework for SFQ Circuits Using Clockless Gates A Design Framework for SFQ Circuits Using Clockless Gates A Design Framework for SFQ Circuits Using Clockless Gates 6th Superconducting SFQ VLSI Workshop (SSV 2013), 123-127 6th Superconducting SFQ VLSI Workshop (SSV 2013), 123-127 6th Superconducting SFQ VLSI Workshop (SSV 2013), 123-127 2013/11 English Disclose to all
Y. Ohmomo, K. Takagi, N. Takagi Y. Ohmomo, K. Takagi, N. Takagi Y. Ohmomo, K. Takagi, N. Takagi Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors 6th Superconducting SFQ VLSI Workshop (SSV 2013), 117-122 6th Superconducting SFQ VLSI Workshop (SSV 2013), 117-122 6th Superconducting SFQ VLSI Workshop (SSV 2013), 117-122 2013/11 English Disclose to all
M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki, Y. Ohmomo, T. Kawaguchi, K. Takagi, N. Takagi Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors 6th Superconducting SFQ VLSI Workshop (SSV 2013), 19-22 6th Superconducting SFQ VLSI Workshop (SSV 2013), 19-22 6th Superconducting SFQ VLSI Workshop (SSV 2013), 19-22 2013/11 English Disclose to all
N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi Retiming of SFQ Logic Circuits for Reduction of Flip-Flops Retiming of SFQ Logic Circuits for Reduction of Flip-Flops Retiming of SFQ Logic Circuits for Reduction of Flip-Flops 6th Superconducting SFQ VLSI Workshop (SSV 2013), 13-18 6th Superconducting SFQ VLSI Workshop (SSV 2013), 13-18 6th Superconducting SFQ VLSI Workshop (SSV 2013), 13-18 2013/11 English Disclose to all
SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi SUDA Akihiro, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 322-327 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 322-327 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 322-327 2013/10 Refereed English Disclose to all
KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi KITO Nobuyuki, TAKAGI Kazuyoshi, TAKAGI Naofumi Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 220-225 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 220-225 Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), 220-225 2013/10 Refereed English Disclose to all
Nobutaka Kito, Naofumi Takagi Nobutaka Kito, Naofumi Takagi Nobutaka Kito, Naofumi Takagi Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 9, 1962-1970 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 9, 1962-1970 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D, 9, 1962-1970 2013/09 Refereed English Research paper(scientific journal) Disclose to all
Naofumi Takagi Naofumi Takagi Naofumi Takagi An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 484, 213-216 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 484, 213-216 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 484, 213-216 2013/01 Refereed English Research paper(scientific journal) Disclose to all
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 8285, 1, 390-401 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 8285, 1, 390-401 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 8285, 1, 390-401 2013 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa 60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm(2) Nb Process 60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm(2) Nb Process 60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm(2) Nb Process 2013 IEEE 14TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2013 IEEE 14TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2013 IEEE 14TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2013 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Hayakawa, K. Takata, M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Y. Hayakawa, K. Takata, M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Y. Hayakawa, K. Takata, M. Okada, A. Fujimaki, M. Tanaka, H. Akaike, N. Yoshikawa, S. Nagasawa, N. Takagi Low Frequency Test of 4x4 Reconfigurable Data-Path Processors Low Frequency Test of 4x4 Reconfigurable Data-Path Processors Low Frequency Test of 4x4 Reconfigurable Data-Path Processors 5th Superconducting SFQ VLSI Workshop (SSV 2012), 162-165 5th Superconducting SFQ VLSI Workshop (SSV 2012), 162-165 5th Superconducting SFQ VLSI Workshop (SSV 2012), 162-165 2012/12 English Disclose to all
X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process 5th Superconducting SFQ VLSI Workshop (SSV 2012), 152-154 5th Superconducting SFQ VLSI Workshop (SSV 2012), 152-154 5th Superconducting SFQ VLSI Workshop (SSV 2012), 152-154 2012/12 English Disclose to all
M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation 5th Superconducting SFQ VLSI Workshop (SSV 2012), 118-121 5th Superconducting SFQ VLSI Workshop (SSV 2012), 118-121 5th Superconducting SFQ VLSI Workshop (SSV 2012), 118-121 2012/12 English Disclose to all
T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa T. Kato, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process 5th Superconducting SFQ VLSI Workshop (SSV 2012), 45-47 5th Superconducting SFQ VLSI Workshop (SSV 2012), 45-47 5th Superconducting SFQ VLSI Workshop (SSV 2012), 45-47 2012/12 English Disclose to all
T. Kawaguchi, k. Takagi, N. Takagi T. Kawaguchi, k. Takagi, N. Takagi T. Kawaguchi, k. Takagi, N. Takagi A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits 5th Superconducting SFQ VLSI Workshop (SSV 2012), 33-36 5th Superconducting SFQ VLSI Workshop (SSV 2012), 33-36 5th Superconducting SFQ VLSI Workshop (SSV 2012), 33-36 2012/12 English Disclose to all
K. Kobayashi, N. Takagi, K. Takagi K. Kobayashi, N. Takagi, K. Takagi K. Kobayashi, N. Takagi, K. Takagi Fast inversion algorithm in GF(2(m)) suitable for implementation with a polynomial multiply instruction on GF(2) Fast inversion algorithm in GF(2(m)) suitable for implementation with a polynomial multiply instruction on GF(2) Fast inversion algorithm in GF(2(m)) suitable for implementation with a polynomial multiply instruction on GF(2) IET COMPUTERS AND DIGITAL TECHNIQUES, 6, 3, 180-185 IET COMPUTERS AND DIGITAL TECHNIQUES, 6, 3, 180-185 IET COMPUTERS AND DIGITAL TECHNIQUES, 6, 3, 180-185 2012/05 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Shinichi Fujii, Naofumi Takagi Nobutaka Kito, Shinichi Fujii, Naofumi Takagi Nobutaka Kito, Shinichi Fujii, Naofumi Takagi A C-Testable Multiple-Block Carry Select Adder A C-Testable Multiple-Block Carry Select Adder A C-Testable Multiple-Block Carry Select Adder IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D, 4, 1084-1092 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D, 4, 1084-1092 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D, 4, 1084-1092 2012/04 Refereed English Research paper(scientific journal) Disclose to all
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition IEICE TRANSACTIONS ON ELECTRONICS, E95C, 4, 456-467 IEICE TRANSACTIONS ON ELECTRONICS, E95C, 4, 456-467 IEICE TRANSACTIONS ON ELECTRONICS, E95C, 4, 456-467 2012/04 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 319-324 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 319-324 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 319-324 2012/03 Refereed English Disclose to all
Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Kousuke Torii, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 106-110 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 106-110 Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), 106-110 2012/03 Refereed English Disclose to all
Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme SUPERCONDUCTIVITY CENTENNIAL CONFERENCE 2011, 36, 349-353 SUPERCONDUCTIVITY CENTENNIAL CONFERENCE 2011, 36, 349-353 SUPERCONDUCTIVITY CENTENNIAL CONFERENCE 2011, 36, 349-353 2012 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi T. Kawaguchi, K. Takagi, N. Takagi Design of SFQ Circuits Using Clockless Logic Gates Design of SFQ Circuits Using Clockless Logic Gates Design of SFQ Circuits Using Clockless Logic Gates 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 English Disclose to all
N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi N. Kito, K. Takagi, N. Takagi Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 English Disclose to all
K. Takagi, N. Takagi K. Takagi, N. Takagi K. Takagi, N. Takagi Design Algorithms for Superconducting SFQ Logic Circuits Design Algorithms for Superconducting SFQ Logic Circuits Design Algorithms for Superconducting SFQ Logic Circuits 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 4th Superconducting SFQ VLSI Workshop (SSV 2011) 2011/11 English Disclose to all
Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, Shuichi Nagasawa Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, Shuichi Nagasawa Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, Shuichi Nagasawa Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm(2) Nb Process Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm(2) Nb Process Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm(2) Nb Process IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 827-830 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 827-830 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 827-830 2011/06 Refereed English Research paper(scientific journal) Disclose to all
Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Shuichi Nagasawa, Naofumi Takagi Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Shuichi Nagasawa, Naofumi Takagi Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Shuichi Nagasawa, Naofumi Takagi Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 809-813 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 809-813 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 809-813 2011/06 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Yuki Yamanashi, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Yuki Yamanashi, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Yuki Yamanashi, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi 100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm(2) Niobium Process 100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm(2) Niobium Process 100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm(2) Niobium Process IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 792-796 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 792-796 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 21, 3, 792-796 2011/06 Refereed English Research paper(scientific journal) Disclose to all
Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits IEICE TRANSACTIONS ON ELECTRONICS, E94C, 3, 288-295 IEICE TRANSACTIONS ON ELECTRONICS, E94C, 3, 288-295 IEICE TRANSACTIONS ON ELECTRONICS, E94C, 3, 288-295 2011/03 Refereed English Research paper(scientific journal) Disclose to all
Hirotaka Kawashima, Naofumi Takagi Hirotaka Kawashima, Naofumi Takagi Hirotaka Kawashima, Naofumi Takagi Partial product generation utilizing the sum of operands for reduced area parallel multipliers Partial product generation utilizing the sum of operands for reduced area parallel multipliers Partial product generation utilizing the sum of operands for reduced area parallel multipliers IPSJ Transactions on System LSI Design Methodology, 4, 131-139 IPSJ Transactions on System LSI Design Methodology, 4, 131-139 IPSJ Transactions on System LSI Design Methodology, 4, 131-139 2011 Refereed English Research paper(scientific journal) Disclose to all
Nobutaka Kito, Kensuke Hanai, Naofumi Takagi Nobutaka Kito, Kensuke Hanai, Naofumi Takagi Nobutaka Kito, Kensuke Hanai, Naofumi Takagi A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 10, 2783-2791 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 10, 2783-2791 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 10, 2783-2791 2010/10 Refereed English Research paper(scientific journal) Disclose to all
Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Ryo Shimazaki, Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 42-47 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 42-47 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 42-47 2010/10 Refereed English Disclose to all
Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi Kazuyoshi Takagi, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 208-213 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 208-213 Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), 208-213 2010/10 Refereed English Disclose to all
Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka 100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm(2) Nb Multi-Layer Process 100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm(2) Nb Multi-Layer Process 100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm(2) Nb Multi-Layer Process IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 440-444 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 440-444 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 440-444 2010/04 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 435-439 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 435-439 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 435-439 2010/04 Refereed English Research paper(scientific journal) Disclose to all
Naofumi Takagi, Masamitsu Tanaka Naofumi Takagi, Masamitsu Tanaka Naofumi Takagi, Masamitsu Tanaka Comparisons of Synchronous-Clocking SFQ Adders Comparisons of Synchronous-Clocking SFQ Adders Comparisons of Synchronous-Clocking SFQ Adders IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 429-434 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 429-434 IEICE TRANSACTIONS ON ELECTRONICS, E93C, 4, 429-434 2010/04 Refereed English Research paper(scientific journal) Disclose to all
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 2, 300-305 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 2, 300-305 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D, 2, 300-305 2010/02 Refereed English Research paper(scientific journal) Disclose to all
M. Sato, M. Tanaka, K. Takagi, N. Takagi M. Sato, M. Tanaka, K. Takagi, N. Takagi M. Sato, M. Tanaka, K. Takagi, N. Takagi A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 81-85 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 81-85 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 81-85 2010/01 English Disclose to all
M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi M. Tanaka, K. Takagi, N. Takagi Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 53-54 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 53-54 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 53-54 2010/01 English Disclose to all
K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi K. Takagi, S. Takeshima, M. Sato, M. Tanaka, N. Takagi Timing Optimization Methods for Superconducting SFQ Circuits Timing Optimization Methods for Superconducting SFQ Circuits Timing Optimization Methods for Superconducting SFQ Circuits 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 21-24 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 21-24 3rd Superconducting SFQ VLSI Workshop (SSV 2010), 21-24 2010/01 English Disclose to all
N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi High-Speed Floating-Point Processors based on Single-Flux-Quantum Circuit Technology High-Speed Floating-Point Processors based on Single-Flux-Quantum Circuit Technology High-Speed Floating-Point Processors based on Single-Flux-Quantum Circuit Technology Asian Conference of Applied Superconductivity and Cryogenics (ACASC 2009) Asian Conference of Applied Superconductivity and Cryogenics (ACASC 2009) Asian Conference of Applied Superconductivity and Cryogenics (ACASC 2009) 2009/12/07 Refereed English Research paper(other academic) Disclose to all
N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi, K. Takagi Component Design and Test of 50-GHz Half-Precision Floating-Point Adders and Multipliers Component Design and Test of 50-GHz Half-Precision Floating-Point Adders and Multipliers Component Design and Test of 50-GHz Half-Precision Floating-Point Adders and Multipliers EUROFLUX 2009 International Conference EUROFLUX 2009 International Conference EUROFLUX 2009 International Conference 2009/09/22 Refereed English Research paper(other academic) Disclose to all
N. Yoshikawa, H. Park, H. Hara, Y. Yamanashi, A. Fujimaki, K. Takagi, N. Takagi, M. Hidaka N. Yoshikawa, H. Park, H. Hara, Y. Yamanashi, A. Fujimaki, K. Takagi, N. Takagi, M. Hidaka N. Yoshikawa, H. Park, H. Hara, Y. Yamanashi, A. Fujimaki, K. Takagi, N. Takagi, M. Hidaka Recent Developments in Floating-Point Processors using Single-Flux-Quantum Circuits Recent Developments in Floating-Point Processors using Single-Flux-Quantum Circuits Recent Developments in Floating-Point Processors using Single-Flux-Quantum Circuits 9th European Conference on Applied Superconductivity (EUCAS 2009) 9th European Conference on Applied Superconductivity (EUCAS 2009) 9th European Conference on Applied Superconductivity (EUCAS 2009) 2009/09/15 Refereed English Research paper(other academic) Disclose to all
Katsuki Kobayashi, Naofumi Takagi Katsuki Kobayashi, Naofumi Takagi Katsuki Kobayashi, Naofumi Takagi Fast Hardware Algorithm for Division in GF(2(m)) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions Fast Hardware Algorithm for Division in GF(2(m)) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions Fast Hardware Algorithm for Division in GF(2(m)) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 56, 8, 644-648 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 56, 8, 644-648 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 56, 8, 644-648 2009/08 Refereed English Research paper(scientific journal) Disclose to all
S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa New Nb multi-layer fabrication process for large-scale SFQ circuits New Nb multi-layer fabrication process for large-scale SFQ circuits New Nb multi-layer fabrication process for large-scale SFQ circuits PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1578-1584 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1578-1584 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1578-1584 2009/08 Refereed English Research paper(scientific journal) Disclose to all
H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M. Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M. Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M. Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi Design of single flux quantum cells for a 10-Nb-layer process Design of single flux quantum cells for a 10-Nb-layer process Design of single flux quantum cells for a 10-Nb-layer process PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1670-1673 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1670-1673 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 469, 15-20, 1670-1673 2009/08 Refereed English Research paper(scientific journal) Disclose to all
KITO Nobutaka, TAKAGI Naofumi 鬼頭信貴, 高木直史 KITO Nobutaka, TAKAGI Naofumi Testability of Multipliers with a Partial Product Compressor Consisting of Carry Save Adders けた上げ保存加算器で構成された部分積加算部をもつ乗算器のテスト Testability of Multipliers with a Partial Product Compressor Consisting of Carry Save Adders Transactions of IEICE, J92-D, 7, 994-1002 電子情報通信学会論文誌, J92-D, 7, 994-1002 Transactions of IEICE, J92-D, 7, 994-1002 2009/07 Refereed Japanese Research paper(scientific journal) Disclose to all
I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi A Crossbar Switch for Routing of 2-bit Wide Data Streams A Crossbar Switch for Routing of 2-bit Wide Data Streams A Crossbar Switch for Routing of 2-bit Wide Data Streams Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) 2009/06/15 Refereed English Research paper(international conference proceedings) Disclose to all
M. Tanaka, K. Takagi, N. Takagi, Y. Yamanashi, N. Yoshikawa M. Tanaka, K. Takagi, N. Takagi, Y. Yamanashi, N. Yoshikawa M. Tanaka, K. Takagi, N. Takagi, Y. Yamanashi, N. Yoshikawa High-Throughput Arithmetic Circuits based on Systolic Architecture for SFQ Reconfigurable Data-Path High-Throughput Arithmetic Circuits based on Systolic Architecture for SFQ Reconfigurable Data-Path High-Throughput Arithmetic Circuits based on Systolic Architecture for SFQ Reconfigurable Data-Path Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009) 2009/06/15 Refereed English Research paper(international conference proceedings) Disclose to all
Kan Fujiwara, Shuichi Nagasawa, Yoshihito Hashimoto, Mutsuo Hidaka, Nobuyuki Yoshikawa, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Kan Fujiwara, Shuichi Nagasawa, Yoshihito Hashimoto, Mutsuo Hidaka, Nobuyuki Yoshikawa, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Kan Fujiwara, Shuichi Nagasawa, Yoshihito Hashimoto, Mutsuo Hidaka, Nobuyuki Yoshikawa, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Research on Effective Moat Configuration for Nb Multi-Layer Device Structure Research on Effective Moat Configuration for Nb Multi-Layer Device Structure Research on Effective Moat Configuration for Nb Multi-Layer Device Structure IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 603-606 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 603-606 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 603-606 2009/06 Refereed English Research paper(scientific journal) Disclose to all
Tetsuro Satoh, Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Tetsuro Satoh, Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Tetsuro Satoh, Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 167-170 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 167-170 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 167-170 2009/06 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki, Nobuyuki Yoshikawa Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki, Nobuyuki Yoshikawa Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi, Akira Fujimaki, Nobuyuki Yoshikawa A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 653-656 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 653-656 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 653-656 2009/06 Refereed English Research paper(scientific journal) Disclose to all
Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Koji Obata, Yuki Ito, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Shuichi Nagasawa Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Koji Obata, Yuki Ito, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Shuichi Nagasawa Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Koji Obata, Yuki Ito, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Shuichi Nagasawa Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 634-639 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 634-639 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 634-639 2009/06 Refereed English Research paper(scientific journal) Disclose to all
Hiroshi Hara, Koji Obata, Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki, N. Takagi, Kazuyoshi Takagi, S. Nagasawa Hiroshi Hara, Koji Obata, Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki, N. Takagi, Kazuyoshi Takagi, S. Nagasawa Hiroshi Hara, Koji Obata, Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki, N. Takagi, Kazuyoshi Takagi, S. Nagasawa Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 657-660 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 657-660 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 657-660 2009/06 Refereed English Research paper(scientific journal) Disclose to all
Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi, Koji Inoue, Hiroaki Honda, Kazuaki Murakami Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi, Koji Inoue, Hiroaki Honda, Kazuaki Murakami Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi, Koji Inoue, Hiroaki Honda, Kazuaki Murakami An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 665-669 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 665-669 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 19, 3, 665-669 2009/06 Refereed English Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi TAKAGI Naofumi, TANAKA Masamitsu, TAKAGI Kazuyoshi Hardware Algorithms for SFQ Arithmetic Circuits Hardware Algorithms for SFQ Arithmetic Circuits Hardware Algorithms for SFQ Arithmetic Circuits 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki FUJIMAKI Akira, KASAGI Ryo, TAKAGI Katsumi, KATAEVA Irina, AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Naofumi, YOSHIKAWA Nobuyuki, MURAKAMI Kazuaki Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki KATAEVA Irina, AKAIKE Hiroyuki, FUJIMAKI Akira, Yoshikawa Nobuyuki, TAKAGI Naofumi, MURAKAMI Kazuaki Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M, FUJIMAKI Akira, IGARASHI M, PARK H, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M, FUJIMAKI Akira, IGARASHI M, PARK H, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi AKAIKE Hiroyuki, TANAKA Masamitsu, TAKAGI Katsumi, KATAEVA Irina, KASAGI Ryo, Itoh M, FUJIMAKI Akira, IGARASHI M, PARK H, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, NAGASAWA Shuichi, HIDAKA Mutsuo, TAKAGI Kazuyoshi, TAKAGI Naofumi Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira TANAKA Masamitsu, OBATA Koji, ITO Yuki, TAKESHIMA Shota, SATO Motoki, TAKAGI Kazuyoshi, TAKAGI Naofumi, AKAIKE Hiroyuki, FUJIMAKI Akira An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki NAGASAWA Shuichi, SATOH Tetsuro, HINODE Kenji, KITAGAWA Yoshihiro, HIDAKA Mutsuo, AKAIKE Hiroyuki, FUJIMAKI Akira, TAKAGI Kazuyoshi, TAKAGI Naofumi, YOSHIKAWA Nobuyuki Nb Multi-Layer Device Fabrication Technology Nb Multi-Layer Device Fabrication Technology Nb Multi-Layer Device Fabrication Technology 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi KAINUMA Toshiki, PARK Heejoung, TAKETOMI Kazuhiro, HARA Hiroshi, YAMANASHI Yuki, YOSHIKAWA Nobuyuki, TANAKA Masamitsu, ITO Yuki, FUJIMAKI Akira, TAKAGI Naofumi, TAKAGI Kazuyoshi, NAGASAWA Shuichi Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm<sup>2</sup> Nb Process 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 12th International Superconductive Electronics Conference (ISEC 2009) 2009/06 Refereed English Research paper(scientific journal) Disclose to all
KAWASHIMA Hirotaka, TAKAGI Naofumi KAWASHIMA Hirotaka, TAKAGI Naofumi KAWASHIMA Hirotaka, TAKAGI Naofumi Small Area Multipliers Utilizing the Sum of Operands Small Area Multipliers Utilizing the Sum of Operands Small Area Multipliers Utilizing the Sum of Operands Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 189-194 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 189-194 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 189-194 2009/03 Refereed English Disclose to all
KOBAYASHI Katsuki, TAKAGI Naofumi KOBAYASHI Katsuki, TAKAGI Naofumi KOBAYASHI Katsuki, TAKAGI Naofumi Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Fast Division Circuit in GF(2<sup>m</sup>) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 94-99 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 94-99 Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), 94-99 2009/03 Refereed English Disclose to all
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3772-3782 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3772-3782 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E91A, 12, 3772-3782 2008/12 Refereed English Research paper(scientific journal) Disclose to all
Katsuki Kobayashi, Naofumi Takagi Katsuki Kobayashi, Naofumi Takagi Katsuki Kobayashi, Naofumi Takagi A Combined Circuit for Multiplication and Inversion in GF(2(m)) A Combined Circuit for Multiplication and Inversion in GF(2(m)) A Combined Circuit for Multiplication and Inversion in GF(2(m)) IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 55, 11, 1144-1148 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 55, 11, 1144-1148 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 55, 11, 1144-1148 2008/11 Refereed English Research paper(scientific journal) Disclose to all
KUMAZAWA Fumio, TAKAGI Naofumi 熊澤文雄, 高木直史 KUMAZAWA Fumio, TAKAGI Naofumi Design Support of Digit-Recurrence Algorithms for Arithmetic Circuits 複合算術演算の減算シフト型ハードウェアアルゴリズムの設計支援 Design Support of Digit-Recurrence Algorithms for Arithmetic Circuits Transactions of IEICE, J91-A, 11, 1026-1035 電子情報通信学会論文誌, J91-A, 11, 1026-1035 Transactions of IEICE, J91-A, 11, 1026-1035 2008/11 Refereed Japanese Research paper(scientific journal) Disclose to all
H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M.Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M.Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M.Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi SFQ cell design for A Nb-10-layer process SFQ cell design for A Nb-10-layer process SFQ cell design for A Nb-10-layer process Abstracts on 21th International Symposium on Superconductivity (ISS2008) Abstracts on 21th International Symposium on Superconductivity (ISS2008) Abstracts on 21th International Symposium on Superconductivity (ISS2008) 2008/10 Refereed English Research paper(international conference proceedings) Disclose to all
I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami An operand routing network for an SFQ-RDP processor: new design and experimental results An operand routing network for an SFQ-RDP processor: new design and experimental results An operand routing network for an SFQ-RDP processor: new design and experimental results Abstracts on 21th International Symposium on Superconductivity (ISS2008) Abstracts on 21th International Symposium on Superconductivity (ISS2008) Abstracts on 21th International Symposium on Superconductivity (ISS2008) 2008/10 Refereed English Research paper(international conference proceedings) Disclose to all
KITO NobutakaTAKAGI Naofumi 鬼頭信貴, 高木直史 KITO NobutakaTAKAGI Naofumi A Design Method of Easily Testable Multipliers with Various Structures of Partial Product Adder 種々の部分積加算構造をもつテスト容易な乗算器の設計 A Design Method of Easily Testable Multipliers with Various Structures of Partial Product Adder Transactions of IEICE, J91-D, 10, 2478-2486 電子情報通信学会論文誌, J91-D, 10, 2478-2486 Transactions of IEICE, J91-D, 10, 2478-2486 2008/10 Refereed Japanese Research paper(scientific journal) Disclose to all
H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi Novel serial-parallel converter using SFQ logic circuits Novel serial-parallel converter using SFQ logic circuits Novel serial-parallel converter using SFQ logic circuits PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 468, 15-20, 1977-1982 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 468, 15-20, 1977-1982 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 468, 15-20, 1977-1982 2008/09 Refereed English Research paper(scientific journal) Disclose to all
A. Fujimaki, S. Iwasaki, K. Takagi, R. Kasagi, I. Kataeva, H. Akaike, M. Tanaka, N. Takagi, N. Yoshikawa, K. Murakami A. Fujimaki, S. Iwasaki, K. Takagi, R. Kasagi, I. Kataeva, H. Akaike, M. Tanaka, N. Takagi, N. Yoshikawa, K. Murakami A. Fujimaki, S. Iwasaki, K. Takagi, R. Kasagi, I. Kataeva, H. Akaike, M. Tanaka, N. Takagi, N. Yoshikawa, K. Murakami Demonstration of an SFQ-Based Accelerator Prototype for a High-Performance Computer Demonstration of an SFQ-Based Accelerator Prototype for a High-Performance Computer Demonstration of an SFQ-Based Accelerator Prototype for a High-Performance Computer 2008 Applied Superconductivity Conference (ASC 2008) 2008 Applied Superconductivity Conference (ASC 2008) 2008 Applied Superconductivity Conference (ASC 2008) 2008/08 Refereed English Research paper(international conference proceedings) Disclose to all
KAWASHIMA Hirotaka, SHIBAOKA Masayuki, TAKAGI Naofumi, TAKAGI KAzuyoshi 川島裕崇, 柴岡雅之, 高木直史, 高木一義 KAWASHIMA Hirotaka, SHIBAOKA Masayuki, TAKAGI Naofumi, TAKAGI KAzuyoshi Reduced Area Multipliers Based on Karatsuba Algorithm Karatsubaアルゴリズムに基づく小面積乗算器 Reduced Area Multipliers Based on Karatsuba Algorithm Transactions of IEICE, J91-A, 7, 707-715 電子情報通信学会論文誌, J91-A, 7, 707-715 Transactions of IEICE, J91-A, 7, 707-715 2008/07 Refereed Japanese Research paper(scientific journal) Disclose to all
Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits IEICE TRANSACTIONS ON ELECTRONICS, E91C, 3, 350-355 IEICE TRANSACTIONS ON ELECTRONICS, E91C, 3, 350-355 IEICE TRANSACTIONS ON ELECTRONICS, E91C, 3, 350-355 2008/03 Refereed English Research paper(scientific journal) Disclose to all
S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa New Nb multi-layer Fabrication Process for Superconducting SFQ VLSI Circuits New Nb multi-layer Fabrication Process for Superconducting SFQ VLSI Circuits New Nb multi-layer Fabrication Process for Superconducting SFQ VLSI Circuits Superconducting SFQ VLSI Workshop 2008, A1-1 Superconducting SFQ VLSI Workshop 2008, A1-1 Superconducting SFQ VLSI Workshop 2008, A1-1 2008/03 English Research paper(international conference proceedings) Disclose to all
I. Kataeva, S. Iwasaki, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami I. Kataeva, S. Iwasaki, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami I. Kataeva, S. Iwasaki, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami Demonstration of the key components of an SFQ Reconfigurable Data-Paths Processor: an Operand Routing Network and a 2×2 RDP prototype Demonstration of the key components of an SFQ Reconfigurable Data-Paths Processor: an Operand Routing Network and a 2×2 RDP prototype Demonstration of the key components of an SFQ Reconfigurable Data-Paths Processor: an Operand Routing Network and a 2×2 RDP prototype Superconducting SFQ VLSI Workshop 2008, I2 Superconducting SFQ VLSI Workshop 2008, I2 Superconducting SFQ VLSI Workshop 2008, I2 2008/03 English Research paper(international conference proceedings) Disclose to all
M. Tanaka, K. Obata, Y. Yamanashi, H. Park, S. Iwasaki, K. Taketomi, K. Takagi, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa M. Tanaka, K. Obata, Y. Yamanashi, H. Park, S. Iwasaki, K. Taketomi, K. Takagi, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa M. Tanaka, K. Obata, Y. Yamanashi, H. Park, S. Iwasaki, K. Taketomi, K. Takagi, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa CORE1: Review and Recent Developments in Bit-serial SFQ Microprocessors CORE1: Review and Recent Developments in Bit-serial SFQ Microprocessors CORE1: Review and Recent Developments in Bit-serial SFQ Microprocessors Superconducting SFQ VLSI Workshop 2008, I3 Superconducting SFQ VLSI Workshop 2008, I3 Superconducting SFQ VLSI Workshop 2008, I3 2008/03 English Research paper(international conference proceedings) Disclose to all
H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi Design and Implementation of the SFQ Floating Point Units Design and Implementation of the SFQ Floating Point Units Design and Implementation of the SFQ Floating Point Units Superconducting SFQ VLSI Workshop 2008, A2-5 Superconducting SFQ VLSI Workshop 2008, A2-5 Superconducting SFQ VLSI Workshop 2008, A2-5 2008/03 English Research paper(international conference proceedings) Disclose to all
H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi Design and Implementation of the SFQ Half-Precision Floating Point Adder Design and Implementation of the SFQ Half-Precision Floating Point Adder Design and Implementation of the SFQ Half-Precision Floating Point Adder Superconducting SFQ VLSI Workshop 2008, P2-9 Superconducting SFQ VLSI Workshop 2008, P2-9 Superconducting SFQ VLSI Workshop 2008, P2-9 2008/03 English Research paper(international conference proceedings) Disclose to all
Marcelo E. Kaihara, Naofumi Takagi Marcelo E. Kaihara, Naofumi Takagi Marcelo E. Kaihara, Naofumi Takagi Bipartite modular multiplication method Bipartite modular multiplication method Bipartite modular multiplication method IEEE TRANSACTIONS ON COMPUTERS, 57, 2, 157-164 IEEE TRANSACTIONS ON COMPUTERS, 57, 2, 157-164 IEEE TRANSACTIONS ON COMPUTERS, 57, 2, 157-164 2008/02 Refereed English Research paper(scientific journal) Disclose to all
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Proceedings - IEEE International Symposium on Circuits and Systems, 1688-1691 Proceedings - IEEE International Symposium on Circuits and Systems, 1688-1691 Proceedings - IEEE International Symposium on Circuits and Systems, 1688-1691 2008 Refereed English Research paper(international conference proceedings) Disclose to all
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 1688-1691 PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 1688-1691 PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 1688-1691 2008 Refereed English Research paper(international conference proceedings) Disclose to all
Nobutaka Kito, Naofumi Takagi Nobutaka Kito, Naofumi Takagi Nobutaka Kito, Naofumi Takagi Level-testability of multi-operand adders Level-testability of multi-operand adders Level-testability of multi-operand adders PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 257-260 PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 257-260 PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 257-260 2008 Refereed English Research paper(international conference proceedings) Disclose to all
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits IEICE TRANSACTIONS ON ELECTRONICS, E90C, 12, 2278-2284 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 12, 2278-2284 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 12, 2278-2284 2007/12 Refereed English Research paper(scientific journal) Disclose to all
S. Iwasaki, M. Tanaka, Y. Yamanashi, H. Park, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, H. Honda, K. Inoue S. Iwasaki, M. Tanaka, Y. Yamanashi, H. Park, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, H. Honda, K. Inoue S. Iwasaki, M. Tanaka, Y. Yamanashi, H. Park, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, H. Honda, K. Inoue Design of a reconfigurable data-path prototype in the single-flux-quantum circuit Design of a reconfigurable data-path prototype in the single-flux-quantum circuit Design of a reconfigurable data-path prototype in the single-flux-quantum circuit SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 20, 11, S328-S331 SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 20, 11, S328-S331 SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 20, 11, S328-S331 2007/11 Refereed English Research paper(scientific journal) Disclose to all
H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Fujiwara, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Fujiwara, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Fujiwara, N. Takagi Multufunctional Buffers Using SFQ Logic Circuits Multufunctional Buffers Using SFQ Logic Circuits Multufunctional Buffers Using SFQ Logic Circuits Abstracts on 20th International Symposium on Superconductivity (ISS2007), FDP-73, pp. 325 Abstracts on 20th International Symposium on Superconductivity (ISS2007), FDP-73, pp. 325 Abstracts on 20th International Symposium on Superconductivity (ISS2007), FDP-73, pp. 325 2007/11 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Yamanashi, H. Park, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi Y. Yamanashi, H. Park, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi Y. Yamanashi, H. Park, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi Design and Implementation of Single-Flux-Quantum Floating-Point Adders Design and Implementation of Single-Flux-Quantum Floating-Point Adders Design and Implementation of Single-Flux-Quantum Floating-Point Adders Extended Abstract of 11th International Superconductivity Conference,Washington DC Extended Abstract of 11th International Superconductivity Conference,Washington DC Extended Abstract of 11th International Superconductivity Conference,Washington DC 2007/06 Refereed English Research paper(international conference proceedings) Disclose to all
H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi Fast Bit-Serial Multipliers Using RSFQ Logic Circuits Fast Bit-Serial Multipliers Using RSFQ Logic Circuits Fast Bit-Serial Multipliers Using RSFQ Logic Circuits Extended Abstract of 11th International Superconductivity Conference, Washington DC Extended Abstract of 11th International Superconductivity Conference, Washington DC Extended Abstract of 11th International Superconductivity Conference, Washington DC 2007/06 Refereed English Research paper(international conference proceedings) Disclose to all
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Koji Obata, Kazuyoshi Takagi, Naofumi Takagi Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 1, 257-266 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 1, 257-266 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A, 1, 257-266 2007/01 Refereed English Research paper(scientific journal) Disclose to all
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi An algorithm for inversion in GF (2(m)) - Suitable for implementation using a polynomial multiply instruction on GF(2) An algorithm for inversion in GF (2(m)) - Suitable for implementation using a polynomial multiply instruction on GF(2) An algorithm for inversion in GF (2(m)) - Suitable for implementation using a polynomial multiply instruction on GF(2) 18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 105-+ 18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 105-+ 18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 105-+ 2007 Refereed English Research paper(international conference proceedings) Disclose to all
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi A hardware algorithm for integer division using the SD2 representation A hardware algorithm for integer division using the SD2 representation A hardware algorithm for integer division using the SD2 representation IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 10, 2874-2881 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 10, 2874-2881 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 10, 2874-2881 2006/10 Refereed English Research paper(scientific journal) Disclose to all
K. Obata, M. Tanaka, Y. Tashiro, Y. Kamiya, N. Irie, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu K. Obata, M. Tanaka, Y. Tashiro, Y. Kamiya, N. Irie, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu K. Obata, M. Tanaka, Y. Tashiro, Y. Kamiya, N. Irie, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu Single-flux-quantum integer multiplier with systolic array structure Single-flux-quantum integer multiplier with systolic array structure Single-flux-quantum integer multiplier with systolic array structure PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 445, 1-2, 1014-1019 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 445, 1-2, 1014-1019 PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 445, 1-2, 1014-1019 2006/10 Refereed English Research paper(scientific journal) Disclose to all
A. Fujimaki, M. Tanaka, N. Irie, S. Iwasaki, T. Yamada, N. Takagi, H. Park, Y. Yamanashi, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai A. Fujimaki, M. Tanaka, N. Irie, S. Iwasaki, T. Yamada, N. Takagi, H. Park, Y. Yamanashi, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai A. Fujimaki, M. Tanaka, N. Irie, S. Iwasaki, T. Yamada, N. Takagi, H. Park, Y. Yamanashi, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai Development of High-speed Single-flux-quantum Microprocessors Development of High-speed Single-flux-quantum Microprocessors Development of High-speed Single-flux-quantum Microprocessors on 19th International Symposium on Superconductivity (ISS2006), 160 on 19th International Symposium on Superconductivity (ISS2006), 160 on 19th International Symposium on Superconductivity (ISS2006), 160 2006/10 Refereed English Research paper(international conference proceedings) Disclose to all
Fumio Kumazawa, Naofumi Takagi Fumio Kumazawa, Naofumi Takagi Fumio Kumazawa, Naofumi Takagi Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 6, 1799-1806 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 6, 1799-1806 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A, 6, 1799-1806 2006/06 Refereed English Research paper(scientific journal) Disclose to all
Yong-hee Jang, Naofumi Takagi, Kazuyoshi Takagi, Yong-jin Kwon Yong-hee Jang, Naofumi Takagi, Kazuyoshi Takagi, Yong-jin Kwon Yong-hee Jang, Naofumi Takagi, Kazuyoshi Takagi, Yong-jin Kwon New countermeasures against power analysis attacks for Koblitz curve cryptosystems New countermeasures against power analysis attacks for Koblitz curve cryptosystems New countermeasures against power analysis attacks for Koblitz curve cryptosystems 2006 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND SECURITY, PTS 1 AND 2, PROCEEDINGS, 2, 1303-1306 2006 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND SECURITY, PTS 1 AND 2, PROCEEDINGS, 2, 1303-1306 2006 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND SECURITY, PTS 1 AND 2, PROCEEDINGS, 2, 1303-1306 2006 Refereed English Research paper(international conference proceedings) Disclose to all
Naofumi Takagi, Kazuyoshi Takagi Naofumi Takagi, Kazuyoshi Takagi Naofumi Takagi, Kazuyoshi Takagi A VLSI algorithm for integer square-rooting A VLSI algorithm for integer square-rooting A VLSI algorithm for integer square-rooting 2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2, 573-+ 2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2, 573-+ 2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2, 573-+ 2006 Refereed English Research paper(international conference proceedings) Disclose to all
ME Kaihara, N Takagi ME Kaihara, N Takagi ME Kaihara, N Takagi A hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm A hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm A hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3610-3617 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3610-3617 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E88A, 12, 3610-3617 2005/12 Refereed English Research paper(scientific journal) Disclose to all
T Nishigai, M Ito, N Yoshikawa, K Obata, K Takagai, N Takagai, A Fujimaki, H Terai, S Yorozu T Nishigai, M Ito, N Yoshikawa, K Obata, K Takagai, N Takagai, A Fujimaki, H Terai, S Yorozu T Nishigai, M Ito, N Yoshikawa, K Obata, K Takagai, N Takagai, A Fujimaki, H Terai, S Yorozu Advanced design approaches for SFQ logic circuits based on the binary decision diagram Advanced design approaches for SFQ logic circuits based on the binary decision diagram Advanced design approaches for SFQ logic circuits based on the binary decision diagram IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 15, 2, 380-383 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 15, 2, 380-383 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 15, 2, 380-383 2005/06 Refereed English Research paper(scientific journal) Disclose to all
OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi 小畑幸嗣, 高木一義, 高木直史 OBATA Koji, TAKAGI Kazuyoshi, TAKAGI Naofumi Design Method of Dual-Rail RSFQ Logic Circuits Using 2x2-Join 2x2-Join を用いた二線式RSFQ論理回路設計手法 Design Method of Dual-Rail RSFQ Logic Circuits Using 2x2-Join Transactions of IEICE, J88-C, 3, 202-209 電子情報通信学会論文誌, J88-C, 3, 202-209 Transactions of IEICE, J88-C, 3, 202-209 2005/03 Refereed Japanese Research paper(scientific journal) Disclose to all
ME Kaihara, N Takagi ME Kaihara, N Takagi ME Kaihara, N Takagi A hardware algorithm for modular multiplication/division A hardware algorithm for modular multiplication/division A hardware algorithm for modular multiplication/division IEEE TRANSACTIONS ON COMPUTERS, 54, 1, 12-21 IEEE TRANSACTIONS ON COMPUTERS, 54, 1, 12-21 IEEE TRANSACTIONS ON COMPUTERS, 54, 1, 12-21 2005/01 Refereed English Research paper(scientific journal) Disclose to all
N Takagi, S Kadowaki, K Takagi N Takagi, S Kadowaki, K Takagi N Takagi, S Kadowaki, K Takagi A hardware algorithm for integer division A hardware algorithm for integer division A hardware algorithm for integer division 17th IEEE Symposium on Computer Arithmetic, Proceedings, 140-146 17th IEEE Symposium on Computer Arithmetic, Proceedings, 140-146 17th IEEE Symposium on Computer Arithmetic, Proceedings, 140-146 2005 Refereed English Research paper(international conference proceedings) Disclose to all
ME Kaihara, N Takagi ME Kaihara, N Takagi ME Kaihara, N Takagi Bipartite modular multiplication Bipartite modular multiplication Bipartite modular multiplication CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 3659, 201-210 CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 3659, 201-210 CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 3659, 201-210 2005 Refereed English Research paper(scientific journal) Disclose to all
NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi NAKAMURA Kazuhiro, SAWADA Yuki, TAKAGI Kazuyoshi, TAKAGI Naofumi A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems Proceedings - 2004 International SoC Design Conference, 109-112 Proceedings - 2004 International SoC Design Conference, 109-112 Proceedings - 2004 International SoC Design Conference, 109-112 2004/10 Refereed English Research paper(international conference proceedings) Disclose to all
NT Quach, NF Takagi, MJ Flynn NT Quach, NF Takagi, MJ Flynn NT Quach, NF Takagi, MJ Flynn Systematic IEEE rounding method for high-speed floating-point multipliers Systematic IEEE rounding method for high-speed floating-point multipliers Systematic IEEE rounding method for high-speed floating-point multipliers IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12, 5, 511-521 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12, 5, 511-521 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12, 5, 511-521 2004/05 Refereed English Research paper(scientific journal) Disclose to all
KUMAZAWA Fumio, TAKAGI Naofumi, TAKAUCHI Daisuke, TAKAGI Kazuyoshi 熊澤文雄, 高木直史, 武内大輔, 高木一義 KUMAZAWA Fumio, TAKAGI Naofumi, TAKAUCHI Daisuke, TAKAGI Kazuyoshi Floating-Point Euclidean Norm Computing Circuit 浮動小数点ユークリッドノルム計算回路 Floating-Point Euclidean Norm Computing Circuit Transactions of IEICE, J86-A, 4, 456-464 電子情報通信学会論文誌, J86-A, 4, 456-464 Transactions of IEICE, J86-A, 4, 456-464 2003/04 Refereed Japanese Research paper(scientific journal) Disclose to all
ME Kaihara, N Takagi ME Kaihara, N Takagi ME Kaihara, N Takagi A VLSI algorithm for modular multiplication/division A VLSI algorithm for modular multiplication/division A VLSI algorithm for modular multiplication/division 16TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 220-227 16TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 220-227 16TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 220-227 2003 Refereed English Research paper(international conference proceedings) Disclose to all
N Takagi, D Matsuoka, K Takagi N Takagi, D Matsuoka, K Takagi N Takagi, D Matsuoka, K Takagi Digit-recurrence algorithm for computing reciprocal square-root Digit-recurrence algorithm for computing reciprocal square-root Digit-recurrence algorithm for computing reciprocal square-root IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 1, 221-228 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 1, 221-228 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E86A, 1, 221-228 2003/01 Refereed English Research paper(scientific journal) Disclose to all
Y Watanabe, N Takagi, K Takagi Y Watanabe, N Takagi, K Takagi Y Watanabe, N Takagi, K Takagi A VLSI algorithm for division in GF(2(m)) based on extended binary GCD algorithm A VLSI algorithm for division in GF(2(m)) based on extended binary GCD algorithm A VLSI algorithm for division in GF(2(m)) based on extended binary GCD algorithm IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 5, 994-999 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 5, 994-999 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A, 5, 994-999 2002/05 Refereed English Research paper(scientific journal) Disclose to all
K Nakamura, N Murakami, K Takagi, N Takagi K Nakamura, N Murakami, K Takagi, N Takagi K Nakamura, N Murakami, K Takagi, N Takagi A real-time lipreading LSI for word recognition A real-time lipreading LSI for word recognition A real-time lipreading LSI for word recognition 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 303-306 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 303-306 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 303-306 2002 Refereed English Research paper(international conference proceedings) Disclose to all
N Takagi, J Yoshiki, K Takagi N Takagi, J Yoshiki, K Takagi N Takagi, J Yoshiki, K Takagi A fast algorithm for multiplicative inversion in GF(2(m)) using normal basis A fast algorithm for multiplicative inversion in GF(2(m)) using normal basis A fast algorithm for multiplicative inversion in GF(2(m)) using normal basis IEEE TRANSACTIONS ON COMPUTERS, 50, 5, 394-398 IEEE TRANSACTIONS ON COMPUTERS, 50, 5, 394-398 IEEE TRANSACTIONS ON COMPUTERS, 50, 5, 394-398 2001/05 Refereed English Research paper(scientific journal) Disclose to all
N Takagi N Takagi N Takagi A digit-recurrence algorithm for cube rooting A digit-recurrence algorithm for cube rooting A digit-recurrence algorithm for cube rooting IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 5, 1309-1314 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 5, 1309-1314 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 5, 1309-1314 2001/05 Refereed English Research paper(scientific journal) Disclose to all
N Takagi N Takagi N Takagi A hardware algorithm for computing reciprocal square root A hardware algorithm for computing reciprocal square root A hardware algorithm for computing reciprocal square root ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 94-100 ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 94-100 ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 94-100 2001 Refereed English Research paper(international conference proceedings) Disclose to all
A Higuchi, N Takagi A Higuchi, N Takagi A Higuchi, N Takagi A fast addition algorithm for elliptic curve arithmetic in GF(2(n)) using projective coordinates A fast addition algorithm for elliptic curve arithmetic in GF(2(n)) using projective coordinates A fast addition algorithm for elliptic curve arithmetic in GF(2(n)) using projective coordinates INFORMATION PROCESSING LETTERS, 76, 3, 101-103 INFORMATION PROCESSING LETTERS, 76, 3, 101-103 INFORMATION PROCESSING LETTERS, 76, 3, 101-103 2000/12 Refereed English Research paper(scientific journal) Disclose to all
N Takagi, S Kuwahara N Takagi, S Kuwahara N Takagi, S Kuwahara A VLSI algorithm for computing the Euclidean norm of a 3D vector A VLSI algorithm for computing the Euclidean norm of a 3D vector A VLSI algorithm for computing the Euclidean norm of a 3D vector IEEE TRANSACTIONS ON COMPUTERS, 49, 10, 1074-1082 IEEE TRANSACTIONS ON COMPUTERS, 49, 10, 1074-1082 IEEE TRANSACTIONS ON COMPUTERS, 49, 10, 1074-1082 2000/10 Refereed English Research paper(scientific journal) Disclose to all
K Takagi, N Takagi K Takagi, N Takagi K Takagi, N Takagi Minimum cut linear arrangement of p-q dags for VLSI layout of adder trees Minimum cut linear arrangement of p-q dags for VLSI layout of adder trees Minimum cut linear arrangement of p-q dags for VLSI layout of adder trees IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 5, 767-774 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 5, 767-774 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 5, 767-774 1999/05 Refereed English Research paper(scientific journal) Disclose to all
N Takagi, T Horiyama N Takagi, T Horiyama N Takagi, T Horiyama A high-speed reduced-size adder under left-to-right input arrival A high-speed reduced-size adder under left-to-right input arrival A high-speed reduced-size adder under left-to-right input arrival IEEE TRANSACTIONS ON COMPUTERS, 48, 1, 76-80 IEEE TRANSACTIONS ON COMPUTERS, 48, 1, 76-80 IEEE TRANSACTIONS ON COMPUTERS, 48, 1, 76-80 1999/01 Refereed English Research paper(scientific journal) Disclose to all
N Takagi, S Kuwahara N Takagi, S Kuwahara N Takagi, S Kuwahara Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 86-93 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 86-93 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 86-93 1999 Refereed English Research paper(international conference proceedings) Disclose to all
N Takagi N Takagi N Takagi Powering by a table look-up and a multiplication with operand modification Powering by a table look-up and a multiplication with operand modification Powering by a table look-up and a multiplication with operand modification IEEE TRANSACTIONS ON COMPUTERS, 47, 11, 1216-1222 IEEE TRANSACTIONS ON COMPUTERS, 47, 11, 1216-1222 IEEE TRANSACTIONS ON COMPUTERS, 47, 11, 1216-1222 1998/11 Refereed English Research paper(scientific journal) Disclose to all
N Takagi N Takagi N Takagi A VLSI algorithm for modular division based on the binary GCD algorithm A VLSI algorithm for modular division based on the binary GCD algorithm A VLSI algorithm for modular division based on the binary GCD algorithm IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A, 5, 724-728 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A, 5, 724-728 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A, 5, 724-728 1998/05 Refereed English Research paper(scientific journal) Disclose to all
T Hamano, N Takagi, S Yajima, FP Preparata T Hamano, N Takagi, S Yajima, FP Preparata T Hamano, N Takagi, S Yajima, FP Preparata O(n)-depth modular exponentiation circuit algorithm O(n)-depth modular exponentiation circuit algorithm O(n)-depth modular exponentiation circuit algorithm IEEE TRANSACTIONS ON COMPUTERS, 46, 6, 701-704 IEEE TRANSACTIONS ON COMPUTERS, 46, 6, 701-704 IEEE TRANSACTIONS ON COMPUTERS, 46, 6, 701-704 1997/06 Refereed English Research paper(scientific journal) Disclose to all
M Ito, N Takagi, S Yajima M Ito, N Takagi, S Yajima M Ito, N Takagi, S Yajima Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification IEEE TRANSACTIONS ON COMPUTERS, 46, 4, 495-498 IEEE TRANSACTIONS ON COMPUTERS, 46, 4, 495-498 IEEE TRANSACTIONS ON COMPUTERS, 46, 4, 495-498 1997/04 Refereed English Research paper(scientific journal) Disclose to all
N Takagi N Takagi N Takagi Generating a power of an operand by a table look-up and a multiplication Generating a power of an operand by a table look-up and a multiplication Generating a power of an operand by a table look-up and a multiplication 13TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 126-131 13TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 126-131 13TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 126-131 1997 Refereed English Research paper(international conference proceedings) Disclose to all
Masayuki Ito, Naofumi Takagi, Shuzo Yajima Masayuki Ito, Naofumi Takagi, Shuzo Yajima Masayuki Ito, Naofumi Takagi, Shuzo Yajima Square rooting by iterative multiply-additions Square rooting by iterative multiply-additions Square rooting by iterative multiply-additions Information Processing Letters, 60, 5, 267-269 Information Processing Letters, 60, 5, 267-269 Information Processing Letters, 60, 5, 267-269 1996/12/09 Refereed English Research paper(scientific journal) Disclose to all
N Takagi N Takagi N Takagi A hardware algorithm for modular division based on the extended euclidean algorithm A hardware algorithm for modular division based on the extended euclidean algorithm A hardware algorithm for modular division based on the extended euclidean algorithm IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D, 11, 1518-1522 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D, 11, 1518-1522 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D, 11, 1518-1522 1996/11 Refereed English Research paper(scientific journal) Disclose to all
N TAKAGI N TAKAGI N TAKAGI A MULTIPLE-PRECISION MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS A MULTIPLE-PRECISION MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS A MULTIPLE-PRECISION MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E78D, 10, 1313-1315 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E78D, 10, 1313-1315 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E78D, 10, 1313-1315 1995/10 Refereed English Research paper(scientific journal) Disclose to all
H HASSLER, N TAKAGI H HASSLER, N TAKAGI H HASSLER, N TAKAGI Function evaluation by table look-up and addition Function evaluation by table look-up and addition Function evaluation by table look-up and addition PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 10-16 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 10-16 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 10-16 1995 Refereed English Research paper(international conference proceedings) Disclose to all
T HAMANO, N TAKAGI, S YAJIMA, FP PREPARATA T HAMANO, N TAKAGI, S YAJIMA, FP PREPARATA T HAMANO, N TAKAGI, S YAJIMA, FP PREPARATA O(n)-depth circuit algorithm for modular exponentiation O(n)-depth circuit algorithm for modular exponentiation O(n)-depth circuit algorithm for modular exponentiation PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 188-192 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 188-192 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 188-192 1995 Refereed English Research paper(international conference proceedings) Disclose to all
M ITO, N TAKAGI, S YAJIMA M ITO, N TAKAGI, S YAJIMA M ITO, N TAKAGI, S YAJIMA Efficient initial approximation and fast converging methods for division and square root Efficient initial approximation and fast converging methods for division and square root Efficient initial approximation and fast converging methods for division and square root PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 2-9 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 2-9 PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 2-9 1995 Refereed English Research paper(international conference proceedings) Disclose to all
N TAKAGI N TAKAGI N TAKAGI A MODULAR INVERSION HARDWARE ALGORITHM WITH A REDUNDANT BINARY REPRESENTATION A MODULAR INVERSION HARDWARE ALGORITHM WITH A REDUNDANT BINARY REPRESENTATION A MODULAR INVERSION HARDWARE ALGORITHM WITH A REDUNDANT BINARY REPRESENTATION IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E76D, 8, 863-869 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E76D, 8, 863-869 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E76D, 8, 863-869 1993/08 Refereed English Research paper(scientific journal) Disclose to all
N TAKAGI N TAKAGI N TAKAGI A MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS A MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS A MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS 11TH SYMPOSIUM ON COMPUTER ARITHMETIC : PROCEEDINGS, 11, 272-276 11TH SYMPOSIUM ON COMPUTER ARITHMETIC : PROCEEDINGS, 11, 272-276 11TH SYMPOSIUM ON COMPUTER ARITHMETIC : PROCEEDINGS, 11, 272-276 1993 Refereed English Research paper(international conference proceedings) Disclose to all
N TAKAGI N TAKAGI N TAKAGI A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM FOR MODULAR EXPONENTIATION A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM FOR MODULAR EXPONENTIATION A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM FOR MODULAR EXPONENTIATION IEEE TRANSACTIONS ON COMPUTERS, 41, 8, 949-956 IEEE TRANSACTIONS ON COMPUTERS, 41, 8, 949-956 IEEE TRANSACTIONS ON COMPUTERS, 41, 8, 949-956 1992/08 Refereed English Research paper(scientific journal) Disclose to all
N TAKAGI, S YAJIMA N TAKAGI, S YAJIMA N TAKAGI, S YAJIMA MODULAR MULTIPLICATION HARDWARE ALGORITHMS WITH A REDUNDANT REPRESENTATION AND THEIR APPLICATION TO RSA CRYPTOSYSTEM MODULAR MULTIPLICATION HARDWARE ALGORITHMS WITH A REDUNDANT REPRESENTATION AND THEIR APPLICATION TO RSA CRYPTOSYSTEM MODULAR MULTIPLICATION HARDWARE ALGORITHMS WITH A REDUNDANT REPRESENTATION AND THEIR APPLICATION TO RSA CRYPTOSYSTEM IEEE TRANSACTIONS ON COMPUTERS, 41, 7, 887-891 IEEE TRANSACTIONS ON COMPUTERS, 41, 7, 887-891 IEEE TRANSACTIONS ON COMPUTERS, 41, 7, 887-891 1992/07 Refereed English Research paper(scientific journal) Disclose to all
TAKENAGA Yasuhiko, TAKAGI Naofumi, YAJIMA Shuzo 武永康彦, 高木直史, 矢島脩三 TAKENAGA Yasuhiko, TAKAGI Naofumi, YAJIMA Shuzo Computational Power of a Memory-Based Parallel Computation Model with Content Addressable Memory 連想メモリによるメモリ型並列計算モデルの計算能力 Computational Power of a Memory-Based Parallel Computation Model with Content Addressable Memory Transactions of IPSJ, 33, 4, 415-422 情報処理学会論文誌, 33, 4, 415-422 Transactions of IPSJ, 33, 4, 415-422 1992/04 Refereed Japanese Research paper(scientific journal) Disclose to all
N TAKAGI, T ASADA, S YAJIMA N TAKAGI, T ASADA, S YAJIMA N TAKAGI, T ASADA, S YAJIMA REDUNDANT CORDIC METHODS WITH A CONSTANT SCALE FACTOR FOR SINE AND COSINE COMPUTATION REDUNDANT CORDIC METHODS WITH A CONSTANT SCALE FACTOR FOR SINE AND COSINE COMPUTATION REDUNDANT CORDIC METHODS WITH A CONSTANT SCALE FACTOR FOR SINE AND COSINE COMPUTATION IEEE TRANSACTIONS ON COMPUTERS, 40, 9, 989-995 IEEE TRANSACTIONS ON COMPUTERS, 40, 9, 989-995 IEEE TRANSACTIONS ON COMPUTERS, 40, 9, 989-995 1991/09 Refereed English Research paper(scientific journal) Disclose to all
Yasuo Okabe, Naofumi Takagi, Shuzo Yajima Yasuo Okabe, Naofumi Takagi, Shuzo Yajima Yasuo Okabe, Naofumi Takagi, Shuzo Yajima Log‐depth circuits for elementary functions using residue number system Log‐depth circuits for elementary functions using residue number system Log‐depth circuits for elementary functions using residue number system Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 74, 8, 31-38 Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 74, 8, 31-38 Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 74, 8, 31-38 1991 Refereed English Research paper(scientific journal) Disclose to all
Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima An on‐line error‐detectable high‐speed array divider An on‐line error‐detectable high‐speed array divider An on‐line error‐detectable high‐speed array divider Systems and Computers in Japan, 22, 1, 21-27 Systems and Computers in Japan, 22, 1, 21-27 Systems and Computers in Japan, 22, 1, 21-27 1991 Refereed English Research paper(scientific journal) Disclose to all
N TAKAGI N TAKAGI N TAKAGI A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM EFFICIENT FOR ITERATIVE MODULAR MULTIPLICATIONS A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM EFFICIENT FOR ITERATIVE MODULAR MULTIPLICATIONS A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM EFFICIENT FOR ITERATIVE MODULAR MULTIPLICATIONS 10TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, 35-42 10TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, 35-42 10TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, 35-42 1991 Refereed English Research paper(international conference proceedings) Disclose to all
N TAKAGI N TAKAGI N TAKAGI ARITHMETIC UNIT BASED ON A HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDITION TREE ARITHMETIC UNIT BASED ON A HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDITION TREE ARITHMETIC UNIT BASED ON A HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDITION TREE ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS II, 1566, 244-251 ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS II, 1566, 244-251 ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS II, 1566, 244-251 1991 Refereed English Research paper(international conference proceedings) Disclose to all
TAKAGI Naofumi, TAKENAGA Yasuhiko, YAJIMA Shuzo 高木直史, 武永康彦, 矢島脩三 TAKAGI Naofumi, TAKENAGA Yasuhiko, YAJIMA Shuzo A Memory-Type Parallel Computation Model and Its Computational Power - Yet Another Approach to Supercomputing メモリ型並列計算モデルとその計算能力 ― スーパコンピュータへの第3のアプローチ ― A Memory-Type Parallel Computation Model and Its Computational Power - Yet Another Approach to Supercomputing Transactions of IPSJ, 31, 11, 1565-1571 情報処理学会論文誌, 31, 11, 1565-1571 Transactions of IPSJ, 31, 11, 1565-1571 1990/11 Refereed Japanese Research paper(scientific journal) Disclose to all
OKABE Yasuo, TAKAGI Naofumi, YAJIMA Shuzo 岡部寿男, 高木直史, 矢島脩三 OKABE Yasuo, TAKAGI Naofumi, YAJIMA Shuzo Log Depth Circuits for Elementary Functions Using Residue Number System 剰余数表示法を用いた初等関数計算の対数段回路アルゴリズム Log Depth Circuits for Elementary Functions Using Residue Number System Transactions of IEICE, J73-D-I, 9, 723-728 電子情報通信学会論文誌, J73-D-I, 9, 723-728 Transactions of IEICE, J73-D-I, 9, 723-728 1990/09 Refereed Japanese Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, YAJIMA Shuzo 高木直史, 矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo An On-Line Error Detectable High-Speed Array Divider オンライン誤り検出可能な高速配列型除算器 An On-Line Error Detectable High-Speed Array Divider Transactions of IEICE, J73-D-I, 2, 148-153 電子情報通信学会論文誌, J73-D-I, 2, 148-153 Transactions of IEICE, J73-D-I, 2, 148-153 1990/02 Refereed Japanese Research paper(scientific journal) Disclose to all
OCHI Hiroyuki, TAKAGI Naofumi, YAJIMA Shuzo 越智裕之, 高木直史, 矢島脩三 OCHI Hiroyuki, TAKAGI Naofumi, YAJIMA Shuzo Vector Algorithms for Generating Prime Implicants of Logic Functions Based on Consensus Expansion 共有展開に基づくベクトル計算機向き論理関数素項生成法 Vector Algorithms for Generating Prime Implicants of Logic Functions Based on Consensus Expansion Transactions of IEICE, J72-D-I, 9, 652-659 電子情報通信学会論文誌, J72-D-I, 9, 652-659 Transactions of IEICE, J72-D-I, 9, 652-659 1989/09 Refereed Japanese Research paper(scientific journal) Disclose to all
Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima On-line error-detectable array divider with a redundant binary representation and a residue code. On-line error-detectable array divider with a redundant binary representation and a residue code. On-line error-detectable array divider with a redundant binary representation and a residue code. Digest of Papers - FTCS (Fault-Tolerant Computing Symposium), 174-179 Digest of Papers - FTCS (Fault-Tolerant Computing Symposium), 174-179 Digest of Papers - FTCS (Fault-Tolerant Computing Symposium), 174-179 1988/10 Refereed English Research paper(scientific journal) Disclose to all
ISHIURA Nagisa, TAKAGI Naofumi, YAJIMA Shuzo 石浦菜岐佐, 高木直史, 矢島脩三 ISHIURA Nagisa, TAKAGI Naofumi, YAJIMA Shuzo Sorting on a Vector Processor ベクトル計算機上でのソーティング Sorting on a Vector Processor Transactions of IPSJ, 29, 4, 378-385 情報処理学会論文誌, 29, 4, 378-385 Transactions of IPSJ, 29, 4, 378-385 1988/04 Refereed Japanese Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, OCHI Hiroyuki, YAJIMA Shuzo TAKAGI Naofumi, OCHI Hiroyuki, YAJIMA Shuzo Vector Algorithms for Generating Prime Implicants of Logic Functions Vector Algorithms for Generating Prime Implicants of Logic Functions Vector Algorithms for Generating Prime Implicants of Logic Functions Proceedings - Third International Conference on Supercomputing, 3, 281-287 Proceedings - Third International Conference on Supercomputing, 3, 281-287 Proceedings - Third International Conference on Supercomputing, 3, 281-287 1988 Refereed English Research paper(international conference proceedings) Disclose to all
N TAKAGI, S YAJIMA N TAKAGI, S YAJIMA N TAKAGI, S YAJIMA ONLINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER USING REDUNDANT BINARY REPRESENTATION AND 3-RAIL LOGIC ONLINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER USING REDUNDANT BINARY REPRESENTATION AND 3-RAIL LOGIC ONLINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER USING REDUNDANT BINARY REPRESENTATION AND 3-RAIL LOGIC IEEE TRANSACTIONS ON COMPUTERS, 36, 11, 1310-1317 IEEE TRANSACTIONS ON COMPUTERS, 36, 11, 1310-1317 IEEE TRANSACTIONS ON COMPUTERS, 36, 11, 1310-1317 1987/11 Refereed English Research paper(scientific journal) Disclose to all
OHKUBO Masaaki, YASUURA Hiroto, TAKAGI Naofumi, YAJIMA Shuzo 大久保雅且, 安浦寛人, 高木直史, 矢島脩三 OHKUBO Masaaki, YASUURA Hiroto, TAKAGI Naofumi, YAJIMA Shuzo A Hardware-Oriented Unification Algorithm Using a Cotent Addressable Memory 連想メモリを利用したハードウェア向き単一化アルゴリズム A Hardware-Oriented Unification Algorithm Using a Cotent Addressable Memory Transactions of IPSJ, 28, 9, 915-922 情報処理学会論文誌, 28, 9, 915-922 Transactions of IPSJ, 28, 9, 915-922 1987/09 Refereed Japanese Research paper(scientific journal) Disclose to all
Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION. Proceedings - Symposium on Computer Arithmetic, 80-86 Proceedings - Symposium on Computer Arithmetic, 80-86 Proceedings - Symposium on Computer Arithmetic, 80-86 1987/05 Refereed English Research paper(international conference proceedings) Disclose to all
Hiroto Yasuura, Naofumi Takagi, Shuzo Tajima 安浦寛人, 高木直史, 矢島脩三 Hiroto Yasuura, Naofumi Takagi, Shuzo Tajima ON HIGH-SPEED PARALLEL ALGORITHMS USING REDUNDANT CODING. 冗長符号化を利用した高速並列アルゴリズムについて ON HIGH-SPEED PARALLEL ALGORITHMS USING REDUNDANT CODING. Systems and Computers in Japan, J70-D, 3, 525-533 電子情報通信学会論文誌, J70-D, 3, 525-533 Systems and Computers in Japan, J70-D, 3, 525-533 1987/03 Refereed Japanese Research paper(scientific journal) Disclose to all
Y HARATA, Y NAKAMURA, H NAGASE, M TAKIGAWA, N TAKAGI Y HARATA, Y NAKAMURA, H NAGASE, M TAKIGAWA, N TAKAGI Y HARATA, Y NAKAMURA, H NAGASE, M TAKIGAWA, N TAKAGI A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE IEEE JOURNAL OF SOLID-STATE CIRCUITS, 22, 1, 28-34 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 22, 1, 28-34 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 22, 1, 28-34 1987/02 Refereed English Research paper(scientific journal) Disclose to all
Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima On high‐speed parallel algorithms using redundant coding On high‐speed parallel algorithms using redundant coding On high‐speed parallel algorithms using redundant coding Systems and Computers in Japan, 18, 12, 72-80 Systems and Computers in Japan, 18, 12, 72-80 Systems and Computers in Japan, 18, 12, 72-80 1987 Refereed English Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo 高木直史, 浅田徹, 矢島脩三 TAKAGI Naofumi, ASADA Tohru, YAJIMA Shuzo A Hardware Algorithm for Computing Sine and Cosine Using Redundant Binary Representation 冗長2進表現を利用した正弦・余弦計算用ハードウェアアルゴリズム A Hardware Algorithm for Computing Sine and Cosine Using Redundant Binary Representation Transactions of IECE, J69-D, 6, 841-847 電子通信学会論文誌, J69-D, 6, 841-847 Transactions of IECE, J69-D, 6, 841-847 1986/06 Refereed Japanese Research paper(scientific journal) Disclose to all
Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima A square root hardware algorithm using redundant binary representation A square root hardware algorithm using redundant binary representation A square root hardware algorithm using redundant binary representation Systems and Computers in Japan, 17, 11, 30-41 Systems and Computers in Japan, 17, 11, 30-41 Systems and Computers in Japan, 17, 11, 30-41 1986 Refereed English Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, YAJIMA Shuzo 高木直史, 矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo Hardware Algorithms for Computing Expornentials and Logarithms Using Redundant Binary Representation 冗長2進表現を利用した指数・対数関数計算用ハードウェアアルゴリズム Hardware Algorithms for Computing Expornentials and Logarithms Using Redundant Binary Representation Transactions of IECE, J69-D, 1, 11-20 電子通信学会論文誌, J69-D, 1, 11-20 Transactions of IECE, J69-D, 1, 11-20 1986/01 Refereed Japanese Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, YAJIMA Shuzo 高木直史, 矢島脩三 TAKAGI Naofumi, YAJIMA Shuzo A Square Root Hardware Algorithm Using Redundant Binary Representation 冗長2進表現を利用した開平用ハードウェアアルゴリズム A Square Root Hardware Algorithm Using Redundant Binary Representation Transactions of IECE, J69-D, 1, 1-10 電子通信学会論文誌, J69-D, 1, 1-10 Transactions of IECE, J69-D, 1, 1-10 1986/01 Refereed Japanese Research paper(scientific journal) Disclose to all
Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima Naofumi Takagi, Shuzo Yajima ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE. Proceedings - IEEE International Symposium on Circuits and Systems, 1321-1324 Proceedings - IEEE International Symposium on Circuits and Systems, 1321-1324 Proceedings - IEEE International Symposium on Circuits and Systems, 1321-1324 1985 Refereed English Research paper(international conference proceedings) Disclose to all
N TAKAGI, H YASUURA, S YAJIMA N TAKAGI, H YASUURA, S YAJIMA N TAKAGI, H YASUURA, S YAJIMA HIGH-SPEED VLSI MULTIPLICATION ALGORITHM WITH A REDUNDANT BINARY ADDITION TREE HIGH-SPEED VLSI MULTIPLICATION ALGORITHM WITH A REDUNDANT BINARY ADDITION TREE HIGH-SPEED VLSI MULTIPLICATION ALGORITHM WITH A REDUNDANT BINARY ADDITION TREE IEEE TRANSACTIONS ON COMPUTERS, 34, 9, 789-796 IEEE TRANSACTIONS ON COMPUTERS, 34, 9, 789-796 IEEE TRANSACTIONS ON COMPUTERS, 34, 9, 789-796 1985 Refereed English Research paper(scientific journal) Disclose to all
N TAKAGI, CK WONG N TAKAGI, CK WONG N TAKAGI, CK WONG A HARDWARE SORT-MERGE SYSTEM A HARDWARE SORT-MERGE SYSTEM A HARDWARE SORT-MERGE SYSTEM IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 29, 1, 49-67 IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 29, 1, 49-67 IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 29, 1, 49-67 1985 Refereed English Research paper(scientific journal) Disclose to all
HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi HARATA Yoshihisa, NAKAMURA Yoshio, NAGASE Hiroshi, TAKIGAWA Mitsuharu, TAKAGI Naofumi High Speed Multiplier Using Redundant Binary Adder Tree High Speed Multiplier Using Redundant Binary Adder Tree High Speed Multiplier Using Redundant Binary Adder Tree Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84), 165-170 Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84), 165-170 Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84), 165-170 1984/10 Refereed English Research paper(international conference proceedings) Disclose to all
TAKAGI Naofumi, YASUURA Hiroto, TAIMA Kenji, HAYATA Hiroshi, YAJIMA Shuzo 高木直史, 安浦寛人, 泰間健司, 早田宏, 矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, TAIMA Kenji, HAYATA Hiroshi, YAJIMA Shuzo An Implementation and Evaluation of the Parallell Enumeration Sorting Circuit 並列計数ソ―ティング回路の試作と評価 An Implementation and Evaluation of the Parallell Enumeration Sorting Circuit Transactions of IECE, J67-D, 5, 623-624 電子通信学会論文誌, J67-D, 5, 623-624 Transactions of IECE, J67-D, 5, 623-624 1984/05 Refereed Japanese Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, YASUURA Hiroto, YAJIMA SHUZO 高木直史, 安浦寛人, 矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, YAJIMA SHUZO A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation 冗長2進表現を利用したVLSI向き高速除算器 A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation Transactions of IECE, J67-D, 4, 450-457 電子通信学会論文誌, J67-D, 4, 450-457 Transactions of IECE, J67-D, 4, 450-457 1984/04 Refereed Japanese Research paper(scientific journal) Disclose to all
TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo 高木直史, 安浦寛人, 矢島脩三 TAKAGI Naofumi, YASUURA Hiroto, YAJIMA Shuzo A VLSI-Oriented High-Speed Multiplier Using a Redandant Binary Addition Tree 冗長2進加算木を用いたVLSI向き高速乗算器 A VLSI-Oriented High-Speed Multiplier Using a Redandant Binary Addition Tree Transaction of IECE, J66-D, 6, 683-690 電子通信学会論文誌, J66-D, 6, 683-690 Transaction of IECE, J66-D, 6, 683-690 1983/06 Refereed Japanese Research paper(scientific journal) Disclose to all
Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE. VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE. VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE. Systems, computers, controls, 14, 4, 19-28 Systems, computers, controls, 14, 4, 19-28 Systems, computers, controls, 14, 4, 19-28 1983 Refereed English Disclose to all
YASUURA Hiroto, TAKAGI Naofumi 安浦寛人, 高木直史 YASUURA Hiroto, TAKAGI Naofumi A High-Speed Sorting Circuit Using Parallel Enumeration Sort 並列計数法による高速ソーティング回路 A High-Speed Sorting Circuit Using Parallel Enumeration Sort Transactions of IECE, J65-D, 2, 179-186 電子通信学会論文誌, J65-D, 2, 179-186 Transactions of IECE, J65-D, 2, 179-186 1982/02 Refereed Japanese Research paper(scientific journal) Disclose to all
H YASUURA, N TAKAGI, S YAJIMA H YASUURA, N TAKAGI, S YAJIMA H YASUURA, N TAKAGI, S YAJIMA THE PARALLEL ENUMERATION SORTING SCHEME FOR VLSI THE PARALLEL ENUMERATION SORTING SCHEME FOR VLSI THE PARALLEL ENUMERATION SORTING SCHEME FOR VLSI IEEE TRANSACTIONS ON COMPUTERS, 31, 12, 1192-1201 IEEE TRANSACTIONS ON COMPUTERS, 31, 12, 1192-1201 IEEE TRANSACTIONS ON COMPUTERS, 31, 12, 1192-1201 1982 Refereed English Research paper(scientific journal) Disclose to all

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Title language:
Misc
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
谷 祐輔, 高瀬 英希, 大川 猛, 高木 一義, 高木 直史 谷 祐輔, 高瀬 英希, 大川 猛, 高木 一義, 高木 直史 谷 祐輔, 高瀬 英希, 大川 猛, 高木 一義, 高木 直史 A Comparative Evaluation of SW/HW Communication Methods on System Design Environments for Programmable SoCs プログラマブルSoCのためのシステム設計環境におけるSW/HW間通信方式の比較評価 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2016) A Comparative Evaluation of SW/HW Communication Methods on System Design Environments for Programmable SoCs 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 115, 518, 139-144 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 115, 518, 139-144 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 115, 518, 139-144 2016/03/24 Japanese Disclose to all
岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (コンピュータシステム) 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (コンピュータシステム) 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 506, 113-118 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 506, 113-118 , 114, 506, 113-118 2015/03/06 Japanese Disclose to all
岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (ディペンダブルコンピューティング) 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (ディペンダブルコンピューティング) 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 507, 113-118 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 507, 113-118 , 114, 507, 113-118 2015/03/06 Japanese Disclose to all
岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング 研究報告システムとLSIの設計技術(SLDM), 2015, 33, 1-6 研究報告システムとLSIの設計技術(SLDM), 2015, 33, 1-6 , 2015, 33, 1-6 2015/02/27 Japanese Disclose to all
IWATA ATSUSHI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 IWATA ATSUSHI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture 同一命令セットヘテロジニアスマルチコアに適したリアルタイムシステム向けタスクマイグレーション手法 (ディペンダブルコンピューティング) -- (デザインガイア2014 : VLSI設計の新しい大地) A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture IEICE technical report. Dependable computing, 114, 329, 63-68 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114, 329, 63-68 IEICE technical report. Dependable computing, 114, 329, 63-68 2014/11/26 Japanese Disclose to all
岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture 同一命令セットヘテロジニアスマルチコアに適したリアルタイムシステム向けタスクマイグレーション手法 A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture 研究報告システムとLSIの設計技術(SLDM), 2014, 4, 1-6 研究報告システムとLSIの設計技術(SLDM), 2014, 4, 1-6 研究報告システムとLSIの設計技術(SLDM), 2014, 4, 1-6 2014/11/19 Japanese Disclose to all
東 遼平, 高瀬 英希, 高木 一義, 高木 直史 東 遼平, 高瀬 英希, 高木 一義, 高木 直史 東 遼平, 高瀬 英希, 高木 一義, 高木 直史 Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC プログラマブルSoCのためのシステム設計環境におけるフロントエンドの実装と事例評価 Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC 研究報告システムLSI設計技術(SLDM), 2014, 16, 1-6 研究報告システムLSI設計技術(SLDM), 2014, 16, 1-6 研究報告システムLSI設計技術(SLDM), 2014, 16, 1-6 2014/03/08 Japanese Disclose to all
AZUMA RYOHEI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI 東 遼平, 高瀬 英希, 高木 一義, 高木 直史 AZUMA RYOHEI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC プログラマブルSoCのためのシステム設計環境におけるフロントエンドの実装と事例評価(組込みハードウェア,組込み技術とネットワークに関するワークショップETNET2014) Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC IEICE technical report. Computer systems, 113, 497, 91-96 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 113, 497, 91-96 IEICE technical report. Computer systems, 113, 497, 91-96 2014/03/08 Japanese Disclose to all
AONO KAZUMI, IWATA ATSUSHI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI 青野 和巳, 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 AONO KAZUMI, IWATA ATSUSHI, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality 環境電力駆動組込みシステムの動作シナリオのモデル化と動作品質最大化アルゴリズム(スケジューリング・アルゴリズム,組込み技術とネットワークに関するワークショップETNET2014) An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality IEICE technical report. Dependable computing, 113, 498, 1-6 電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング, 113, 498, 1-6 IEICE technical report. Dependable computing, 113, 498, 1-6 2014/03/08 Japanese Disclose to all
東遼平, 高瀬英希, 高木一義, 高木直史 東遼平, 高瀬英希, 高木一義, 高木直史 東遼平, 高瀬英希, 高木一義, 高木直史 A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs プログラマブルSoCのためのシステム設計環境の検討とSW-HWインタフェース生成手法の実装 A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs 研究報告システムLSI設計技術(SLDM), 2014, 34, 1-6 研究報告システムLSI設計技術(SLDM), 2014, 34, 1-6 研究報告システムLSI設計技術(SLDM), 2014, 34, 1-6 2014/01/21 Japanese Disclose to all
東 遼平, 高瀬 英希, 高木 一義, 高木 直史 東 遼平, 高瀬 英希, 高木 一義, 高木 直史 東 遼平, 高瀬 英希, 高木 一義, 高木 直史 A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs プログラマブルSoCのためのシステム設計環境の検討とSW-HWインタフェース生成手法の実装(システム設計環境,FPGA応用及び一般) A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs Technical report of IEICE. VLD, 113, 416, 191-196 電子情報通信学会技術研究報告. VLD, VLSI設計技術, 113, 416, 191-196 Technical report of IEICE. VLD, 113, 416, 191-196 2014/01/21 Japanese Disclose to all
須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 Estimation for Method of Controller Implementation in High-Level Synthesis 高位合成における制御回路の構成方法の定量的評価 Estimation for Method of Controller Implementation in High-Level Synthesis 研究報告システムLSI設計技術(SLDM), 2013, 46, 1-6 研究報告システムLSI設計技術(SLDM), 2013, 46, 1-6 研究報告システムLSI設計技術(SLDM), 2013, 46, 1-6 2013/11/20 Japanese Disclose to all
SUDA AKIHIRO, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 SUDA AKIHIRO, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis 高位合成における非一様依存性を持つ入れ子ループ向けのバッファ構成手法(高位合成,デザインガイア2013-VLSI設計の新しい大地-) Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis Technical report of IEICE. VLD, 113, 320, 251-256 電子情報通信学会技術研究報告. VLD, VLSI設計技術, 113, 320, 251-256 Technical report of IEICE. VLD, 113, 320, 251-256 2013/11/20 Japanese Disclose to all
須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis 高位合成における非一様依存性を持つ入れ子ループ向けのバッファ構成手法 Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis 研究報告システムLSI設計技術(SLDM), 2013, 45, 1-6 研究報告システムLSI設計技術(SLDM), 2013, 45, 1-6 研究報告システムLSI設計技術(SLDM), 2013, 45, 1-6 2013/11/20 Japanese Disclose to all
Iwata Atsushi, Takase Hideki, Takagi Kazuyoshi, Takagi Naofumi 岩田 淳, 高瀬 英希, 高木 一義, 高木 直史 Iwata Atsushi, Takase Hideki, Takagi Kazuyoshi, Takagi Naofumi C-003 Implementations and Comparative Evaluation of DVFS algorithm on the Embedded RTOS C-003 組込みシステム向けDVFSアルゴリズムのリアルタイムOSへの実装および比較評価(C分野:ハードウェア・アーキテクチャ,一般論文) C-003 Implementations and Comparative Evaluation of DVFS algorithm on the Embedded RTOS 情報科学技術フォーラム講演論文集, 12, 1, 315-318 情報科学技術フォーラム講演論文集, 12, 1, 315-318 情報科学技術フォーラム講演論文集, 12, 1, 315-318 2013/08/20 Japanese Disclose to all
SUDA AKIHIRO, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 SUDA AKIHIRO, TAKASE HIDEKI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI Threading Method for Polyhedral Optimization in High Level Synthesis 高位合成における多面体最適化のためのスレッド構成手法(動作合成,組込み技術とネットワークに関するワークショップETNET2013) Threading Method for Polyhedral Optimization in High Level Synthesis IEICE technical report. Computer systems, 112, 481, 121-126 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 112, 481, 121-126 IEICE technical report. Computer systems, 112, 481, 121-126 2013/03/06 Japanese Disclose to all
ITOH Yuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi 伊藤 勇也, 高瀬 英希, 高木 一義, 高木 直史 ITOH Yuya, TAKASE Hideki, TAKAGI Kazuyoshi, TAKAGI Naofumi Evaluation Environment for Configuration of Floating-Point Unit Arrays 浮動小数点演算器アレイの構成のための評価環境(演算機構,組込み技術とネットワークに関するワークショップETNET2013) Evaluation Environment for Configuration of Floating-Point Unit Arrays IEICE technical report. Computer systems, 112, 481, 253-258 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 112, 481, 253-258 IEICE technical report. Computer systems, 112, 481, 253-258 2013/03/06 Japanese Disclose to all
須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 須田 瑛大, 高瀬 英希, 高木 一義, 高木 直史 Threading Method for Polyhedral Optimization in High Level Synthesis 高位合成における多面体最適化のためのスレッド構成手法 Threading Method for Polyhedral Optimization in High Level Synthesis 研究報告組込みシステム(EMB), 2013, 21, 1-6 研究報告組込みシステム(EMB), 2013, 21, 1-6 研究報告組込みシステム(EMB), 2013, 21, 1-6 2013/03/06 Japanese Disclose to all
伊藤 勇也, 高瀬 英希, 高木 一義, 高木 直史 伊藤 勇也, 高瀬 英希, 高木 一義, 高木 直史 伊藤 勇也, 高瀬 英希, 高木 一義, 高木 直史 Evaluation Environment for Configuration of Floating-Point Unit Arrays 浮動小数点演算器アレイの構成のための評価環境 Evaluation Environment for Configuration of Floating-Point Unit Arrays 研究報告組込みシステム(EMB), 2013, 43, 1-6 研究報告組込みシステム(EMB), 2013, 43, 1-6 研究報告組込みシステム(EMB), 2013, 43, 1-6 2013/03/06 Japanese Disclose to all
荒木 達真, 高瀬 英希, 高木 一義, 高木 直史 荒木 達真, 高瀬 英希, 高木 一義, 高木 直史 荒木 達真, 高瀬 英希, 高木 一義, 高木 直史 A Speculative Execution Method for Indefinite Loops in High Level Synthesis 高位合成における繰り返し回数未決定ループに対する投機実行手法 A Speculative Execution Method for Indefinite Loops in High Level Synthesis 研究報告システムLSI設計技術(SLDM), 2012, 18, 1-6 研究報告システムLSI設計技術(SLDM), 2012, 18, 1-6 研究報告システムLSI設計技術(SLDM), 2012, 18, 1-6 2012/11/19 Japanese Disclose to all
ARAKI Tatuma, TAKASE Hideki, TAKAGI Kazuyosi, TAKAGI Naohumi 荒木 達真, 高瀬 英希, 高木 一義, 高木 直史 ARAKI Tatuma, TAKASE Hideki, TAKAGI Kazuyosi, TAKAGI Naohumi A Speculative Execution Method for Indefinite Loops in High Level Synthesis 高位合成における繰り返し回数未決定ループに対する投機実行手法(動作合成(2),デザインガイア2012-VLSI設計の新しい大地-) A Speculative Execution Method for Indefinite Loops in High Level Synthesis IEICE technical report. Dependable computing, 112, 321, 99-104 電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング, 112, 321, 99-104 IEICE technical report. Dependable computing, 112, 321, 99-104 2012/11/19 Japanese Disclose to all
貝沼世樹, 島村泰浩, 宮岡史滋, 山梨裕希, 吉川信行, 藤巻朗, 高木直史, 高木一義 貝沼世樹, 島村泰浩, 宮岡史滋, 山梨裕希, 吉川信行, 藤巻朗, 高木直史, 高木一義 Nbアドバンストプロセスを用いた単一磁束量子浮動小数点演算器の設計 Nbアドバンストプロセスを用いた単一磁束量子浮動小数点演算器の設計 電子情報通信学会超伝導エレクトロニクス研究会SCE2009-19 電子情報通信学会超伝導エレクトロニクス研究会SCE2009-19 2009/10/20 Japanese Article, review, commentary, editorial, etc.(other) Disclose to all
田中雅光, 小畑幸嗣, 高木一義, 高木直史, 吉川信行 田中雅光, 小畑幸嗣, 高木一義, 高木直史, 吉川信行 再構成可能なデータパスに向けた単一磁束量浮動小数点除算器の実証 再構成可能なデータパスに向けた単一磁束量浮動小数点除算器の実証 電子情報通信学会超伝導エレクロトニクス研究会SCE2008-27 電子情報通信学会超伝導エレクロトニクス研究会SCE2008-27 2008/10 Japanese Article, review, commentary, editorial, etc.(other) Disclose to all
原浩史, 小畑幸嗣, 朴熙中, 山梨裕希, 武富一博, 吉川信行, 田中雅光, 伊藤祐喜, 藤巻朗, 高木直史, 高木一義 原浩史, 小畑幸嗣, 朴熙中, 山梨裕希, 武富一博, 吉川信行, 田中雅光, 伊藤祐喜, 藤巻朗, 高木直史, 高木一義 SFQ半精度浮動小数点乗算器の設計と試作 SFQ半精度浮動小数点乗算器の設計と試作 電子情報通信学会超伝導エレクロトニクス研究会SCE2007-32 電子情報通信学会超伝導エレクロトニクス研究会SCE2007-32 2008/01 Japanese Article, review, commentary, editorial, etc.(other) Disclose to all
N. Takagi, K.Murakami, A. Fujimaki, N. Yoshikawa, K. Inoue, H. Honda N. Takagi, K.Murakami, A. Fujimaki, N. Yoshikawa, K. Inoue, H. Honda N. Takagi, K.Murakami, A. Fujimaki, N. Yoshikawa, K. Inoue, H. Honda A Desk-Side Supercomputer with RSFQ Reconfigurable Data-Paths A Desk-Side Supercomputer with RSFQ Reconfigurable Data-Paths A Desk-Side Supercomputer with RSFQ Reconfigurable Data-Paths 日本学術振興会 超伝導エレクトロニクス第146委員会 創立25周年記念シンポジウム 日本学術振興会 超伝導エレクトロニクス第146委員会 創立25周年記念シンポジウム 日本学術振興会 超伝導エレクトロニクス第146委員会 創立25周年記念シンポジウム 2007/10 English Article, review, commentary, editorial, etc.(other) Disclose to all
高木直史, 村上和彰, 藤巻朗, 井上弘士, 本田宏明, 吉川信行 高木直史, 村上和彰, 藤巻朗, 井上弘士, 本田宏明, 吉川信行 単一磁束量子回路による再構成可能な大規模データパスをもつプロセッサ 単一磁束量子回路による再構成可能な大規模データパスをもつプロセッサ 電子情報通信学会超伝導エレクロトニクス研究会SCE2006-36、東京 電子情報通信学会超伝導エレクロトニクス研究会SCE2006-36、東京 2007/01 Japanese Article, review, commentary, editorial, etc.(other) Disclose to all
西海尚伸, 伊藤真紀, 吉川信行, 小畑幸嗣, 高木一義, 高木直史 西海尚伸, 伊藤真紀, 吉川信行, 小畑幸嗣, 高木一義, 高木直史 BDDに基づくSFQ論理回路の新しい実現方法 BDDに基づくSFQ論理回路の新しい実現方法 電子情報通信学会超伝導エレクトロニクス研究会, 27 電子情報通信学会超伝導エレクトロニクス研究会, 27 , 27 2004/10 Japanese Article, review, commentary, editorial, etc.(other) Disclose to all
N Takagi N Takagi N Takagi Multiple-valued-digit number representations in arithmetic circuit algorithms Multiple-valued-digit number representations in arithmetic circuit algorithms Multiple-valued-digit number representations in arithmetic circuit algorithms ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 224-235 ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 224-235 ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 224-235 2002 Refereed English Disclose to all

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Title language:
Conference Activities & Talks
Title Title(Japanese) Title(English) Conference Conference(Japanese) Conference(English) Promotor Promotor(Japanese) Promotor(English) Date Language Assortment Disclose
Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors The 10th Superconducting SFQ VLSI Workshop (SSV 2017) The 10th Superconducting SFQ VLSI Workshop (SSV 2017) The 10th Superconducting SFQ VLSI Workshop (SSV 2017) 2017/02/20 English Oral presentation(general) Disclose to all
Research Results of CREST-JST SFQ-RDP Project and Future Issues Research Results of CREST-JST SFQ-RDP Project and Future Issues Research Results of CREST-JST SFQ-RDP Project and Future Issues The 6th Superconducting SFQ VLSI Workshop (SSV 2013) The 6th Superconducting SFQ VLSI Workshop (SSV 2013) The 6th Superconducting SFQ VLSI Workshop (SSV 2013) 2013/11/22 English Oral presentation(invited, special) Disclose to all
An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits 24th International Symposium on Superconductivity 24th International Symposium on Superconductivity 24th International Symposium on Superconductivity 2011/10/26 English Oral presentation(invited, special) Disclose to all
Title language:
Books etc
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Publisher Publisher(Japanese) Publisher(English) Publication date Language Type Disclose
TAKAGI Naofumi, ISO Naoyuki 高木直史, 磯直行 TAKAGI Naofumi, ISO Naoyuki New Inter-University Logic Circuits 新インターユニバーシティ 論理回路 New Inter-University Logic Circuits Ohmsha オーム社 Ohmsha 2010/12 Japanese Contributor Disclose to all
TAKAGI Naofumi 高木 直史 TAKAGI Naofumi VLSI Algorithms for Arithmetic Operations 算術演算のVLSIアルゴリズム VLSI Algorithms for Arithmetic Operations Corona Publishing Co., LTD コロナ社 Corona Publishing Co., LTD 2005/03 Single Work Disclose to all
CHEN Waikai Ed, MUROGA Saburo, TAKAGI Naofumi CHEN Waikai Ed, MUROGA Saburo, TAKAGI Naofumi CHEN Waikai Ed, MUROGA Saburo, TAKAGI Naofumi The VLSI Handbook The VLSI Handbook The VLSI Handbook CRC Press (with IEEE Press) CRC Press (with IEEE Press) CRC Press (with IEEE Press) 2000 Joint Work Disclose to all
INAGAKI Yasuyoshi, TAKAGI Naofumi, HAYASHI Terumine, NAOI Tohru 稲垣康善, 高木直史, 林照峯, 直井徹 INAGAKI Yasuyoshi, TAKAGI Naofumi, HAYASHI Terumine, NAOI Tohru Inter-University Logic Circuits and Automata インターユニバーシティ 論理回路とオートマトン Inter-University Logic Circuits and Automata Ohmsha オーム社 Ohmsha 1998/01 Contributor Disclose to all
TAKAGI Naofumi 高木 直史 TAKAGI Naofumi Logic Circuits New Text 電子情報系シリーズ 論理回路 Logic Circuits Shokodo 昭晃堂 Shokodo 1997/04 Single Work Disclose to all
IKEDA Katsuo, SHIBAYAMA Kiyoshi, TAKAGI Naofumi 池田克夫, 柴山潔, 高木直史他 IKEDA Katsuo, SHIBAYAMA Kiyoshi, TAKAGI Naofumi Experiments in Information Engineering 情報工学実験 (新コンピュータサイエンス講座) Experiments in Information Engineering オーム社 オーム社 1993/03 Contributor Disclose to all
Title language:
Industrial Property Rights (Patent)
Inventor(s) Inventor(s) (Japanese) Inventor(s) (English) Title Title(Japanese) Title(English) Stage Patent number Date Disclose
並列係数ソーティング回路 並列係数ソーティング回路 Disclose to all
Arithmetic processor and multiplier using redundant signed digit arithmetic Arithmetic processor and multiplier using redundant signed digit arithmetic Disclose to all
Arithmetic processor and divider using redundant signed digit Arithmetic processor and divider using redundant signed digit Disclose to all
Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands Disclose to all
High speed multiplier utilizing signed-digit and carry-save operands High speed multiplier utilizing signed-digit and carry-save operands Disclose to all
Arithmetic processor using singed-digit representation of internal operands Arithmetic processor using singed-digit representation of internal operands Disclose to all
Arithmetic processor using signed-digit representation of external operands Arithmetic processor using signed-digit representation of external operands Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
演算処理装置 演算処理装置 Disclose to all
加算装置 加算装置 Disclose to all
Method and hardware for computing reciprocal square root and program for the same Method and hardware for computing reciprocal square root and program for the same Disclose to all
平方根の逆数計算方法、計算回路、及びプログラム 平方根の逆数計算方法、計算回路、及びプログラム Disclose to all
剰余系の計算方法及び装置並びにプログラム 剰余系の計算方法及び装置並びにプログラム Disclose to all
再構成可能データパスプロセッサ 再構成可能データパスプロセッサ Disclose to all
剰余系の計算方法及び装置 剰余系の計算方法及び装置 Disclose to all
Arithmetic processor and multiplier using redundant signed digit arithmetic Arithmetic processor and multiplier using redundant signed digit arithmetic Arithmetic processor and multiplier using redundant signed digit arithmetic Disclose to all
Arithmetic processor and divider using redundant signed digit Arithmetic processor and divider using redundant signed digit Arithmetic processor and divider using redundant signed digit Disclose to all
Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands Adder circuitry utilizing redundant signed digit operands Disclose to all
High speed multiplier utilizing signed-digit and carry-save operands High speed multiplier utilizing signed-digit and carry-save operands High speed multiplier utilizing signed-digit and carry-save operands Disclose to all
Arithmetic processor using singed-digit representation of internal operands Arithmetic processor using singed-digit representation of internal operands Arithmetic processor using singed-digit representation of internal operands Disclose to all
Arithmetic processor using signed-digit representation of external operands Arithmetic processor using signed-digit representation of external operands Arithmetic processor using signed-digit representation of external operands Disclose to all
Method and hardware for computing reciprocal square root and program for the same Method and hardware for computing reciprocal square root and program for the same Method and hardware for computing reciprocal square root and program for the same Disclose to all

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Title language:
Awards
Title(Japanese) Title(English) Organization name(Japanese) Organization name(English) Date
Best Paper Award of 7th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005) Organizing Committee of CHES2005 2005/09/
平成17年度科学技術分野の文部科学大臣表彰 研究部門 文部科学省 2005/04/
第9回 日本IBM科学賞 日本アイ・ビー・エム 1995/11/
情報処理学会 第3回(平成6年度)坂井記念特別賞 情報処理学会 1995/05/
第9回 電気通信普及財団 テレコムシステム技術賞 奨励賞 電気通信普及財団 1994/03/
電子情報通信学会 第6回(平成2年度)篠原記念学術奨励賞 電子情報通信学会 1991/03/
情報処理学会 1988年度論文賞 情報処理学会 1989/05/
電子情報通信学会 1987年度論文賞 電子情報通信学会 1988/05/
Outstanding Paper Award of IEEE International Conference on Computer Design (ICCD'84) Organizing Committee of ICCD'84 1984/11/
External funds: competitive funds and Grants-in-Aid for Scientific Research (Kakenhi)
Type Position Title(Japanese) Title(English) Period
基盤研究(B) Representative テスト容易な演算回路の自動合成に関する研究 Research on synthesis of easily-testable arithmetic circuits 2008/04/01-2011/03/31
基盤研究(B) Representative データ表現の工夫による高性能・高信頼浮動小数点演算器アレイに関する研究      Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation 2012/04/01-2015/03/31
基盤研究(B) Representative 浮動小数点関数計算のハードウェアアシストに関する研究 Research on hardware-asist for computation of floating-point functions 2016/04/01-2020/03/31
基盤研究(B) Representative 浮動小数点関数計算のハードウェアアシストに関する研究 (平成29年度分) 2017/04/01-2018/03/31
基盤研究(B) Representative 浮動小数点関数計算のハードウェアアシストに関する研究 (平成30年度分) 2018/04/01-2019/03/31
基盤研究(B) Representative 浮動小数点関数計算のハードウェアアシストに関する研究 (2019年度分) 2019/04/01-2020/03/31
External funds: other than those above
System Main person Title(Japanese) Title(English) Period
JST-CREST 高木直史 単一磁束量子回路による再構成可能な低電力高性能プロセッサ/単一磁束量子論理回路設計及び設計支援技術の開発 Low-power, high-performance, reconfigurable processor using single-flux-quantum circuits / Development of logic design method and design autmation technologies of single-flax-quantum logic circuits 2006/10/-2013/03/31
JST-ALCA 高木直史 低エネルギー情報ネットワーク用光・磁気・超伝道融合システム/超伝導回路設計用CADの開発 Superconductor Electronic System Combined with Optics and Spintronics / Development of CAD for Superconductive Digital Circuits 2011/10/01-2017/03/31
Teaching subject(s)
Name(Japanese) Name(English) Term Department Period
Advanced Study in CCE II 通年 情報学研究科 2011/04-2012/03
通信情報システム特別研究1 通年 情報学研究科 2011/04-2012/03
通信情報システム特別研究2 通年 情報学研究科 2011/04-2012/03
Advanced Study in CCE I 通年 情報学研究科 2011/04-2012/03
計算機アーキテクチャ1(計算機) 後期 工学部 2011/04-2012/03
計算機アーキテクチャ2(計算機) 前期 工学部 2011/04-2012/03
論理回路(計算機) 前期 工学部 2011/04-2012/03
情報と職業 前期 工学部 2011/04-2012/03
特別研究1(16年以降入学者)(計算機) 前期集中 工学部 2011/04-2012/03
特別研究1(16年以降入学者)(計算機) 後期集中 工学部 2011/04-2012/03
特別研究2(16年以降入学者)(計算機) 前期集中 工学部 2011/04-2012/03
特別研究2(16年以降入学者)(計算機) 後期集中 工学部 2011/04-2012/03
特別研究1(15年以前入学者)(計算機) 前期集中 工学部 2011/04-2012/03
特別研究1(15年以前入学者)(計算機) 後期集中 工学部 2011/04-2012/03
特別研究2(15年以前入学者)(計算機) 前期集中 工学部 2011/04-2012/03
特別研究2(15年以前入学者)(計算機) 後期集中 工学部 2011/04-2012/03
並列計算機アーキテクチャ 前期 情報学研究科 2011/04-2012/03
ハードウェアアリゴリズム 後期 情報学研究科 2011/04-2012/03
ハードウェアアリゴリズム Hardware Algorithm 後期 情報学研究科 2012/04-2013/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2012/04-2013/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2012/04-2013/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2012/04-2013/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2012/04-2013/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2012/04-2013/03
論理回路 Logic Circuits 前期 工学部 2012/04-2013/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2012/04-2013/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2012/04-2013/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2013/04-2014/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2013/04-2014/03
論理回路 Logic Circuits 前期 工学部 2013/04-2014/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2013/04-2014/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2013/04-2014/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2013/04-2014/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2013/04-2014/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2014/04-2015/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2014/04-2015/03
論理回路 Logic Circuits 前期 工学部 2014/04-2015/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2014/04-2015/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04-2015/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04-2015/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2014/04-2015/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2014/04-2015/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2014/04-2015/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2014/04-2015/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2014/04-2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04-2015/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04-2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04-2016/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04-2016/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2015/04-2016/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2015/04-2016/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2015/04-2016/03
計算機アーキテクチャ1 Computer Architecture 1 後期 工学部 2015/04-2016/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2015/04-2016/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2015/04-2016/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2015/04-2016/03
論理回路 Logic Circuits 前期 工学部 2015/04-2016/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2015/04-2016/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04-2016/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04-2016/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04-2017/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04-2017/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2016/04-2017/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2016/04-2017/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2016/04-2017/03
計算機アーキテクチャ2 Computer Architecture 2 前期 工学部 2016/04-2017/03
計算機の構成 Computer organization 後期 工学部 2016/04-2017/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2016/04-2017/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2016/04-2017/03
論理システム Logical Systems 前期 工学部 2016/04-2017/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2016/04-2017/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 後期集中 情報学研究科 2016/04-2017/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04-2017/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04-2017/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04-2018/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04-2018/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2017/04-2018/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2017/04-2018/03
コンピュータ工学特別セミナー Seminar on Computer Engineering, Advanced 通年 情報学研究科 2017/04-2018/03
計算機の構成 Computer organization 後期 工学部 2017/04-2018/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2017/04-2018/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2017/04-2018/03
論理システム Logical Systems 前期 工学部 2017/04-2018/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2017/04-2018/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 前期集中 情報学研究科 2017/04-2018/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04-2018/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04-2018/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年集中 情報学研究科 2018/04-2019/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2018/04-2019/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2018/04-2019/03
情報と職業 Information and Business 前期 工学部 2018/04-2019/03
特別研究1 Graduation Thesis 1 前期集中 工学部 2018/04-2019/03
特別研究1 Graduation Thesis 1 後期集中 工学部 2018/04-2019/03
特別研究2 Graduation Thesis 2 前期集中 工学部 2018/04-2019/03
特別研究2 Graduation Thesis 2 後期集中 工学部 2018/04-2019/03
計算機の構成 Computer organization 後期 工学部 2018/04-2019/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2018/04-2019/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2018/04-2019/03
論理システム Logical Systems 前期 工学部 2018/04-2019/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2019/04-2020/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2019/04-2020/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2019/04-2020/03
計算機の構成 Computer organization 後期 工学部 2019/04-2020/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2019/04-2020/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2019/04-2020/03
論理システム Logical Systems 前期 工学部 2019/04-2020/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2020/04-2021/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2020/04-2021/03
計算機の構成 Computer organization 後期 工学部 2020/04-2021/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2020/04-2021/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2020/04-2021/03
論理システム(計算機) Logical Systems 前期 工学部 2020/04-2021/03
ハードウェアアルゴリズム Hardware Algorithm 後期 情報学研究科 2021/04-2022/03
並列計算機アーキテクチャ Parallel Computer Architecture 前期 情報学研究科 2021/04-2022/03
計算機の構成 Computer organization 後期 工学部 2021/04-2022/03
計算機科学概論 Introduction to Computer Science 前期 全学共通科目 2021/04-2022/03
計算機科学概論 Introduction to Computer Science 前期 工学部 2021/04-2022/03
論理システム(計算機) Logical Systems 前期 工学部 2021/04-2022/03

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School management (title, position)
Title Period
教育用計算機専門委員会 委員 2011/07/01-2012/03/31
京都大学情報環境整備委員会 委員 2014/10/01-2015/03/31
教育用計算機専門委員会 委員長 2014/10/01-
京都大学情報環境整備委員会 委員 2015/04/01-2016/09/30
情報環境機構 副機構長 2014/10/01-
京都大学情報環境整備委員会 委員 2016/10/01-2018/09/30
京都大学情報環境整備委員会 委員 2020/04/01-2023/03/31
Faculty management (title, position)
Title Period
教務委員会委員 2011/04/01-2012/03/31
専攻長会議 2012/04/01-2013/03/31
制規委員会委員 2012/04/01-2013/03/31
情報セキュリティ委員会委員 2012/04/01-2013/03/31
教務委員会委員 2013/04/01-2014/03/31
財務委員会委員長 2014/04/01-2017/03/31
財務委員会委員 2017/04/01-2018/03/31
企画委員会委員 2018/04/01-2019/03/33
情報学科長 2018/04/01-2019/03/31
企画委員会委員 2019/04/01-2020/03/31
工学研究科運営会議 学生・教育部門 教育担当 2018/04/01-2021/03/31
工学部新工学教育実施専門委員会 委員 2019/04/01-2021/03/31
教務委員会委員 2020/04/01-2021/03/31
制規委員会委員 2021/04/01-2022/03/31
専攻長 2021/04/01-2022/03/31
情報セキュリティ委員会委員 2021/04/01-2022/03/31
情報環境機構運営委員会委員 2020/04/01-2022/03/31
情報環境機構管理委員会委員 2020/04/01-2022/03/31
情報環境機構協議会委員 2020/04/01-2022/03/31
情報環境機構評価委員会委員 2020/04/01-2022/03/31
情報環境機構教育用計算機専門委員会委員長 2020/04/01-2022/03/31

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Other activities (awards)
Award name Organization name Date
Meritorious Service Certificate IEEE Computer Society 2014/04/ 2014/04/
Service Award ACM 2017/04/
功労賞 電子情報通信学会 基礎・境界ソサイエティ 2017/09/