小野寺 秀俊

Last Update: 2019/09/10 18:13:37

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Name(Kanji/Kana/Abecedarium Latinum)
小野寺 秀俊/オノデラ ヒデトシ/Onodera, Hidetoshi
Primary Affiliation(Org1/Job title)
Graduate Schools Informatics/Professor
Faculty
Org1 Job title
工学部
Contact Address
Type Address(Japanese) Address(English)
Office 606-8501 京都市左京区吉田本町 Sakyo-ku, Kyoto 606-8501
Academic Organizations You are Affiliated to in Japan
Organization name(Japanese) Organization name(English)
電子情報通信学会 IEICE
情報処理学会 IPSJ
Academic Organizations Overaseas You are Affiliated to
Organization name Country
IEEE USA
ACM USA
Academic Degree
Field(Japanese) Field(English) University(Japanese) University(English) Method
工学修士 京都大学
工学博士 京都大学
Graduate School
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(Japanese) Major(English) Degree
京都大学 大学院工学研究科修士課程電子工学専攻 修了
京都大学 大学院工学研究科博士後期課程電子工学専攻 修了
Undergraduate School / Major(s)
University(Japanese) University(English) Faculty(Japanese) Faculty(English) Major(s)(Japanese) Major(s)(English) Degree
京都大学 工学部電子工学科 卒業
Personal Profile
(Japanese)
集積回路の設計技術に取り組んでいる。特に、回路設計やレイアウト設計などの物理設計を対象として、製造を容易にするための設計技術、低消費電力設計技術、信頼性を高める設計技術に取り組んでいる。ディジタル回路とともに、RF/アナログ回路も研究対象としている。チップ試作に利用可能なスタンダードセルライブラリを開発し、日本全国の大学に 提供している。近年は、ディペンダブル集積回路の設計技術にも取り組んでいる。
(English)
Design technologies for integrated circuits are major research focuses. Research subjects include design for manufacturability enhancement, design for low-power dissipation, and design for reliability enhancement, at the physical design level. RF/analog circuits as well as digital circuits are being studied. A standard-cell library that can be used for chip fabrication has been developed and released for public use among Japanese universities. Recent subjects include deign methods for dependable VLSIs.
Personal Website(s) (URL(s))
URL
http://www-lab13.kuee.kyoto-u.ac.jp/~onodera
ORCID ID
https://orcid.org/0000-0001-5198-0668
researchmap URL
https://researchmap.jp/read0012717
Research Topics
(Japanese)
集積回路設計技術、低消費電力化設計技術、製造容易化設計技術、アナログ/RF回路設計技術、ディペンダブルLSI設計技術
(English)
Design Technology for Integrated Circuits, Low power design method, Design for manufacturability, Analog/RF LSI, Dependable VLSI,
Overview of the research
(Japanese)
集積回路の設計技術に取り組んでいる。特に、回路設計やレイアウト設計などの物理設計を対象として、製造を容易にするための設計技術、低消費電力設計技術、信頼性を高める設計技術に取り組んでいる。ディジタル回路とともに、RF/アナログ回路も研究対象としている。チップ試作に利用可能なスタンダードセルライブラリを開発し、日本全国の大学に提供している。近年は、ディペンダブル集積回路の設計技術にも取り組んでいる。
(English)
Design technologies for integrated circuits are major research focuses. Research subjects include design for manufacturability enhancement, design for low-power dissipation, and design for reliability enhancement, at the physical design level. RF/analog circuits as well as digital circuits are being studied. A standard-cell library that can be used for chip fabrication has been developed and released for public use among Japanese universities. Recent subjects include deign methods for dependable VLSIs.
Fields of research (key words)
Key words(Japanese) Key words(English)
集積回路工学 Integrated Circuits Technology
低消費電力化設計技術 Low Power Design
製造容易化設計技術 Design for Manufacturability
Published Papers
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiroyuki Ochi, Hidetoshi Onodera, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, and Munehiro Tada Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiroyuki Ochi, Hidetoshi Onodera, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, and Munehiro Tada Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiroyuki Ochi, Hidetoshi Onodera, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, and Munehiro Tada Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA IEEE Trans. on Electron Devices, 66, 8, 3331-3336 IEEE Trans. on Electron Devices, 66, 8, 3331-3336 IEEE Trans. on Electron Devices, 66, 8, 3331-3336 2019/08 Refereed English Research paper(scientific journal) Disclose to all
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Design Method of a Cell-Based Amplifier for Body Bias Generation A Design Method of a Cell-Based Amplifier for Body Bias Generation A Design Method of a Cell-Based Amplifier for Body Bias Generation IEICE Transactions on IEICE Transactions on Electronics, E102-C, 7, 565-572 IEICE Transactions on IEICE Transactions on Electronics, E102-C, 7, 565-572 IEICE Transactions on IEICE Transactions on Electronics, E102-C, 7, 565-572 2019/07 Refereed English Research paper(scientific journal) Disclose to all
Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity IEICE Transaction on Electronics, E102-C, 7, 573-579 IEICE Transaction on Electronics, E102-C, 7, 573-579 IEICE Transaction on Electronics, E102-C, 7, 573-579 2019/07 Refereed English Research paper(scientific journal) Disclose to all
A.K.M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6 2019/04 Refereed English Research paper(international conference proceedings) Disclose to all
塩見準,石原亨,小野寺秀俊 塩見準,石原亨,小野寺秀俊 リアルタイム電圧最適化によるマルチタスク処理の消費エネルギー最小化 リアルタイム電圧最適化によるマルチタスク処理の消費エネルギー最小化 ETNET2019 ETNET2019 2019/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation IPSJ Transactions on System LSI Design Methodology, 12, 2-12 IPSJ Transactions on System LSI Design Methodology, 12, 2-12 IPSJ Transactions on System LSI Design Methodology, 12, 2-12 2019/02 Refereed English Research paper(scientific journal) Disclose to all
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi 松尾亮祐、塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也 Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi Methods for Reducing Power and Area of BDD-based Optical Logic Circuits BDDに基づく光論理回路の素子数削減と消費電力低減 Methods for Reducing Power and Area of BDD-based Optical Logic Circuits 信学技報VLD2018-116, 139-144 信学技報VLD2018-116, 139-144 , 139-144 2019/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing Proceedings of the 24th Asia and South Pacific Design Automation Conference Proceedings of the 24th Asia and South Pacific Design Automation Conference Proceedings of the 24th Asia and South Pacific Design Automation Conference 2019/01 Refereed English Research paper(international conference proceedings) Disclose to all
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture IEEE Embedded Systems Letters, 10, 4, 119-122 IEEE Embedded Systems Letters, 10, 4, 119-122 IEEE Embedded Systems Letters, 10, 4, 119-122 2018/12 Refereed English Research paper(scientific journal) Disclose to all
Akitaka Hiratsuka, Akira Tsuchiya, Kcnji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera Akitaka Hiratsuka, Akira Tsuchiya, Kcnji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 69-72 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 69-72 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 69-72 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD ’18) IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD ’18) IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD ’18) 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics 2018 IEEE International Conference on Rebooting Computing (ICRC), 43-50 2018 IEEE International Conference on Rebooting Computing (ICRC), 43-50 2018 IEEE International Conference on Rebooting Computing (ICRC), 43-50 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing 2018 IEEE International Conference on Rebooting Computing (ICRC), 62-67 2018 IEEE International Conference on Rebooting Computing (ICRC), 62-67 2018 IEEE International Conference on Rebooting Computing (ICRC), 62-67 2018/11 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi A Light Speed Optical Approximate Parallel Multiplier and Its Applications A Light Speed Optical Approximate Parallel Multiplier and Its Applications A Light Speed Optical Approximate Parallel Multiplier and Its Applications PHOTONICS: Photonics-Optics Technology Oriented Networking, Information, and Computing Systems PHOTONICS: Photonics-Optics Technology Oriented Networking, Information, and Computing Systems PHOTONICS: Photonics-Optics Technology Oriented Networking, Information, and Computing Systems 2018/10 Refereed English Research paper(research society, symposium materials, etc.) Disclose to all
Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization The 31st IEEE International System-on-Chip Conference, 112-117 The 31st IEEE International System-on-Chip Conference, 112-117 The 31st IEEE International System-on-Chip Conference, 112-117 2018/09 Refereed English Research paper(international conference proceedings) Disclose to all
松尾亮祐、塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也 松尾亮祐、塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也 波長多重を用いた二分決定グラフに基づく光論理回路の合成 波長多重を用いた二分決定グラフに基づく光論理回路の合成 DAシンポジウム2018, 51-56 DAシンポジウム2018, 51-56 , 51-56 2018/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也 塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也 集積ナノフォトニクスに基づく近似二進対数を用いた低レイテンシ光並列乗算器 集積ナノフォトニクスに基づく近似二進対数を用いた低レイテンシ光並列乗算器 DAシンポジウム2018, 57-62 DAシンポジウム2018, 57-62 , 57-62 2018/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
A.K.M. Mahfuzul Islam, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Hidetoshi Onodera Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 140-146 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 140-146 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 140-146 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera Independent N-well and P-well Biasing for Minimum Leakage Energy Operation Independent N-well and P-well Biasing for Minimum Leakage Energy Operation Independent N-well and P-well Biasing for Minimum Leakage Energy Operation The International Symposium on On-Line Testing and Robust System Design (IOLTS), 177-182 The International Symposium on On-Line Testing and Robust System Design (IOLTS), 177-182 The International Symposium on On-Line Testing and Robust System Design (IOLTS), 177-182 2018/07 Refereed English Research paper(international conference proceedings) Disclose to all
Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 237-242 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 237-242 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 237-242 2018/07 Refereed Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera Minimum Energy Point Tracking with All-Digital On-Chip Sensors Minimum Energy Point Tracking with All-Digital On-Chip Sensors Minimum Energy Point Tracking with All-Digital On-Chip Sensors ASP Journal of Low Power Electronics, 14, 2 ASP Journal of Low Power Electronics, 14, 2 ASP Journal of Low Power Electronics, 14, 2 2018/06 Refereed English Research paper(scientific journal) Disclose to all
Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018), JW2A.50 OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018), JW2A.50 OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018), JW2A.50 2018/05 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya, A. Hiratsuka, T. Inoue, K. Kishine, H. Onodera A. Tsuchiya, A. Hiratsuka, T. Inoue, K. Kishine, H. Onodera A. Tsuchiya, A. Hiratsuka, T. Inoue, K. Kishine, H. Onodera Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net 22nd IEEE Workshop on Signal and Power Integrity, 1-4 22nd IEEE Workshop on Signal and Power Integrity, 1-4 22nd IEEE Workshop on Signal and Power Integrity, 1-4 2018/05 Refereed English Research paper(international conference proceedings) Disclose to all
福田 展和,塩見 準,石原 亨,小野寺 秀俊 福田 展和,塩見 準,石原 亨,小野寺 秀俊 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法 第184回システムとLSIの設計技術研究発表会, 2018-SLDM-184, 5, 1-6 第184回システムとLSIの設計技術研究発表会, 2018-SLDM-184, 5, 1-6 , 2018-SLDM-184, 5, 1-6 2018/05 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata and Masaya Notomi Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata and Masaya Notomi An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 100-105 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 100-105 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 100-105 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 56-61 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 56-61 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 56-61 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo, Kenta Takata, Masaya Notomi Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo, Kenta Takata, Masaya Notomi Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo, Kenta Takata, Masaya Notomi A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 320-325 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 320-325 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 320-325 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Shinichi Nishizawa, Hidetoshi Onodera Shinichi Nishizawa, Hidetoshi Onodera Process Variation Aware D-Flip-Flop Design using Regression Analysis Process Variation Aware D-Flip-Flop Design using Regression Analysis Process Variation Aware D-Flip-Flop Design using Regression Analysis International Symposium on Quality Electronic Design (ISQED), 88-93 International Symposium on Quality Electronic Design (ISQED), 88-93 International Symposium on Quality Electronic Design (ISQED), 88-93 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Yuta Nagaoka, Tohru Ishihara, and Hidetoshi Onodera Yuta Nagaoka, Tohru Ishihara, and Hidetoshi Onodera Yuta Nagaoka, Tohru Ishihara, and Hidetoshi Onodera Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 290-295 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 290-295 The 21st Workshop on Synthesis And System Integration of Mixed Information technologies, 290-295 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
塩見準,石原亨,小野寺秀俊 塩見準,石原亨,小野寺秀俊 選択的活性化によるスタンダードセルメモリの低消費エネルギー化 選択的活性化によるスタンダードセルメモリの低消費エネルギー化 電子情報通信学会技術研究報告, 117, 455, 211-216 電子情報通信学会技術研究報告, 117, 455, 211-216 , 117, 455, 211-216 2018/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Japanese Journal of Applied Physics, 57, 45, 04FF09-1-04FF09-6 Japanese Journal of Applied Physics, 57, 45, 04FF09-1-04FF09-6 Japanese Journal of Applied Physics, 57, 45, 04FF09-1-04FF09-6 2018/03 Refereed English Research paper(scientific journal) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 45-50 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 45-50 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 45-50 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors International Conference on Microelectronic Test Structures (ICMTS), 128-133 International Conference on Microelectronic Test Structures (ICMTS), 128-133 International Conference on Microelectronic Test Structures (ICMTS), 128-133 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Tadashi Kishimoto, Tohru Ishihara and Hidetoshi Onodera Tadashi Kishimoto, Tohru Ishihara and Hidetoshi Onodera On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation International Conference on Microelectronic Test Structures (ICMTS), 111-116 International Conference on Microelectronic Test Structures (ICMTS), 111-116 International Conference on Microelectronic Test Structures (ICMTS), 111-116 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, Masashi Oka, and Hidetoshi Onodera A.K.M. Mahfuzul Islam, Masashi Oka, and Hidetoshi Onodera Measurement of Temperature Effect on Random Telegraph Noise Induced Delay Flucutuation Measurement of Temperature Effect on Random Telegraph Noise Induced Delay Flucutuation Measurement of Temperature Effect on Random Telegraph Noise Induced Delay Flucutuation Proceedings of the 2018 International Conference on Microelectronic Test Sturucure, 210-215 Proceedings of the 2018 International Conference on Microelectronic Test Sturucure, 210-215 Proceedings of the 2018 International Conference on Microelectronic Test Sturucure, 210-215 2018/03 Refereed English Research paper(international conference proceedings) Disclose to all
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2776-2784 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2776-2784 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2776-2784 2017/12 Refereed English Research paper(scientific journal) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2764-2775 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2764-2775 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A, 12, 2764-2775 2017/12 Refereed English Research paper(scientific journal) Disclose to all
Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator 2017 International Conference on Solid State Devices and Materials, 345-346 2017 International Conference on Solid State Devices and Materials, 345-346 2017 International Conference on Solid State Devices and Materials, 345-346 2017/09 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Hidetoshi Onodera Effect of supply voltage on random telegraph noise of transistors under switching condition Effect of supply voltage on random telegraph noise of transistors under switching condition Effect of supply voltage on random telegraph noise of transistors under switching condition Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on, 1-8 Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on, 1-8 Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on, 1-8 2017/09 Refereed English Research paper(international conference proceedings) Disclose to all
長岡 悠太,石原 亨,小野寺 秀俊 長岡 悠太,石原 亨,小野寺 秀俊 クロスバ構造を利用した論理関数参照型ルックアップテーブルの回路構成法 クロスバ構造を利用した論理関数参照型ルックアップテーブルの回路構成法 DAシンポジウム2017, 216-221 DAシンポジウム2017, 216-221 , 216-221 2017/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岡村 陽介,石原 亨,小野寺 秀俊 岡村 陽介,石原 亨,小野寺 秀俊 リークエネルギーを最小化するP/N基板電圧の設定手法 リークエネルギーを最小化するP/N基板電圧の設定手法 DAシンポジウム2017, 157-162 DAシンポジウム2017, 157-162 , 157-162 2017/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs 2017 IEEE International SoC Conference, 56-61 2017 IEEE International SoC Conference, 56-61 2017 IEEE International SoC Conference, 56-61 2017/09 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement IEEE Transactions on Semiconductor Manufacturing, 30, 3, 216-226 IEEE Transactions on Semiconductor Manufacturing, 30, 3, 216-226 IEEE Transactions on Semiconductor Manufacturing, 30, 3, 216-226 2017/08 Refereed English Research paper(scientific journal) Disclose to all
樋口 達大,石原 亨,小野寺 秀俊 樋口 達大,石原 亨,小野寺 秀俊 ビアスイッチFPGAの性能予測モデル ビアスイッチFPGAの性能予測モデル DAシンポジウム2017, 9-14 DAシンポジウム2017, 9-14 , 9-14 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
江川 巧,石原 亨,小野寺 秀俊,新家 昭彦,北 翔太,野崎 謙悟,高田 健太,納富 雅也 江川 巧,石原 亨,小野寺 秀俊,新家 昭彦,北 翔太,野崎 謙悟,高田 健太,納富 雅也 ナノフォトニクスを用いた高速多入力論理演算の実現法 ナノフォトニクスを用いた高速多入力論理演算の実現法 DAシンポジウム2017, 45-50 DAシンポジウム2017, 45-50 , 45-50 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
今井 悠貴,石原 亨,小野寺 秀俊,新家 昭彦,北 翔太,野崎 謙悟,高田 健太,納富 雅也 今井 悠貴,石原 亨,小野寺 秀俊,新家 昭彦,北 翔太,野崎 謙悟,高田 健太,納富 雅也 集積ナノフォトニクスに基づく光アナログ加算手法と光並列乗算器への適用 集積ナノフォトニクスに基づく光アナログ加算手法と光並列乗算器への適用 DAシンポジウム2017, 51-56 DAシンポジウム2017, 51-56 , 51-56 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岸本 真,石原 亨,小野寺 秀俊 岸本 真,石原 亨,小野寺 秀俊 トポロジー可変リングオシレータを用いた電圧感度の小さい動作温度モニタ トポロジー可変リングオシレータを用いた電圧感度の小さい動作温度モニタ DAシンポジウム2017, 85-90 DAシンポジウム2017, 85-90 , 85-90 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
保木本 修,塩見 準,石原 亨,小野寺 秀俊 保木本 修,塩見 準,石原 亨,小野寺 秀俊 最小エネルギー動作点追跡アルゴリズムの実チップ評価 最小エネルギー動作点追跡アルゴリズムの実チップ評価 DAシンポジウム2017, 145-150 DAシンポジウム2017, 145-150 , 145-150 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
塩見 準,石原 亨,小野寺 秀俊 塩見 準,石原 亨,小野寺 秀俊 アクセス頻度に応じた電圧調節によるオンチップメモリの消費エネルギー最小化 アクセス頻度に応じた電圧調節によるオンチップメモリの消費エネルギー最小化 DAシンポジウム2017, 151-156 DAシンポジウム2017, 151-156 , 151-156 2017/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Integration, the VLSI Journal Integration, the VLSI Journal Integration, the VLSI Journal 2017/07 Refereed English Research paper(scientific journal) Disclose to all
Tadashi Kishimoto, Tohru Ishihara, ONODERA Hidetoshi Tadashi Kishimoto, Tohru Ishihara, ONODERA Hidetoshi On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator 2017 International Symposium on VLSI Design, Automation and Test, 1-4 2017 International Symposium on VLSI Design, Automation and Test, 1-4 2017 International Symposium on VLSI Design, Automation and Test, 1-4 2017/04 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera The Impact of RTN-induced Temporal Performance Fluctuation against Static Performance Variation The Impact of RTN-induced Temporal Performance Fluctuation against Static Performance Variation The Impact of RTN-induced Temporal Performance Fluctuation against Static Performance Variation Proceedings of the 2017 IEEE Electron Devices Technology and Manufacturing, 31-32 Proceedings of the 2017 IEEE Electron Devices Technology and Manufacturing, 31-32 Proceedings of the 2017 IEEE Electron Devices Technology and Manufacturing, 31-32 2017/03 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators Proceedings of the 2017 IEEE International Conference on Microelectronic Test Structures, 159-164 Proceedings of the 2017 IEEE International Conference on Microelectronic Test Structures, 159-164 Proceedings of the 2017 IEEE International Conference on Microelectronic Test Structures, 159-164 2017/03 Refereed English Research paper(international conference proceedings) Disclose to all
伴野直樹、多田宗弘、岡本浩一郎、井口憲幸、坂本利司、波田博光、越智裕之、小野寺秀俊、橋本昌宜、杉林直彦 伴野直樹、多田宗弘、岡本浩一郎、井口憲幸、坂本利司、波田博光、越智裕之、小野寺秀俊、橋本昌宜、杉林直彦 低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 信学技報, 116, 450, SDM2016-144 信学技報, 116, 450, SDM2016-144 , 116, 450, SDM2016-144 2017/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、中尾拓也、中野慎介、野河正史、野坂秀之、小野寺秀俊 土谷亮、中尾拓也、中野慎介、野河正史、野坂秀之、小野寺秀俊 高密度・高速光インターコネクトに向けたCMOS光受信回路の開発 高密度・高速光インターコネクトに向けたCMOS光受信回路の開発 信学技報, 116, 467, CAS2016-124 信学技報, 116, 467, CAS2016-124 , 116, 467, CAS2016-124 2017/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic 2016 International Electron Devices Meeting, 16.4.1-16.4.4 2016 International Electron Devices Meeting, 16.4.1-16.4.4 2016 International Electron Devices Meeting, 16.4.1-16.4.4 2016/12 Refereed English Research paper(international conference proceedings) Disclose to all
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Analytical Stability Modeling for CMOS Latches in Low Voltage Operation IEICE Transactions on Fundamentals, E99-A, 12, 2463-2472 IEICE Transactions on Fundamentals, E99-A, 12, 2463-2472 IEICE Transactions on Fundamentals, E99-A, 12, 2463-2472 2016/12 Refereed English Research paper(scientific journal) Disclose to all
H-Y Su, B-S Wang, S-Y Hsieh, Y-L L,\i, I-H Wu, C-C Wu, W-C Shih, Hidetoshi Onodera, Masanori Hashimoto H-Y Su, B-S Wang, S-Y Hsieh, Y-L L,\i, I-H Wu, C-C Wu, W-C Shih, Hidetoshi Onodera, Masanori Hashimoto Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 129-134 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 129-134 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 129-134 2016/10 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 36-41 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 36-41 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 36-41 2016/10 Refereed English Research paper(international conference proceedings) Disclose to all
Kei Yoshizawa, Tohru Ishihara Hidetoshi Onodera Kei Yoshizawa, Tohru Ishihara Hidetoshi Onodera Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 329-334 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 329-334 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 329-334 2016/10 Refereed English Research paper(international conference proceedings) Disclose to all
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera Minimum Energy Point Tracking under a Wide Range of PVT Conditions Minimum Energy Point Tracking under a Wide Range of PVT Conditions Minimum Energy Point Tracking under a Wide Range of PVT Conditions , 323-328 , 323-328 , 323-328 2016/10 Refereed English Research paper(international conference proceedings) Disclose to all
Tadashi Kishimoto, Hidetoshi Onodera Tadashi Kishimoto, Hidetoshi Onodera On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 274-279 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 274-279 The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), 274-279 2016/10 Refereed English Research paper(international conference proceedings) Disclose to all
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing IEEE International System-on-Chip Conference, 1-6 IEEE International System-on-Chip Conference, 1-6 IEEE International System-on-Chip Conference, 1-6 2016/09 Refereed English Research paper(international conference proceedings) Disclose to all
Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Pieter Weckx, Ben Kaczer, Takashi Matsumoto, and Hidetoshi Onodera Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Pieter Weckx, Ben Kaczer, Takashi Matsumoto, and Hidetoshi Onodera Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 327-330 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 327-330 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 327-330 2016/09 Refereed English Research paper(international conference proceedings) Disclose to all
中井辰哉、業天英範、イスラム・マーフズル、小野寺秀俊 中井辰哉、業天英範、イスラム・マーフズル、小野寺秀俊 リングオシレータを用いたランダムテレグラフノイズの統計解析 リングオシレータを用いたランダムテレグラフノイズの統計解析 情報処理学会DAシンポジウム2016論文集, 187-192 情報処理学会DAシンポジウム2016論文集, 187-192 , 187-192 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2016 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2016 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2016 2016/09 Refereed English Research paper(international conference proceedings) Disclose to all
岸本真、石原亨、小野寺秀俊 岸本真、石原亨、小野寺秀俊 回路トポロジー可変なリングオシレータを用いたプロセス変動量と動作温度の推定方法 回路トポロジー可変なリングオシレータを用いたプロセス変動量と動作温度の推定方法 情報処理学会DAシンポジウム2016論文集, 175-180 情報処理学会DAシンポジウム2016論文集, 175-180 , 175-180 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
保木本修、石原亨、小野寺秀俊 保木本修、石原亨、小野寺秀俊 プロセッサにおける電源電圧と基板電圧の同時調節によるエネルギー最小点追跡手法 プロセッサにおける電源電圧と基板電圧の同時調節によるエネルギー最小点追跡手法 情報処理学会DAシンポジウム2016論文集, 169-174 情報処理学会DAシンポジウム2016論文集, 169-174 , 169-174 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
吉澤慶、石原亨、小野寺秀俊 吉澤慶、石原亨、小野寺秀俊 組み込みアプリケーションにおける汎用プロセッサと専用ハードウェアの性能解析-消費エネルギーと処理速度および回路規模の定量的評価 組み込みアプリケーションにおける汎用プロセッサと専用ハードウェアの性能解析-消費エネルギーと処理速度および回路規模の定量的評価 情報処理学会DAシンポジウム2016論文集, 103-108 情報処理学会DAシンポジウム2016論文集, 103-108 , 103-108 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
長岡悠太、石原亨、小野寺秀俊 長岡悠太、石原亨、小野寺秀俊 低電圧動作に適したマルチプレクサツリー構成法 低電圧動作に適したマルチプレクサツリー構成法 情報処理学会DAシンポジウム2016論文集, 97-102 情報処理学会DAシンポジウム2016論文集, 97-102 , 97-102 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
塩見準、石原亨、小野寺秀俊 塩見準、石原亨、小野寺秀俊 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ 情報処理学会DAシンポジウム2016論文集, 91-96 情報処理学会DAシンポジウム2016論文集, 91-96 , 91-96 2016/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), 272-275 Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), 272-275 Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL 2016), 272-275 2016/08 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Sato and Hidetoshi Onodera Takashi Sato and Hidetoshi Onodera Circuit Aging - Measurement Techniques Circuit Aging - Measurement Techniques Circuit Aging - Measurement Techniques IEEE International Reliability Physics Symposium, Monday Tutorial, TU2-6 IEEE International Reliability Physics Symposium, Monday Tutorial, TU2-6 IEEE International Reliability Physics Symposium, Monday Tutorial, TU2-6 2016/04 English Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 IoT時代の設計課題 IoT時代の設計課題 信学技報, 115, 477, ICD2015-129 信学技報, 115, 477, ICD2015-129 , 115, 477, ICD2015-129 2016/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤原将倫、土谷亮、中野慎介、野河正史、野坂秀之、小野寺秀俊 藤原将倫、土谷亮、中野慎介、野河正史、野坂秀之、小野寺秀俊 インバータ増幅段によるレギュレーティッドカスコード型トランスインピーダンスアンプの広帯域化 インバータ増幅段によるレギュレーティッドカスコード型トランスインピーダンスアンプの広帯域化 電子情報通信学会技術報告, 477, 229-233 電子情報通信学会技術報告, 477, 229-233 , 477, 229-233 2016/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
A.K.M. Mahfuzul Islam, Tatsuya Nakai, and Hidetoshi Onodera A.K.M. Mahfuzul Islam, Tatsuya Nakai, and Hidetoshi Onodera Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Variation Measurement Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Variation Measurement Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Variation Measurement 2016 International Conference on Microelectronic Test Structures (ICMTS), 82-87 2016 International Conference on Microelectronic Test Structures (ICMTS), 82-87 2016 International Conference on Microelectronic Test Structures (ICMTS), 82-87 2016/03 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design 17th International Symposium on Quality Electronic Design (ISQED), 18-23 17th International Symposium on Quality Electronic Design (ISQED), 18-23 17th International Symposium on Quality Electronic Design (ISQED), 18-23 2016/03 Refereed English Research paper(international conference proceedings) Disclose to all
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 691-696 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 691-696 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 691-696 2016/01 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations Proc. of 2016 Asia and South-Pacific Design Automation Conference, 403-409 Proc. of 2016 Asia and South-Pacific Design Automation Conference, 403-409 Proc. of 2016 Asia and South-Pacific Design Automation Conference, 403-409 2016/01 Refereed English Research paper(international conference proceedings) Disclose to all
N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura1, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura1, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs 2015 International Electron Devices Meeting, 2.5.1-2.5.4 2015 International Electron Devices Meeting, 2.5.1-2.5.4 2015 International Electron Devices Meeting, 2.5.1-2.5.4 2015/12 Refereed English Research paper(international conference proceedings) Disclose to all
A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring IEEE Journal of Solid-State Circuits, 50, 11, 2475-2490 IEEE Journal of Solid-State Circuits, 50, 11, 2475-2490 IEEE Journal of Solid-State Circuits, 50, 11, 2475-2490 2015/11 Refereed English Research paper(scientific journal) Disclose to all
Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking IEEE Asian Solid-State Circuits Conference, 1-4 IEEE Asian Solid-State Circuits Conference, 1-4 IEEE Asian Solid-State Circuits Conference, 1-4 2015/11 Refereed English Research paper(international conference proceedings) Disclose to all
塩見準,石原亨,小野寺秀俊 塩見準,石原亨,小野寺秀俊 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング 情報処理学会DAシンポジウム2015論文集, 137-142 情報処理学会DAシンポジウム2015論文集, 137-142 , 137-142 2015/08/27 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
鎌苅竜也,塩見準,石原亨,小野寺秀俊 鎌苅竜也,塩見準,石原亨,小野寺秀俊 サブスレッショルド領域におけるラッチ回路の動作安定性モデル サブスレッショルド領域におけるラッチ回路の動作安定性モデル 情報処理学会DAシンポジウム2015論文集, 187-192 情報処理学会DAシンポジウム2015論文集, 187-192 , 187-192 2015/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
中井辰哉、イスラム マーフズル、小野寺秀俊 中井辰哉、イスラム マーフズル、小野寺秀俊 再構成可能なリングオシレータを用いたランダムテレグラフノイズの統計解析 再構成可能なリングオシレータを用いたランダムテレグラフノイズの統計解析 情報処理学会DAシンポジウム2015論文集, 95-100 情報処理学会DAシンポジウム2015論文集, 95-100 , 95-100 2015/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
ONODERA Hidetoshi 小野寺 秀俊 ONODERA Hidetoshi Dependable VLSI Platform with Variability and Soft-Error Resilience Dependable VLSI Platform with Variability and Soft-Error Resilience Dependable VLSI Platform with Variability and Soft-Error Resilience Proceedings of the 2015 International Conference on Integrated Circutis, Design, and Verification, 102-103 Proceedings of the 2015 International Conference on Integrated Circutis, Design, and Verification, 102-103 Proceedings of the 2015 International Conference on Integrated Circutis, Design, and Verification, 102-103 2015/08 Refereed English Research paper(international conference proceedings) Disclose to all
S. Nishizawa, T. Ishihara, H. Onodera S. Nishizawa, T. Ishihara, H. Onodera An impact of process variation on supply voltage dependence of logic path delay variation An impact of process variation on supply voltage dependence of logic path delay variation An impact of process variation on supply voltage dependence of logic path delay variation Proc. of the 2015 International Symposium on VLSI Design, Automation and Test, 1-4 Proc. of the 2015 International Symposium on VLSI Design, Automation and Test, 1-4 Proc. of the 2015 International Symposium on VLSI Design, Automation and Test, 1-4 2015/04 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera 塩見準,石原亨,小野寺秀俊 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design ニアスレッショルド回路設計のための基本定理 Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design IEICE Technical Report, VLD2014-172, 109-114 電子情報通信学会技術研究報告, VLD2014-172, 109-114 IEICE Technical Report, VLD2014-172, 109-114 2015/03/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
釡江 典裕, 土谷 亮, 石原 亨, 小野寺 秀俊 釡江 典裕, 土谷 亮, 石原 亨, 小野寺 秀俊 PLLの物理レイアウト自動生成を目指した設計手法 PLLの物理レイアウト自動生成を目指した設計手法 情報処理学会DAシンポジウム2014論文集 情報処理学会DAシンポジウム2014論文集 2014/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
鎌苅竜也,西澤真一,石原亨,小野寺秀俊 鎌苅竜也,西澤真一,石原亨,小野寺秀俊 製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法 製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法 情報処理学会DAシンポジウム2014論文集, 91-96 情報処理学会DAシンポジウム2014論文集, 91-96 , 91-96 2014/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
塩見準,石原亨,小野寺秀俊 塩見準,石原亨,小野寺秀俊 ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオン チップメモリの設計 ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオン チップメモリの設計 情報処理学会DAシンポジウム2014論文集, 103-108 情報処理学会DAシンポジウム2014論文集, 103-108 , 103-108 2014/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
西澤真一, 石原 亨, 小野寺秀俊 西澤真一, 石原 亨, 小野寺秀俊 電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム 電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム 情報処理学会DAシンポジウム2014論文集, 97-102 情報処理学会DAシンポジウム2014論文集, 97-102 , 97-102 2014/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Shohei NISHIMURA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI, Hidetoshi ONODERA 西村彰平、松本高士、小林和淑、小野寺秀俊 Shohei NISHIMURA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI, Hidetoshi ONODERA Characterization of Random Telegraph Noise using Inhomogeneous Ring Oscillator 非均質なリングオシレータを用いたランダムテレグラフノイズの特性解析 Characterization of Random Telegraph Noise using Inhomogeneous Ring Oscillator IEICE Technical Report, VLD2013-134 電子情報通信学会技術研究報告, VLD2013-134 IEICE Technical Report, VLD2013-134 2014/03/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Takashi MATSUMOTO, Kazutoshi KOBAYASHI, Hidetoshi ONODERA 松本高士、小林和淑、小野寺秀俊 Takashi MATSUMOTO, Kazutoshi KOBAYASHI, Hidetoshi ONODERA Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay CMOSトランジスタのランダム・テレグラフ・ノイズが組合せ回路遅延に及ぼす影響 Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay IEICE Technical Report, VLD2013-135 電子情報通信学会技術研究報告, VLD2013-135 IEICE Technical Report, VLD2013-135 2014/03/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA 古田潤、小林和淑、小野寺秀俊 Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA Evaluation of Multiple Cell Upsets Considering Parasitic Biploar Effects 寄生バイポーラ効果を考慮した多ビットソフトエラーの評価 Evaluation of Multiple Cell Upsets Considering Parasitic Biploar Effects IEICE Technical Report, VLD2013-157 電子情報通信学会技術研究報告, VLD2013-157 IEICE Technical Report, VLD2013-157 2014/03 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 特性ばらつき概説 特性ばらつき概説 日本信頼性学会誌, 35, 8, 445-446 日本信頼性学会誌, 35, 8, 445-446 , 35, 8, 445-446 2013/12 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺 秀俊 小野寺 秀俊 特性ばらつきの診断と補償 特性ばらつきの診断と補償 日本信頼性学会誌, 35, 8, 445-446 日本信頼性学会誌, 35, 8, 445-446 , 35, 8, 445-446 2013/12 Refereed Japanese Research paper(scientific journal) Disclose to all
西澤真一、石原 亨,小野寺秀俊 西澤真一、石原 亨,小野寺秀俊 低電圧動作に向けたXOR論理ゲートの構成法の検討 低電圧動作に向けたXOR論理ゲートの構成法の検討 DAシンポジウム2013, 9-14 DAシンポジウム2013, 9-14 , 9-14 2013/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
近藤正大、石原 亨、小野寺秀俊 近藤正大、石原 亨、小野寺秀俊 ニアスレショルド電圧動作に適したスタンダードセルの駆動力集合の決定法 ニアスレショルド電圧動作に適したスタンダードセルの駆動力集合の決定法 DAシンポジウム2013, 21-26 DAシンポジウム2013, 21-26 , 21-26 2013/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Islam A.K.M. Mahfuzul、小野寺秀俊 Islam A.K.M. Mahfuzul、小野寺秀俊 チップ間およびチップ内ばらつきを評価可能な再構成可能遅延モニタ回路 チップ間およびチップ内ばらつきを評価可能な再構成可能遅延モニタ回路 DAシンポジウム2013, 121-126 DAシンポジウム2013, 121-126 , 121-126 2013/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
修 斉、石原 亨、小野寺秀俊 修 斉、石原 亨、小野寺秀俊 電源電圧・閾値電圧・パイプライン段数の同時スケーリングによるプロセッサのエネルギー高効率化設計手法 電源電圧・閾値電圧・パイプライン段数の同時スケーリングによるプロセッサのエネルギー高効率化設計手法 DAシンポジウム2013, 145-150 DAシンポジウム2013, 145-150 , 145-150 2013/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
SinNyoung KIM, Akira Tsuchiya, Hidetoshi Onodera SinNyoung KIM, Akira Tsuchiya, Hidetoshi Onodera Analysis of Radiation-Induced Timing Vulnerability on Phase-locked Loops Analysis of Radiation-Induced Timing Vulnerability on Phase-locked Loops DAシンポジウム2013, 73-78 DAシンポジウム2013, 73-78 , 73-78 2013/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
密山幸男(高知工科大学)、尾上孝雄(大阪大学)、小野寺秀俊(京都大学) 密山幸男(高知工科大学)、尾上孝雄(大阪大学)、小野寺秀俊(京都大学) 「再構成可能ディペンダブルVLSIプラットホーム」 「再構成可能ディペンダブルVLSIプラットホーム」 電子情報通信学会学会誌, 95-99 電子情報通信学会学会誌, 95-99 , 95-99 2013/02 Refereed Japanese Research paper(scientific journal) Disclose to all
松本高士、小林和淑、小野寺秀俊 松本高士、小林和淑、小野寺秀俊 ランダム・テレグラフ・ノイズが低電圧CMOS論理回路の遅延ゆら ぎに及ぼす影響 ランダム・テレグラフ・ノイズが低電圧CMOS論理回路の遅延ゆら ぎに及ぼす影響 応用物理学会分科会 シリコンテクノロジー, 154, 27-30 応用物理学会分科会 シリコンテクノロジー, 154, 27-30 , 154, 27-30 2013/01/30 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士, 小林和淑, 小野寺秀俊 松本高士, 小林和淑, 小野寺秀俊 ランダム・テレグラフ・ノイズに起因した組合せ回路遅延ゆらぎに対する基板バイアスの影響 ランダム・テレグラフ・ノイズに起因した組合せ回路遅延ゆらぎに対する基板バイアスの影響 デザインガイア2012, 信学技報, 112, 320, 63-68 デザインガイア2012, 信学技報, 112, 320, 63-68 , 112, 320, 63-68 2012/11/26 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
KIM SinNyoung;TSUCHIYA Akira;ONODERA Hidetoshi;ONODERA Hidetoshi 松本高士;小林和淑;小林和淑;小野寺秀俊;小野寺秀俊 KIM SinNyoung;TSUCHIYA Akira;ONODERA Hidetoshi;ONODERA Hidetoshi Evaluation of Single-Event Vulnerability in Analog and Digital Signals of PLL based on Error-Categorization NBTI・RTNが論理回路およびSRAMの信頼性に与える影響について Evaluation of Single-Event Vulnerability in Analog and Digital Signals of PLL based on Error-Categorization DA Symposium, 2012, 5, 151-156 情報処理学会シンポジウム論文集, 2012, 5, 151-156 DA Symposium, 2012, 5, 151-156 2012/08/22 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
釡江典裕、土谷亮、小野寺秀俊(京都大学) 釡江典裕、土谷亮、小野寺秀俊(京都大学) チップ内基板バイアス生成回路のモジュール化設計 チップ内基板バイアス生成回路のモジュール化設計 情報処理学会DAシンポジウム2012論文集, 55-60 情報処理学会DAシンポジウム2012論文集, 55-60 , 55-60 2012/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Islam A.K.M Mahfuzul、釡江典裕、石原亨、小野寺秀俊(京都大学) Islam A.K.M Mahfuzul、釡江典裕、石原亨、小野寺秀俊(京都大学) 完全ディジタル型のP/Nばらつきの自律補償回路 完全ディジタル型のP/Nばらつきの自律補償回路 情報処理学会DAシンポジウム2012論文集, 43-48 情報処理学会DAシンポジウム2012論文集, 43-48 , 43-48 2012/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 松本高士(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) LSI信頼性へのRTN・NBTIの影響と特性補償技術について LSI信頼性へのRTN・NBTIの影響と特性補償技術について LSIとシステムのワークショップ LSIとシステムのワークショップ 2012/05 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮、小野寺 秀俊 土谷 亮、小野寺 秀俊 伝送線路の損失に対する異常表皮効果の影響 伝送線路の損失に対する異常表皮効果の影響 電子情報通信学会技術報告(マイクロ波), MW2011-139, MW2011-139 (2011-12), 77-81 電子情報通信学会技術報告(マイクロ波), MW2011-139, MW2011-139 (2011-12), 77-81 , MW2011-139 (2011-12), 77-81 2011/12/16 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
山本亮輔、 濱中力(京都工芸繊維大学)、 古田潤(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) 山本亮輔、 濱中力(京都工芸繊維大学)、 古田潤(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) MCUに強靭な耐ソフトエラーフリップフロップ MCUに強靭な耐ソフトエラーフリップフロップ 電子情報通信学会技術報告(集積回路設計), ICD2011-129, ICD2011-129 電子情報通信学会技術報告(集積回路設計), ICD2011-129, ICD2011-129 , ICD2011-129 2011/12/16 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士、 牧野紘明(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学)) 松本高士、 牧野紘明(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学)) NBTI回復現象を利用したマルチコアLSIの自己特性補償法 NBTI回復現象を利用したマルチコアLSIの自己特性補償法 電子情報通信学会技術報告(集積回路設計), ICD2011-92, ICD2011-92, 59-63 電子情報通信学会技術報告(集積回路設計), ICD2011-92, ICD2011-92, 59-63 , ICD2011-92, 59-63 2011/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
北島和彦、小野寺秀俊 北島和彦、小野寺秀俊 チップ内ばらつき耐性を高めたフリップフロップの設計手法 チップ内ばらつき耐性を高めたフリップフロップの設計手法 DAシンポジウム2011年論文集, 183-188 DAシンポジウム2011年論文集, 183-188 , 183-188 2011/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
増田政基、 岡田翔伍、 山本亮輔(京都工芸繊維大学)、 古田潤(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) 増田政基、 岡田翔伍、 山本亮輔(京都工芸繊維大学)、 古田潤(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) スタンダードセルベースASICにおける多重化フリップフロップのソフトエラー耐性の評価 スタンダードセルベースASICにおける多重化フリップフロップのソフトエラー耐性の評価 回路とシステムワークショップ講演論文集 回路とシステムワークショップ講演論文集 2011/08/11 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
古田潤(京都大)、 濱中力、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) 古田潤(京都大)、 濱中力、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) 寄生バイポーラ効果を考慮したソフトエラーによる一過性パルスのモデル化と評価 寄生バイポーラ効果を考慮したソフトエラーによる一過性パルスのモデル化と評価 DAシンポジウム2011年論文集, 81-86 DAシンポジウム2011年論文集, 81-86 , 81-86 2011/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
西澤真一(京都大)、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) 西澤真一(京都大)、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) パッケージとの接続抵抗を考慮したチップ内電源ネットワークの構成手法 パッケージとの接続抵抗を考慮したチップ内電源ネットワークの構成手法 DAシンポジウム2011年論文集, 45-50 DAシンポジウム2011年論文集, 45-50 , 45-50 2011/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
金 信寧、土谷 亮、 小野寺 秀俊 金 信寧、土谷 亮、 小野寺 秀俊 金 信寧、土谷 亮、 小野寺 秀俊 Evaluation of future PLL performance by predictive model card reflecting ITRS technology scaling Evaluation of future PLL performance by predictive model card reflecting ITRS technology scaling Evaluation of future PLL performance by predictive model card reflecting ITRS technology scaling DAシンポジウム2011年論文集, pp.105-110, 105-110 DAシンポジウム2011年論文集, 105-110 DAシンポジウム2011年論文集, pp.105-110, 105-110 2011/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士、牧野裕明(京都大)、小林和淑(京都工繊大)、小野寺秀俊(京都大) 松本高士、牧野裕明(京都大)、小林和淑(京都工繊大)、小野寺秀俊(京都大) トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について LSIとシステムのワークショップ 2011 LSIとシステムのワークショップ 2011 2011/05/18 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士、牧野裕明(京都大)、小林和淑(京都工繊大)、小野寺秀俊(京都大) 松本高士、牧野裕明(京都大)、小林和淑(京都工繊大)、小野寺秀俊(京都大) トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について LSIとシステムのワークショップ 2011 LSIとシステムのワークショップ 2011 2011/05/17 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺秀俊 小野寺秀俊 ロバストファブリックを用いたディペンダブルVLSIプラットフォーム ロバストファブリックを用いたディペンダブルVLSIプラットフォーム LSIとシステムのワークショップ 2011 LSIとシステムのワークショップ 2011 2011/05 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺秀俊 小野寺秀俊 More Mooreに立ちはだかるCMOSばらつきの理解に向けて More Mooreに立ちはだかるCMOSばらつきの理解に向けて 信学技報VLD2010-124, 110, 432, 49-49 信学技報VLD2010-124, 110, 432, 49-49 , 110, 432, 49-49 2011/03/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
松本高士、牧野紘明(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 松本高士、牧野紘明(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 測定時の劣化の影響を除去した高速NBTI回復特性センサーの検討 測定時の劣化の影響を除去した高速NBTI回復特性センサーの検討 電子情報通信学会技術報告(集積回路設計) 電子情報通信学会技術報告(集積回路設計) 2010/12/16 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
伊東恭佑、松本高士、小林和淑、小野寺秀俊 伊東恭佑、松本高士、小林和淑、小野寺秀俊 組み合わせ回路におけるランダム・テレグラフ・ノイズの影響の評価 組み合わせ回路におけるランダム・テレグラフ・ノイズの影響の評価 DAシンポジウム2010年論文集, 99-104 DAシンポジウム2010年論文集, 99-104 , 99-104 2010/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤本秀一、Islam A.K.M. Mahfuzul、西澤真一、小野寺秀俊 藤本秀一、Islam A.K.M. Mahfuzul、西澤真一、小野寺秀俊 チップ内ばらつきの成分解析手法 チップ内ばらつきの成分解析手法 DAシンポジウム2010年論文集, 215-220 DAシンポジウム2010年論文集, 215-220 , 215-220 2010/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
北島和彦、砂川洋輝、土谷亮、小野寺秀俊 北島和彦、砂川洋輝、土谷亮、小野寺秀俊 レイアウト制約が性能と製造性に与える影響 レイアウト制約が性能と製造性に与える影響 DAシンポジウム2010年論文集, 221-226 DAシンポジウム2010年論文集, 221-226 , 221-226 2010/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
古田潤、小林和淑、小野寺秀俊 古田潤、小林和淑、小野寺秀俊 バッファチェインにおけるパルス幅縮小現象を利用したSETパルス幅測定回路 バッファチェインにおけるパルス幅縮小現象を利用したSETパルス幅測定回路 DAシンポジウム2010年論文集, 233-238 DAシンポジウム2010年論文集, 233-238 , 233-238 2010/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
濱中力(京都工芸繊維大学)、古田潤、牧野紘明(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 濱中力(京都工芸繊維大学)、古田潤、牧野紘明(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 基板バイポーラ効果によるSEUとMCUの発生機構の検討 基板バイポーラ効果によるSEUとMCUの発生機構の検討 電子情報通信学会 VLSI設計技術研究会 電子情報通信学会 VLSI設計技術研究会 2010/03/10 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
奥村 佳弘、中村 誠、岸根 桂路、土谷 亮、小野寺 秀俊 奥村 佳弘、中村 誠、岸根 桂路、土谷 亮、小野寺 秀俊 相互結合インダクタを用いたTIA帯域向上手法 相互結合インダクタを用いたTIA帯域向上手法 電子情報通信学会技術報告書, 157-161 電子情報通信学会技術報告書, 157-161 , 157-161 2009/12/15 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Islam A.K.M. Mahfuzul、土谷亮、小林和淑、小野寺秀俊 Islam A.K.M. Mahfuzul、土谷亮、小林和淑、小野寺秀俊 遅延モニタ回路によるプロセス変動量の推定 遅延モニタ回路によるプロセス変動量の推定 DAシンポジウム2009, 127-132 DAシンポジウム2009, 127-132 , 127-132 2009/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
古田 潤, 小林 和淑, 小野寺 秀俊 古田 潤, 小林 和淑, 小野寺 秀俊 高いSEU/SET耐性を持つ省面積・低遅延二重化フリップフロップ 高いSEU/SET耐性を持つ省面積・低遅延二重化フリップフロップ 第22回回路とシステム軽井沢ワークショップ, 456-461 第22回回路とシステム軽井沢ワークショップ, 456-461 , 456-461 2009/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Hidetoshi Onodera 小野寺秀俊 Hidetoshi Onodera Toward Variability-Aware Design ばらつき考慮設計に向けて Toward Variability-Aware Design IEICE Technical Report, 83-88 電子情報通信学会技術研究報告 ICD2008-73, 83-88 IEICE Technical Report, 83-88 2008/11/18 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera 久米洋平、杉原有理、Ngo Cam Lai、小林和淑、小野寺秀俊 Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera A Low-cost Speed and Yield Enhancement Method using Enbedded Delay-Detectors on FPGAs 遅延比較器を用いた低コストなFPGAの速度・歩留まり向上手法 A Low-cost Speed and Yield Enhancement Method using Enbedded Delay-Detectors on FPGAs IEICE Technical Report, VLD2007-163, ICD-2007-186, 41-46 電子情報通信学会技術報告, VLD2007-163, ICD-2007-186, 41-46 IEICE Technical Report, VLD2007-163, ICD-2007-186, 41-46 2008/03/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
久米洋平、杉原有理、香月和也、小林和淑、小野寺秀俊 久米洋平、杉原有理、香月和也、小林和淑、小野寺秀俊 チップ内ばらつきを利用して歩留まりと速度を向上させるFPGA チップ内ばらつきを利用して歩留まりと速度を向上させるFPGA 第11回システムLSIワークショップ予稿集, 278-280 第11回システムLSIワークショップ予稿集, 278-280 , 278-280 2007/11/20 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera 杉原有理、久米洋平、小林和淑、小野寺秀俊 Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield ランダムばらつきを利用したトラック入れ替えによるFPGAの速度と歩留まり向上 Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield IEICE Technical Report(RECONF2007-34), 107, 340, 13-18 電子情報通信学会技術報告(RECONF2007-34), 107, 340, 13-18 IEICE Technical Report(RECONF2007-34), 107, 340, 13-18 2007/11/20 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
橋本昌宜;小野寺秀俊 杉原有理;小林和淑;小野寺俊秀 橋本昌宜;小野寺秀俊 A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits. 配線自由度によるばらつきを利用したFPGAの速度向上 A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits. 電子情報通信学会技術研究報告, 2007, 7, 139-144 情報処理学会シンポジウム論文集, 2007, 7, 139-144 電子情報通信学会技術研究報告, 2007, 7, 139-144 2007/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
福岡孝之、土谷 亮、小野寺秀俊 福岡孝之、土谷 亮、小野寺秀俊 同時スイッチングの影響を考慮した統計的遅延解析 同時スイッチングの影響を考慮した統計的遅延解析 DAシンポジウム2007, 13-18 DAシンポジウム2007, 13-18 , 13-18 2007/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮;小野寺 秀俊 土谷 亮;小野寺 秀俊 ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法 (第20回 回路とシステム軽井沢ワークショップ論文集) -- (デバイスモデリング) ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法 (第20回 回路とシステム軽井沢ワークショップ論文集) -- (デバイスモデリング) 回路とシステム軽井沢ワークショップ論文集, 20, 19-22 回路とシステム軽井沢ワークショップ論文集, 20, 19-22 , 20, 19-22 2007/04/23 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮、小野寺 秀俊 土谷 亮、小野寺 秀俊 ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法 ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法 第20回 回路とシステム軽井沢ワークショップ, 19-22 第20回 回路とシステム軽井沢ワークショップ, 19-22 , 19-22 2007/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
K. Ogata, M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera 尾形幸亮、小谷学、香月和也、小林和淑、小野寺秀俊 K. Ogata, M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera Speed Enhancement of FPGAs by Reconfiguration by Utilizing Variations within a Chip FPGAのチップ内ばらつきを利用した再配置による高速化の検討 Speed Enhancement of FPGAs by Reconfiguration by Utilizing Variations within a Chip IEICE Technical Report(RECONF), 106, 50(RECONF2006-14), 19-24 信学技報リコンフィギャラブルシステム, 106, 50(RECONF2006-14), 19-24 IEICE Technical Report(RECONF), 106, 50(RECONF2006-14), 19-24 2006/05/19 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 DFM ばらつきを克服する設計技術 DFM ばらつきを克服する設計技術 回路とシステム軽井沢ワークショップ論文集, 19, 565-570 回路とシステム軽井沢ワークショップ論文集, 19, 565-570 , 19, 565-570 2006/04/24 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮;小野寺 秀俊 土谷 亮;小野寺 秀俊 オンチップ長距離高速信号伝送の性能予測 (信号伝送回路) オンチップ長距離高速信号伝送の性能予測 (信号伝送回路) 回路とシステム軽井沢ワークショップ論文集, 19, 393-398 回路とシステム軽井沢ワークショップ論文集, 19, 393-398 , 19, 393-398 2006/04/24 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
久保木 猛;土谷 亮;小野寺 秀俊 久保木 猛;土谷 亮;小野寺 秀俊 出力インピーダンスの調整による高速信号伝送用CMLドライバの低消費電力設計 (信号伝送回路) 出力インピーダンスの調整による高速信号伝送用CMLドライバの低消費電力設計 (信号伝送回路) 回路とシステム軽井沢ワークショップ論文集, 19, 387-392 回路とシステム軽井沢ワークショップ論文集, 19, 387-392 , 19, 387-392 2006/04/24 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
久保木 猛、土谷 亮、小野寺 秀俊 久保木 猛、土谷 亮、小野寺 秀俊 出力インピーダンスの調整による高速信号伝送用CMLドライバの低消費電力設計 出力インピーダンスの調整による高速信号伝送用CMLドライバの低消費電力設計 第19回 回路とシステム軽井沢ワークショップ, 387-392 第19回 回路とシステム軽井沢ワークショップ, 387-392 , 387-392 2006/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮、小野寺 秀俊 土谷 亮、小野寺 秀俊 オンチップ長距離高速信号伝送の性能予測 オンチップ長距離高速信号伝送の性能予測 第19回 回路とシステム軽井沢ワークショップ, 393-398 第19回 回路とシステム軽井沢ワークショップ, 393-398 , 393-398 2006/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 ばらつきを克服する設計技術 ばらつきを克服する設計技術 第19回 回路とシステム軽井沢ワークショップ, 565-570 第19回 回路とシステム軽井沢ワークショップ, 565-570 , 565-570 2006/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
杉原 有理, 高務 祐哲, 小林 和淑, 小野寺 秀俊 杉原 有理, 高務 祐哲, 小林 和淑, 小野寺 秀俊 チップ内ばらつきを考慮したFPGA内配線モデルの検討 チップ内ばらつきを考慮したFPGA内配線モデルの検討 第19回 回路とシステム軽井沢ワークショップ, 547-552 第19回 回路とシステム軽井沢ワークショップ, 547-552 , 547-552 2006/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小谷学、香月和也、尾形幸亮、小林和淑、小野寺秀俊 小谷学、香月和也、尾形幸亮、小林和淑、小野寺秀俊 ばらつきを利用し補償するための再構成可能回路 ばらつきを利用し補償するための再構成可能回路 信学技報(VLSI設計技術), VLD-2005-130, 49-54 信学技報(VLSI設計技術), VLD-2005-130, 49-54 , VLD-2005-130, 49-54 2006/03/10 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮、新名 亮規、橋本 昌宜、小野寺 秀俊 土谷 亮、新名 亮規、橋本 昌宜、小野寺 秀俊 CMLを用いたオンチップ長距離高速信号伝送技術の開発 CMLを用いたオンチップ長距離高速信号伝送技術の開発 第9回システムLSIワークショップ, 275-278 第9回システムLSIワークショップ, 275-278 , 275-278 2005/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小林 和淑、香月 和也、小谷 学、小野寺 秀俊 小林 和淑、香月 和也、小谷 学、小野寺 秀俊 トランジスタの特性ばらつきを利用する再構成デバイス トランジスタの特性ばらつきを利用する再構成デバイス 第9回システムLSIワークショップ, 129-135 第9回システムLSIワークショップ, 129-135 , 129-135 2005/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera 湯山 洋一、小林 和淑、小野寺 秀俊 Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect オンチップグローバル配線における確定的/確率的ノイズとエラー率のモデル化 Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect Technical Report of IPSJ, 2005-SLDM-122-(20), 115-120 情報処理学会研究報告, 2005-SLDM-122-(20), 115-120 Technical Report of IPSJ, 2005-SLDM-122-(20), 115-120 2005/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 微細化限界を回路テクノロジで突破する 微細化限界を回路テクノロジで突破する 第9回システムLSIワークショップ, 57-68 第9回システムLSIワークショップ, 57-68 , 57-68 2005/11/28 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Y. Takatsukasa, K. Kobayashi, H. Onodera 高務祐哲、小林和淑、小野寺秀俊 Y. Takatsukasa, K. Kobayashi, H. Onodera An Energy Reduction Technique by Task Relocation Considering Energy Minimum Execution Frequency for Multiprocessor Systems エネルギ最小周波数を利用したタスク再配置によるマルチプロセッサ向け消費エネルギ削減手法 An Energy Reduction Technique by Task Relocation Considering Energy Minimum Execution Frequency for Multiprocessor Systems Technical Report of IEICE, VLD2004-143, ICD2004-239, 37-42 信学技報, VLD2004-143, ICD2004-239, 37-42 Technical Report of IEICE, VLD2004-143, ICD2004-239, 37-42 2005/03/11 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、橋本昌宜、小野寺秀俊 土谷亮、橋本昌宜、小野寺秀俊 オンチップ高速信号伝送用線路の解析的性能評価 オンチップ高速信号伝送用線路の解析的性能評価 信学技報, 49-54 信学技報, 49-54 , 49-54 2005/03/11 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
A. Higuchi, K. Kobayashi, H. Onodera 樋口昭彦、小林和淑、小野寺秀俊 A. Higuchi, K. Kobayashi, H. Onodera A Leakage Current Reduction Technique by Optimizing Waiting Time Dynamically in Self-Timed Cut-Off Scheme Self-Timed Cut-Off法の待ち時間動的最適化によるリーク電流削減手法 A Leakage Current Reduction Technique by Optimizing Waiting Time Dynamically in Self-Timed Cut-Off Scheme Technical Report of IEICE, VLD2004-94/ICD2004-180/DC2004-80 信学技報, VLD2004-94/ICD2004-180/DC2004-80 Technical Report of IEICE, VLD2004-94/ICD2004-180/DC2004-80 2004/12/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、橋本昌宜、小野寺秀俊 土谷亮、橋本昌宜、小野寺秀俊 配線RL抽出におけるリターンパス選択手法 配線RL抽出におけるリターンパス選択手法 DAシンポジウム2004論文集, 175-180 DAシンポジウム2004論文集, 175-180 , 175-180 2004/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
A. Higuchi, K. Kobayashi, H. Onodera 樋口昭彦、小林和淑、小野寺秀俊 A. Higuchi, K. Kobayashi, H. Onodera A High-Level Power Model for Synthesized Register Files Using Access Pattern アクセスパターンによるレジスタファイルの高位消費電力モデル A High-Level Power Model for Synthesized Register Files Using Access Pattern Technical Report of IEICE, VLD2004-11(2004-05), 25-30 信学技報, VLD2004-11(2004-05), 25-30 Technical Report of IEICE, VLD2004-11(2004-05), 25-30 2004/06/22 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
J. Yamaguchi, M. Hashimoto, H. Onodera 山口隼司、橋本昌宜、小野寺秀俊 J. Yamaguchi, M. Hashimoto, H. Onodera Static Timing Analysis Considering Supply Voltage Variation among Logic Cells ゲート毎の電源電圧変動を考慮した静的遅延解析法 Static Timing Analysis Considering Supply Voltage Variation among Logic Cells Technical Report of IEICE, VLD2003-143/ICD2003-236 信学技報, VLD2003-143/ICD2003-236 Technical Report of IEICE, VLD2003-143/ICD2003-236 2004/03/17 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
M. Aramoto, Y. Yuyama, A. Higuchi, J. Okazawa, K. Kobayashi, H. Onodera 荒本雅夫、湯山洋一、樋口昭彦、岡澤潤香、小林和淑、小野寺秀俊 M. Aramoto, Y. Yuyama, A. Higuchi, J. Okazawa, K. Kobayashi, H. Onodera Performance Evaluation of a Resource-Shared VLIW Processor Array 資源共有型VLIWプロセッサの性能評価 Performance Evaluation of a Resource-Shared VLIW Processor Array Technical Report of IEICE, VLD-2003-115, 7月12日 信学技法, VLD-2003-115, 7月12日 Technical Report of IEICE, VLD-2003-115, 7月12日 2004/01/22 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 高度情報化社会を支える集積回路 ―情報処理デバイスの回路・システム化技術― 高度情報化社会を支える集積回路 ―情報処理デバイスの回路・システム化技術― 京都大学大学院情報学研究科 第6 回情報学シンポジウム 「世界のセンターオブエクセレンスをめざして」   平成15 年12 月1 日(月曜日) 「高度情報化社会を支える集積回路 ―情報処理デバイスの回路・システム化技術―」 小野寺 秀俊 (通信情報シ ステム専攻教授) 京都大学大学院情報学研究科 第6 回情報学シンポジウム 「世界のセンターオブエクセレンスをめざして」   平成15 年12 月1 日(月曜日) 「高度情報化社会を支える集積回路 ―情報処理デバイスの回路・システム化技術―」 小野寺 秀俊 (通信情報シ ステム専攻教授) 2003/12 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
荒本雅夫、湯山洋一、樋口昭彦、岡澤潤香、小林和淑、小野寺秀俊 荒本雅夫、湯山洋一、樋口昭彦、岡澤潤香、小林和淑、小野寺秀俊 処理の優先度を利用した実行ユニット共有型VLIWプロセッサアレイ 処理の優先度を利用した実行ユニット共有型VLIWプロセッサアレイ 第7回システムLSIワークショップ, 267-270 第7回システムLSIワークショップ, 267-270 , 267-270 2003/11/26 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
T. Miyazaki, M. Hashimoto, H. Onodera 宮崎崇仁、橋本昌宜、小野寺秀俊 T. Miyazaki, M. Hashimoto, H. Onodera A Performance Prediction of Clock Generation PLLs in Digital CMOS Processes -The Efficacy of LC Oscillator based PLLs- デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 -LC発振型VCOを用いたPLLの有効性- A Performance Prediction of Clock Generation PLLs in Digital CMOS Processes -The Efficacy of LC Oscillator based PLLs- Technical Report of IEICE, ICD20003-98, 29-34 信学技法, ICD20003-98, 29-34 Technical Report of IEICE, ICD20003-98, 29-34 2003/09/12 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、橋本昌宜、小野寺秀俊 土谷亮、橋本昌宜、小野寺秀俊 直交配線を持つオンチップ伝送線路の特性評価 直交配線を持つオンチップ伝送線路の特性評価 情報処理学会 DAシンポジウム2003年論文集, 133-138 情報処理学会 DAシンポジウム2003年論文集, 133-138 , 133-138 2003/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
樋口昭彦、小林和淑、小野寺秀俊 樋口昭彦、小林和淑、小野寺秀俊 命令レベルにおけるレジスタの変化ビット幅を考慮した組み込みプロセッサ向け消費電力見積り手法 命令レベルにおけるレジスタの変化ビット幅を考慮した組み込みプロセッサ向け消費電力見積り手法 第16回 回路とシステム(軽井沢)ワークショップ論文集, 453-458 第16回 回路とシステム(軽井沢)ワークショップ論文集, 453-458 , 453-458 2003/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、橋本昌宜、小野寺秀俊 土谷亮、橋本昌宜、小野寺秀俊 配線R(f)L(f)C抽出のための代表周波数決定手法 配線R(f)L(f)C抽出のための代表周波数決定手法 第16回 回路とシステム(軽井沢)ワークショップ論文集, 61-66 第16回 回路とシステム(軽井沢)ワークショップ論文集, 61-66 , 61-66 2003/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Yuji Yamada, Masanori Hashimoto, Hidetoshi Onodera 山田祐嗣、橋本昌宜、小野寺秀俊 Yuji Yamada, Masanori Hashimoto, Hidetoshi Onodera Estimating Equivalent Gate Input Waveform for Static Timing Analysis -Coping with waveform distortion due to VDSM processes- 静的遅延解析のための等価ゲート入力波形導出法 -VDSMプロセスに起因する波形歪みへの対応- Estimating Equivalent Gate Input Waveform for Static Timing Analysis -Coping with waveform distortion due to VDSM processes- IPSJ SIG notes, 2003-SLDM-108-20, 111-116 情報処理学会研究報告, 2003-SLDM-108-20, 111-116 IPSJ SIG notes, 2003-SLDM-108-20, 111-116 2003/01/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Y. Yuyama, M. Aramoto, K. Takai, K. Kobayashi, H. Onodera 湯山洋一、荒本雅夫、高井幸輔、小林和淑、小野寺秀俊 Y. Yuyama, M. Aramoto, K. Takai, K. Kobayashi, H. Onodera SoC Architecture with Unifunctional Heterogenous Processor Array 機能特化型プロセッサアレイによるSoCアーキテクチャ SoC Architecture with Unifunctional Heterogenous Processor Array Technical Report of IEICE, ICD2002-169, 31-36 信学技報, ICD2002-169, 31-36 Technical Report of IEICE, ICD2002-169, 31-36 2002/12/19 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
K. Okada, K. Yamaoka, H. Onodera 岡田健一、山岡健人、小野寺秀俊 K. Okada, K. Yamaoka, H. Onodera Statistical Gate-Delay Modeling with Intra-gate Variability CMOS論理ゲートにおけるセル内特性ばらつきを考慮した統計的遅延モデル化手法 Statistical Gate-Delay Modeling with Intra-gate Variability IPSJ SIG Notes, 2002, 113, 91-96 情報処理学会研究報告, 2002, 113, 91-96 IPSJ SIG Notes, 2002, 113, 91-96 2002/11/28 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
M. Aramoto, Y. Yuyama, K. Takai, K. Kobayashi, H. Onodera 荒本雅夫、湯山洋一、高井幸輔、小林和淑、小野寺秀俊 M. Aramoto, Y. Yuyama, K. Takai, K. Kobayashi, H. Onodera The Design of SH Compatible Processor Using RTL description of SystemC SystemCのRTL記述を用いたSH互換プロセッサの設計 The Design of SH Compatible Processor Using RTL description of SystemC Technical Report of IEICE, IE2002-75, 33-38 信学技報, IE2002-75, 33-38 Technical Report of IEICE, IE2002-75, 33-38 2002/10/24 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
林宙輝、橋本昌宜、小野寺秀俊 林宙輝、橋本昌宜、小野寺秀俊 セルベース設計環境を用いた高性能データパス設計法の検討 セルベース設計環境を用いた高性能データパス設計法の検討 情報処理学会 DAシンポジウム論文集 2002, 113-118 情報処理学会 DAシンポジウム論文集 2002, 113-118 , 113-118 2002/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
山口隼司、橋本昌宜、小野寺秀俊 山口隼司、橋本昌宜、小野寺秀俊 IRドロップを考慮した電源線構造の最適化手法 IRドロップを考慮した電源線構造の最適化手法 情報処理学会 DAシンポジウム2002年論文集, 253-258 情報処理学会 DAシンポジウム2002年論文集, 253-258 , 253-258 2002/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
平松大輔、土谷亮、橋本昌宜、小野寺秀俊 平松大輔、土谷亮、橋本昌宜、小野寺秀俊 長距離高速信号伝送を可能にするVLSI配線構造の検討 長距離高速信号伝送を可能にするVLSI配線構造の検討 情報処理学会 DAシンポジウム2002年論文集, 155-160 情報処理学会 DAシンポジウム2002年論文集, 155-160 , 155-160 2002/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
荒本雅夫、湯山洋一、小林和淑、小野寺秀俊 荒本雅夫、湯山洋一、小林和淑、小野寺秀俊 MPEG-4エンコーダのシステムレベル設計 MPEG-4エンコーダのシステムレベル設計 情報処理学会 DAシンポジウム2002年論文集, 31-36 情報処理学会 DAシンポジウム2002年論文集, 31-36 , 31-36 2002/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷 亮, 橋本 昌宜, 小野寺 秀俊 土谷 亮, 橋本 昌宜, 小野寺 秀俊 VLSI配線の伝送線路特性を考慮した駆動力決定手法 VLSI配線の伝送線路特性を考慮した駆動力決定手法 情報処理学会論文誌, 43, 5, 1338-1347 情報処理学会論文誌, 43, 5, 1338-1347 , 43, 5, 1338-1347 2002/05 Refereed Japanese Research paper(scientific journal) Disclose to all
岡田健一、小野寺 秀俊 岡田健一、小野寺 秀俊 トランジスタ特性におけるチップ内ばらつきのモデル化手法 トランジスタ特性におけるチップ内ばらつきのモデル化手法 情報処理学会論文誌, 43, 5, 1330-1337 情報処理学会論文誌, 43, 5, 1330-1337 , 43, 5, 1330-1337 2002/05 Refereed Japanese Research paper(scientific journal) Disclose to all
岡田健一、山岡健人、藤田智弘、小野寺秀俊 岡田健一、山岡健人、藤田智弘、小野寺秀俊 トランジスタ特性のチップ内ばらつきを考慮した統計遅延解析手法 トランジスタ特性のチップ内ばらつきを考慮した統計遅延解析手法 第15回 回路とシステム(軽井沢)ワークショップ論文集, 499-504 第15回 回路とシステム(軽井沢)ワークショップ論文集, 499-504 , 499-504 2002/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
K. Fujimori, M. Hashimoto, H. Onodera 藤森一憲、橋本昌宜、小野寺秀俊 K. Fujimori, M. Hashimoto, H. Onodera Development of Standard Cell Libraries Using Variable Driving Strength Cell Layout Generation System 駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリの開発 Development of Standard Cell Libraries Using Variable Driving Strength Cell Layout Generation System Technical Report of IEICE, VLD2001-147 電子情報通信学会技術研究報告, VLD2001-147 Technical Report of IEICE, VLD2001-147 2002/03/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
K. Okada, T. Fujita, H. Onodera 岡田健一、藤田智弘、小野寺秀俊 K. Okada, T. Fujita, H. Onodera A Statistical Timing Analysis with Intra-Chip Manufacturing Variability トランジスタ製造ばらつきにおけるチップ内特性変動を考慮した統計遅延解析手法 A Statistical Timing Analysis with Intra-Chip Manufacturing Variability Technical Report of IEICE, ICD2001-158/VLD2001-113/FTS2001-607-12 電子情報通信学会技術研究報告, ICD2001-158/VLD2001-113/FTS2001-607-12 Technical Report of IEICE, ICD2001-158/VLD2001-113/FTS2001-607-12 2001/11/30 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Y. Yuyama, K. Takai, K. Kobayashi, H. Onodera 湯山洋一、高井幸輔、小林和淑、小野寺秀俊 Y. Yuyama, K. Takai, K. Kobayashi, H. Onodera LSI Design Using SystemC and Bach SystemCとBachを用いたLSI設計手法 LSI Design Using SystemC and Bach Technical Report of IEICE, ICD2001-156/VLD2001-111/FTS2001-58133-138 電子情報通信学会技術研究報告, ICD2001-156/VLD2001-111/FTS2001-58133-138 Technical Report of IEICE, ICD2001-156/VLD2001-111/FTS2001-58133-138 2001/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
M. Hashimoto, M. Takahashi, H. Onodera 橋本昌宜、高橋正郎、小野寺秀俊 M. Hashimoto, M. Takahashi, H. Onodera Crosstalk Noise Optimization by Post-Layout Transistor Sizing ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法 Crosstalk Noise Optimization by Post-Layout Transistor Sizing Technical Report of IPSJ, SLDM103-6, 39-44 情報処理学会研究報告, SLDM103-6, 39-44 Technical Report of IPSJ, SLDM103-6, 39-44 2001/11/29 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
中西龍太、荒本雅夫、小林和淑、小野寺秀俊 中西龍太、荒本雅夫、小林和淑、小野寺秀俊 ジャイロセンサを用いた動画像圧縮システム ジャイロセンサを用いた動画像圧縮システム 第5回システムLSIワークショップ講演資料集およびポスタ資料集, 263-266 第5回システムLSIワークショップ講演資料集およびポスタ資料集, 263-266 , 263-266 2001/11/27 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
井口誠、星野洋昭、岡田健一、小野寺秀俊 井口誠、星野洋昭、岡田健一、小野寺秀俊 スパイラルインダクタのモデル化と最適化 スパイラルインダクタのモデル化と最適化 第5回システムLSIワークショップ講演資料集およびポスタ資料集, 363-366 第5回システムLSIワークショップ講演資料集およびポスタ資料集, 363-366 , 363-366 2001/11/27 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
R. Nakanishi, M. Aramoto, K. Kobayashi, H. Onodera 中西龍太、荒本雅夫、小林和淑、小野寺秀俊 R. Nakanishi, M. Aramoto, K. Kobayashi, H. Onodera A Study on Video Compression Using a Gyro Sensor ジャイロセンサを用いた動画像符号化の検討 A Study on Video Compression Using a Gyro Sensor Proceedings of PCSJ, P4.04, 71-72 第16回画像符号化シンポジウム資料, P4.04, 71-72 Proceedings of PCSJ, P4.04, 71-72 2001/11/13 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
R. Nakanishi, M. Aramoto, K. Kobayashi, H. Onodera 中西龍太、荒本雅夫、小林和淑、小野寺秀俊 R. Nakanishi, M. Aramoto, K. Kobayashi, H. Onodera Motion Estimation Using a Gyro Sensor ジャイロセンサを用いた動き補償 Motion Estimation Using a Gyro Sensor Proceedings of DSP Symposium, B5-4, 433-438 第16回ディジタル信号処理シンポジウム講演論文集, B5-4, 433-438 Proceedings of DSP Symposium, B5-4, 433-438 2001/11/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
高橋正郎、橋本昌宜、小野寺秀俊 高橋正郎、橋本昌宜、小野寺秀俊 隣接位置を考慮した解析的クロストークノイズ見積もり手法 隣接位置を考慮した解析的クロストークノイズ見積もり手法 DAシンポジウム2001, 19-24 DAシンポジウム2001, 19-24 , 19-24 2001/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
土谷亮、小野寺秀俊 土谷亮、小野寺秀俊 VLSI配線の伝送線路化を考慮した駆動力決定手法 VLSI配線の伝送線路化を考慮した駆動力決定手法 DAシンポジウム2001, 13-18 DAシンポジウム2001, 13-18 , 13-18 2001/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岡田健一、小野寺秀俊 岡田健一、小野寺秀俊 チップ内でのばらつきを考慮したトランジスタ特性ばらつきモデル化手法 チップ内でのばらつきを考慮したトランジスタ特性ばらつきモデル化手法 DAシンポジウム2001年論文集, 241-246 DAシンポジウム2001年論文集, 241-246 , 241-246 2001/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
中西龍太、小林和淑、小野寺秀俊 中西龍太、小林和淑、小野寺秀俊 カメラの動きを用いた動き補償の検討 カメラの動きを用いた動き補償の検討 第14回 回路とシステム(軽井沢)ワークショップ論文集, 525-530 第14回 回路とシステム(軽井沢)ワークショップ論文集, 525-530 , 525-530 2001/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
T. Shibayama, K. Kobayashi, H. Onodera 柴山武英、小林和淑、小野寺秀俊 T. Shibayama, K. Kobayashi, H. Onodera A Semi-Syncronous Multi-Clock One-Dimensional PE Array for Motion Estimation 動きベクトル検出用準同期一次元PEアレイの設計 A Semi-Syncronous Multi-Clock One-Dimensional PE Array for Motion Estimation Technival Report of IEICE., ICD2000-208, 33-38 電子情報通信学会技術研究報告, ICD2000-208, 33-38 Technival Report of IEICE., ICD2000-208, 33-38 2001/03/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
X. Li, K. Kobayashi, H. Onodera 李翔、小林和淑、小野寺秀俊 X. Li, K. Kobayashi, H. Onodera An Investigation of Delay Fluctuation in Logic-Gate with using an EB-Tester EBテスタを用いた論理ゲート遅延ばらつき測定手法の検討 An Investigation of Delay Fluctuation in Logic-Gate with using an EB-Tester IEICE Technical Report, VLD-2000-73, 23-28 電子情報通信学会技術研究報告, VLD-2000-73, 23-28 IEICE Technical Report, VLD-2000-73, 23-28 2000/11/30 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岩橋卓也、柴山武英、李翔、中西龍太、高井幸輔、小林和淑、小野寺秀俊 岩橋卓也、柴山武英、李翔、中西龍太、高井幸輔、小林和淑、小野寺秀俊 低ビットレートに適した動画像圧縮-ベクトル量子化による動画像圧縮とカメラベクトルによる動き補償- 低ビットレートに適した動画像圧縮-ベクトル量子化による動画像圧縮とカメラベクトルによる動き補償- 第4回システムLSI琵琶湖ワークショップ 講演資料集およびポスター資料集, 251-254 第4回システムLSI琵琶湖ワークショップ 講演資料集およびポスター資料集, 251-254 , 251-254 2000/11/27 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
橋本昌宜、小野寺秀俊 橋本昌宜、小野寺秀俊 セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法 セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法 情報処理学会DAシンポジウム2000年論文集, 185-190 情報処理学会DAシンポジウム2000年論文集, 185-190 , 185-190 2000/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤田智弘、小野寺秀俊 藤田智弘、小野寺秀俊 ベクトル合成モデルによる集積回路遅延特性のワーストケース解析 ベクトル合成モデルによる集積回路遅延特性のワーストケース解析 情報処理学会論文誌, 41, 4, 927-934 情報処理学会論文誌, 41, 4, 927-934 , 41, 4, 927-934 2000/04 Refereed Japanese Research paper(scientific journal) Disclose to all
橋本昌宜、小野寺秀俊 橋本昌宜、小野寺秀俊 静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法 静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法 第13回 回路とシステム(軽井沢)ワークショップ, 137-142 第13回 回路とシステム(軽井沢)ワークショップ, 137-142 , 137-142 2000/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤田智弘、小野寺秀俊 藤田智弘、小野寺秀俊 アナログ集積回路の階層的歩留まり最適化手法 アナログ集積回路の階層的歩留まり最適化手法 第13回 回路とシステム軽井沢ワークショップ論文集, 187-192 第13回 回路とシステム軽井沢ワークショップ論文集, 187-192 , 187-192 2000/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Sibayama, Sho Li, Hidetoshi Onodera 小林和淑、江口真、岩橋卓也、柴山武英、李翔、小野寺秀俊 Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Sibayama, Sho Li, Hidetoshi Onodera A Design Environment for a Vector-pipeline Processor ベクトル並列信号処理プロセッサ(VP-DSP)における設計環境 A Design Environment for a Vector-pipeline Processor IEICE Technical Report, 99, 658, 23-30-30 電子情報通信学会技術研究報告, 99, 658, 23-30-30 IEICE Technical Report, 99, 658, 23-30-30 2000/03/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera 橋本昌宜、橋本鉄太郎、西川亮太、福田大輔、黒田慎介、菅俊介、神原弘之、小野寺秀俊 Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera Design Optimization of System LSIs using On-Demand Libraries オンデマンドライブラリを用いたシステムLSI詳細設計手法 Design Optimization of System LSIs using On-Demand Libraries IEICE Technical Report, 99, 660, 31-38-38 電子情報通信学会技術研究報告, 99, 660, 31-38-38 IEICE Technical Report, 99, 660, 31-38-38 2000/03/02 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera 橋本昌宜、橋本鉄太郎、西川亮太、福田大輔、黒田慎介、菅俊介、神原弘之、小野寺秀俊 Masanori Hashimoto, Tetsutaro Hashimoto, Ryota Nishikawa, Daisuke Fukuda, Shinsuke Kuroda, Syunsuke Suga, Hiroyuki Kanbara, Hidetoshi Onodera オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 オンデマンドライブラリを用いたシステムLSI詳細設計手法 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 第3回システムLSI琵琶湖ワークショップ予稿集, 279-281 1999/11/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岩橋卓也、江口真、柴山武英、 李翔、坂口知靖、高井 幸輔、小林和淑、小野寺秀俊 岩橋卓也、江口真、柴山武英、 李翔、坂口知靖、高井 幸輔、小林和淑、小野寺秀俊 実時間動画像圧縮伸長用ベクトル並列信号処理プロセッサVP-DSPの開発 実時間動画像圧縮伸長用ベクトル並列信号処理プロセッサVP-DSPの開発 第3回システムLSI琵琶湖ワークショップ予稿集, 275-278 第3回システムLSI琵琶湖ワークショップ予稿集, 275-278 , 275-278 1999/11/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤田智弘,小野寺秀俊,田丸啓吉 藤田智弘,小野寺秀俊,田丸啓吉 現実的ワーストケースにおけるセルライブラリ遅延特性評価 現実的ワーストケースにおけるセルライブラリ遅延特性評価 DAシンポジウム '99 論文集, 59-64 DAシンポジウム '99 論文集, 59-64 , 59-64 1999/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺秀俊、平田昭夫、北村晃男、小林和淑、田丸啓吉 小野寺秀俊、平田昭夫、北村晃男、小林和淑、田丸啓吉 P2Lib:スタンダードセルライブラリ自動生成システム(共著) P2Lib:スタンダードセルライブラリ自動生成システム(共著) 情報処理学会論文誌, 40, 4, 1660-1669 情報処理学会論文誌, 40, 4, 1660-1669 , 40, 4, 1660-1669 1999/04 Refereed Japanese Research paper(scientific journal) Disclose to all
平田昭夫、近藤友一、小野寺秀俊、田丸啓吉 平田昭夫、近藤友一、小野寺秀俊、田丸啓吉 抵抗分を含む負荷を駆動するCMOS論理回路のゲート遅延時間計算手法 抵抗分を含む負荷を駆動するCMOS論理回路のゲート遅延時間計算手法 情報処理学会論文誌, 40, 4, 1679-1686 情報処理学会論文誌, 40, 4, 1679-1686 , 40, 4, 1679-1686 1999/04 Refereed Japanese Research paper(scientific journal) Disclose to all
橋本 昌宜;小野寺 秀俊;田丸 啓吉 橋本 昌宜;小野寺 秀俊;田丸 啓吉 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 (<特集>電子システムの設計技術と設計自動化) グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 (<特集>電子システムの設計技術と設計自動化) 情報処理学会論文誌, 40, 4, 1707-1716 情報処理学会論文誌, 40, 4, 1707-1716 , 40, 4, 1707-1716 1999/04 Refereed Japanese Research paper(scientific journal) Disclose to all
橋本鉄太郎、平田昭夫、小野寺秀俊、田丸啓吉 橋本鉄太郎、平田昭夫、小野寺秀俊、田丸啓吉 スタンダードセルライブラリ構成法の検討 スタンダードセルライブラリ構成法の検討 第12回 回路とシステム(軽井沢)ワークショップ, 337-342 第12回 回路とシステム(軽井沢)ワークショップ, 337-342 , 337-342 1999/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤田智弘,岡田健一,藤田浩章,小野寺秀俊,田丸啓吉 藤田智弘,岡田健一,藤田浩章,小野寺秀俊,田丸啓吉 システム特性の階層的統計解析手法 システム特性の階層的統計解析手法 第12回 回路とシステム(軽井沢)ワークショップ論文集,199-204,, 199-204 第12回 回路とシステム(軽井沢)ワークショップ論文集,199-204,, 199-204 , 199-204 1999/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小林和淑、神原弘之、小野寺秀俊、田丸啓吉 小林和淑、神原弘之、小野寺秀俊、田丸啓吉 FPGA設計用統合環境を用いたASIC設計事例 FPGA設計用統合環境を用いたASIC設計事例 電子情報通信学会技術研究報告 電子情報通信学会技術研究報告 1998/12/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
藤田智弘、岡田健一、藤田浩章、小野寺秀俊、田丸啓吉 藤田智弘、岡田健一、藤田浩章、小野寺秀俊、田丸啓吉 微細化プロセスによるばらつきを考慮した統計的設計環境の開発 微細化プロセスによるばらつきを考慮した統計的設計環境の開発 第2回システムLSI琵琶湖ワークショップポスター資料集, 297-299 第2回システムLSI琵琶湖ワークショップポスター資料集, 297-299 , 297-299 1998/11/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
平田昭夫、近藤友一、小野寺秀俊、田丸啓吉 平田昭夫、近藤友一、小野寺秀俊、田丸啓吉 抵抗分を含む負荷を駆動するCMOS論理回路の等価モデルとゲート遅延時間の解析 抵抗分を含む負荷を駆動するCMOS論理回路の等価モデルとゲート遅延時間の解析 情報処理学会DAシンポジウム’98論文集, 13-18 情報処理学会DAシンポジウム’98論文集, 13-18 , 13-18 1998/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
橋本昌宜、小野寺秀俊、田丸啓吉 橋本昌宜、小野寺秀俊、田丸啓吉 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 情報処理学会DAシンポジウム’98論文集, 269-274 情報処理学会DAシンポジウム’98論文集, 269-274 , 269-274 1998/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岡田健一、小野寺秀俊、田丸啓吉 岡田健一、小野寺秀俊、田丸啓吉 レイアウトを考慮したCMOS回路の比精度解析 レイアウトを考慮したCMOS回路の比精度解析 第11回回路とシステム軽井沢ワークショップ論文集, 409-414 第11回回路とシステム軽井沢ワークショップ論文集, 409-414 , 409-414 1998/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
森江隆史;小野寺秀俊;田丸啓吉 森江隆史;小野寺秀俊;田丸啓吉 アナログ回路設計方法の再利用率向上手法  設計制約とパラメータの確信度の保存と再利用 アナログ回路設計方法の再利用率向上手法  設計制約とパラメータの確信度の保存と再利用 電子情報通信学会論文誌 A, J81-A, 3, 397-407 電子情報通信学会論文誌 A, J81-A, 3, 397-407 , J81-A, 3, 397-407 1998/03 Refereed Japanese Research paper(scientific journal) Disclose to all
小林和淑、武内昌弘、寺田和彦、小野寺秀俊、田丸啓吉 小林和淑、武内昌弘、寺田和彦、小野寺秀俊、田丸啓吉 ベクトル量子化を用いた低ビットレート動画像圧縮システム ベクトル量子化を用いた低ビットレート動画像圧縮システム 第1回システムLSI琵琶湖ワークショップ資料集, 365-370 第1回システムLSI琵琶湖ワークショップ資料集, 365-370 , 365-370 1997/11/20 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
近藤正樹、藤田智弘、岡田健一、小野寺秀俊、田丸啓吉 近藤正樹、藤田智弘、岡田健一、小野寺秀俊、田丸啓吉 MOS集積回路の統計的モデル化手法 MOS集積回路の統計的モデル化手法 第1回システムLSI琵琶湖ワークショップ資料集, 437-442 第1回システムLSI琵琶湖ワークショップ資料集, 437-442 , 437-442 1997/11/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
近藤正樹、小野寺秀俊、田丸啓吉 近藤正樹、小野寺秀俊、田丸啓吉 中間モデルを用いたMOSFETの統計的モデル化手法 中間モデルを用いたMOSFETの統計的モデル化手法 電子情報通信学会技術報告, ICD97-146, 89-96 電子情報通信学会技術報告, ICD97-146, 89-96 , ICD97-146, 89-96 1997/09/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小林和淑、中村典嗣、山岡雅直、小野寺秀俊、田丸啓吉 小林和淑、中村典嗣、山岡雅直、小野寺秀俊、田丸啓吉 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQ64の設計 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQ64の設計 DAシンポジウム '97論文集, 13-18 DAシンポジウム '97論文集, 13-18 , 13-18 1997/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
橋本昌宜、小野寺秀俊、田丸啓吉 橋本昌宜、小野寺秀俊、田丸啓吉 入力端子接続最適化による消費電力削減手法 入力端子接続最適化による消費電力削減手法 情報処理学会 DAシンポジウム '97 論文集, 99-104 情報処理学会 DAシンポジウム '97 論文集, 99-104 , 99-104 1997/07 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺秀俊、平田昭夫、北村晃男、田丸啓吉 小野寺秀俊、平田昭夫、北村晃男、田丸啓吉 P2Lib: スタンダードセルライブラリ自動生成システム P2Lib: スタンダードセルライブラリ自動生成システム 情報処理学会研究報告, 97, 50, 97DA84-6, 33-44 情報処理学会研究報告, 97, 50, 97DA84-6, 33-44 , 97, 50, 97DA84-6, 33-44 1997/05/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
武内昌弘、寺田一彦、中村典嗣、小林和淑、小野寺秀俊、田丸啓吉 武内昌弘、寺田一彦、中村典嗣、小林和淑、小野寺秀俊、田丸啓吉 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQによる動画像の低ビットレート圧縮アルゴリズムの提案 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQによる動画像の低ビットレート圧縮アルゴリズムの提案 第10回回路とシステム軽井沢ワークショップ講演論文集, 291-296 第10回回路とシステム軽井沢ワークショップ講演論文集, 291-296 , 291-296 1997/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
平田昭夫、小野寺秀俊、田丸啓吉 平田昭夫、小野寺秀俊、田丸啓吉 CRCπ型負荷を駆動するCMOS論理ゲートにおける貫通電流による消費電力及び出力波形の導出 CRCπ型負荷を駆動するCMOS論理ゲートにおける貫通電流による消費電力及び出力波形の導出 第10回回路とシステム軽井沢ワークショップ講演論文集, 445-450 第10回回路とシステム軽井沢ワークショップ講演論文集, 445-450 , 445-450 1997/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
近藤正樹、小野寺秀俊、田丸啓吉 近藤正樹、小野寺秀俊、田丸啓吉 高精度アナログ素子を用いない電流モード循環型A/D変換回路 高精度アナログ素子を用いない電流モード循環型A/D変換回路 情報処理学会 DA シンポジウム '96 論文集, 31-34 情報処理学会 DA シンポジウム '96 論文集, 31-34 , 31-34 1996/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 高精度アナログ素子を用いない電流モード循環型A/D変換回路(共著) 高精度アナログ素子を用いない電流モード循環型A/D変換回路(共著) 情報処理学会DAシンポジウム'96論文集,96/4,31-34 情報処理学会DAシンポジウム'96論文集,96/4,31-34 1996/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小林和淑、木下雅善、清水友人、武内昌弘、小野寺秀俊、田丸啓吉 小林和淑、木下雅善、清水友人、武内昌弘、小野寺秀俊、田丸啓吉 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQの設計 ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQの設計 回路とシステム軽井沢ワークショップ論文集, 353-358 回路とシステム軽井沢ワークショップ論文集, 353-358 , 353-358 1996/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
古沢慎也、モシニャガ ワシリー、小野寺秀俊、田丸啓吉 古沢慎也、モシニャガ ワシリー、小野寺秀俊、田丸啓吉 演算器共有・選択を考慮したパイプラインデータパスの合成手法 演算器共有・選択を考慮したパイプラインデータパスの合成手法 電子情報通信学会技術研究報告, VLD95-135, ICD95-235, 45-52 電子情報通信学会技術研究報告, VLD95-135, ICD95-235, 45-52 , VLD95-135, ICD95-235, 45-52 1996/03/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岡田和久、小野寺秀俊、田丸啓吉 岡田和久、小野寺秀俊、田丸啓吉 抵抗アレイモデルを用いたアナログ回路用概略配線 抵抗アレイモデルを用いたアナログ回路用概略配線 情報処理学会 設計自動化研究会79-8, 43-48 情報処理学会 設計自動化研究会79-8, 43-48 , 43-48 1996/02/09 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
近藤正樹;小野寺秀俊;田丸啓吉 近藤正樹;小野寺秀俊;田丸啓吉 中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法 中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法 電子情報通信学会論文誌 A, 78, 9, 1133-1141 電子情報通信学会論文誌 A, 78, 9, 1133-1141 , 78, 9, 1133-1141 1995/09 Refereed Japanese Research paper(scientific journal) Disclose to all
Guangqiu Chen, Hidetoshi Onodera, and Keikichi Tamaru Guangqiu Chen, Hidetoshi Onodera, and Keikichi Tamaru Guangqiu Chen, Hidetoshi Onodera, and Keikichi Tamaru A Gate Sizing Approach with Accurate Delay Evaluation A Gate Sizing Approach with Accurate Delay Evaluation A Gate Sizing Approach with Accurate Delay Evaluation Proc. of the 8th Circuits and Systems Karuizawa Workshop, 239-244 第8回 回路とシステム軽井沢ワークショップ論文集, 239-244 Proc. of the 8th Circuits and Systems Karuizawa Workshop, 239-244 1995/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
平田昭夫、小野寺秀俊、田丸啓吉 平田昭夫、小野寺秀俊、田丸啓吉 CMOS論理ゲートにおける貫通電流による消費電力の定式化 CMOS論理ゲートにおける貫通電流による消費電力の定式化 第8回 回路とシステム軽井沢ワークショップ論文集, 245-250 第8回 回路とシステム軽井沢ワークショップ論文集, 245-250 , 245-250 1995/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
G. Chen, H. Onodera, and K. Tamrau G. Chen, H. Onodera, and K. Tamrau G. Chen, H. Onodera, and K. Tamrau The Area-Power-Delay Tradeoff in Gate Sizing The Area-Power-Delay Tradeoff in Gate Sizing The Area-Power-Delay Tradeoff in Gate Sizing DA Symposium, 187-192 DA Symposium, 187-192 DA Symposium, 187-192 1994/08 English Research paper(research society, symposium materials, etc.) Disclose to all
小野寺 秀俊 小野寺 秀俊 回路合成と最適化技術の動向と展望 回路合成と最適化技術の動向と展望 第7回 回路とシステム軽井沢ワークショップ論文集, 151-156 第7回 回路とシステム軽井沢ワークショップ論文集, 151-156 , 151-156 1994/04 Refereed Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小林和淑、竹村秀城、W. Jungsuwadee、小野寺秀俊、田丸啓吉 小林和淑、竹村秀城、W. Jungsuwadee、小野寺秀俊、田丸啓吉 ビット並列ブロック並列方式による機能メモリ型並列プロセッサの設計 ビット並列ブロック並列方式による機能メモリ型並列プロセッサの設計 電子情報通信学会技術研究報告, SDM93-145, ICD93-139, 37-44 電子情報通信学会技術研究報告, SDM93-145, ICD93-139, 37-44 , SDM93-145, ICD93-139, 37-44 1993/10/01 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
森江隆史;小野寺秀俊;田丸啓吉 森江隆史;小野寺秀俊;田丸啓吉 アナログ回路設計手順の保存・再利用化手法 アナログ回路設計手順の保存・再利用化手法 電子情報通信学会論文誌 A, 76, 10, 1457-1464 電子情報通信学会論文誌 A, 76, 10, 1457-1464 , 76, 10, 1457-1464 1993/10 Refereed Japanese Research paper(scientific journal) Disclose to all
岡田和久, 小野寺秀俊, 田丸啓吉 岡田和久, 小野寺秀俊, 田丸啓吉 レイアウト要素の形状自由度を考慮したコンパクション手法 レイアウト要素の形状自由度を考慮したコンパクション手法 情報処理学会 DAシンポジウム '93 論文集, 33-36 情報処理学会 DAシンポジウム '93 論文集, 33-36 , 33-36 1993/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
岡田和久, 小野寺秀俊, 田丸啓吉 岡田和久, 小野寺秀俊, 田丸啓吉 レイアウト要素の形状自由度を考慮したコンパクション手法 レイアウト要素の形状自由度を考慮したコンパクション手法 情報処理学会DAシンポジウム'92論文集, 33-36 情報処理学会DAシンポジウム'92論文集, 33-36 , 33-36 1993/04 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
小野寺秀俊;谷口陽;田丸啓吉 小野寺秀俊;谷口陽;田丸啓吉 ビルディングブロックレイアウトのための分枝限定配置手法 ビルディングブロックレイアウトのための分枝限定配置手法 電子情報通信学会論文誌 A, 75, 9, 1487-1495 電子情報通信学会論文誌 A, 75, 9, 1487-1495 , 75, 9, 1487-1495 1992/09 Refereed Japanese Research paper(scientific journal) Disclose to all
森江隆史,小野寺秀俊,田丸啓吉 森江隆史,小野寺秀俊,田丸啓吉 アナログ回路設計手順の保存と再利用化の手法 アナログ回路設計手順の保存と再利用化の手法 情報処理学会 DAシンポジウム '92 論文集, 129-132 情報処理学会 DAシンポジウム '92 論文集, 129-132 , 129-132 1992/08 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
音羽克則・安田岳雄・小野寺秀俊・田丸啓吉 音羽克則・安田岳雄・小野寺秀俊・田丸啓吉 CMOSオペアンプ自動設計システムOACにおける自動回路設計手法-回路構造と素子概略値の決定- CMOSオペアンプ自動設計システムOACにおける自動回路設計手法-回路構造と素子概略値の決定- 電子情報通信学会論文誌A, J74-A, 2, 277-286 電子情報通信学会論文誌A, J74-A, 2, 277-286 , J74-A, 2, 277-286 1991/02 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊 小野寺秀俊 アナログ回路の合成と最適化 アナログ回路の合成と最適化 電子情報通信学会論文誌 A, 74, 2, 179-186 電子情報通信学会論文誌 A, 74, 2, 179-186 , 74, 2, 179-186 1991/02 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊;神原弘之;田丸啓吉 小野寺秀俊;神原弘之;田丸啓吉 OAC:CMOSオペアンプ自動設計システム システム概要と評価 OAC:CMOSオペアンプ自動設計システム システム概要と評価 電子情報通信学会論文誌 A, 73, 1, 67-76 電子情報通信学会論文誌 A, 73, 1, 67-76 , 73, 1, 67-76 1990/01 Refereed Japanese Research paper(scientific journal) Disclose to all
坂本守;小野寺秀俊;田丸啓吉 坂本守;小野寺秀俊;田丸啓吉 シフトコンパクション  シンボリックレイアウトの擬2次元的コンパクション手法 シフトコンパクション  シンボリックレイアウトの擬2次元的コンパクション手法 電子情報通信学会論文誌 A, 72, 8, 1277-1286 電子情報通信学会論文誌 A, 72, 8, 1277-1286 , 72, 8, 1277-1286 1989/08 Refereed Japanese Research paper(scientific journal) Disclose to all
奥田亮輔;小野寺秀俊;田丸啓吉 奥田亮輔;小野寺秀俊;田丸啓吉 HILDS  プロセス変更に耐える階層的シンボリックレイアウトシステム HILDS  プロセス変更に耐える階層的シンボリックレイアウトシステム 電子情報通信学会論文誌 A, 72, 3, 561-569 電子情報通信学会論文誌 A, 72, 3, 561-569 , 72, 3, 561-569 1989/03 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊;田丸啓吉 小野寺秀俊;田丸啓吉 力学モデルに基づくブロック配置手法 力学モデルに基づくブロック配置手法 電子情報通信学会論文誌 A, 72, 1, 105-113 電子情報通信学会論文誌 A, 72, 1, 105-113 , 72, 1, 105-113 1989/01 Refereed Japanese Research paper(scientific journal) Disclose to all
奥田亮輔;小野寺秀俊;田丸啓吉 奥田亮輔;小野寺秀俊;田丸啓吉 回路とレイアウトを対応づけたデータ表現とそれを用いたレイアウト設計手法 回路とレイアウトを対応づけたデータ表現とそれを用いたレイアウト設計手法 電子情報通信学会論文誌 A, 71, 12, 2156-2162 電子情報通信学会論文誌 A, 71, 12, 2156-2162 , 71, 12, 2156-2162 1988/12 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊・立石哲夫・田丸啓吉 小野寺秀俊・立石哲夫・田丸啓吉 循環型スイッチトキャパシタA-D,D-A変換器 循環型スイッチトキャパシタA-D,D-A変換器 電子通信学会論文誌C, 69, 10, 1359-1366 電子通信学会論文誌C, 69, 10, 1359-1366 , 69, 10, 1359-1366 1986/10 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊・粟井郁男・中島将光・池上淳一 小野寺秀俊・粟井郁男・中島将光・池上淳一 Nb<sub>2</sub>O<sub>5</sub>薄膜-LiTaO<sub>3</sub>基板導波路における導波-放射モード結合光変調器の実験 Nb<sub>2</sub>O<sub>5</sub>薄膜-LiTaO<sub>3</sub>基板導波路における導波-放射モード結合光変調器の実験 電子通信学会論文誌, J64-C, 1, 170-171 電子通信学会論文誌, J64-C, 1, 170-171 , J64-C, 1, 170-171 1984/01 Refereed Japanese Research paper(scientific journal) Disclose to all
小野寺秀俊・中島将光・粟井郁男・池上淳一 小野寺秀俊・中島将光・粟井郁男・池上淳一 高変調度導波-放射モード結合型光変調器の解析(共著) 高変調度導波-放射モード結合型光変調器の解析(共著) 電子通信学会論文誌C, J64-C, 4, 288-295 電子通信学会論文誌C, J64-C, 4, 288-295 , J64-C, 4, 288-295 1981/04 Refereed Japanese Research paper(scientific journal) Disclose to all
塩見凖、石原亨、小野寺秀俊 塩見凖、石原亨、小野寺秀俊 複数電源ドメインの実行時電圧制御によるCMOS LSIの消費エネルギー最小化 複数電源ドメインの実行時電圧制御によるCMOS LSIの消費エネルギー最小化 DAシンポジウム2018, 160-165 DAシンポジウム2018, 160-165 , 160-165 Japanese Research paper(research society, symposium materials, etc.) Disclose to all
Shengyu Liu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera Shengyu Liu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera Shengyu Liu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors DA Symposium 2018, 166-171 DA Symposium 2018, 166-171 DA Symposium 2018, 166-171 English Research paper(research society, symposium materials, etc.) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E98-A, 7, 1455-1466 , E98-A, 7, 1455-1466 IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E98-A, 7, 1455-1466 2015/07 Refereed English Research paper(scientific journal) Disclose to all
N. Kamae, A. Tsuchiya, H. Onodera N. Kamae, A. Tsuchiya, H. Onodera A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage IEICE TRANSACTIONS on Electronics, 98-C, 6, 504-511 , 98-C, 6, 504-511 IEICE TRANSACTIONS on Electronics, 98-C, 6, 504-511 2015/06 Refereed English Research paper(scientific journal) Disclose to all
K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS IEEE Transactions on Circuits and Systems I, 62, 5, 1288-1295 , 62, 5, 1288-1295 IEEE Transactions on Circuits and Systems I, 62, 5, 1288-1295 2015/05 Refereed English Research paper(scientific journal) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation 16th International Symposium on Quality Electronic Design (ISQED), 23-28 , 23-28 16th International Symposium on Quality Electronic Design (ISQED), 23-28 2015/03 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M.Mahfuzul Islam, Hidetoshi Onodera A.K.M.Mahfuzul Islam, Hidetoshi Onodera Sensitivity-independent Extraction of Vth Variation Utilizing Log-normal Delay Distribution Sensitivity-independent Extraction of Vth Variation Utilizing Log-normal Delay Distribution Proceedings of the 2015 IEEE International Conference on Microelectronic Test Structures, 212-217 , 212-217 Proceedings of the 2015 IEEE International Conference on Microelectronic Test Structures, 212-217 2015/03 Refereed English Research paper(international conference proceedings) Disclose to all
N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera Energy reduction by built-in body biasing with single supply voltage operation Energy reduction by built-in body biasing with single supply voltage operation International Symposium on Quality Electronic Devices, 181-185 , 181-185 International Symposium on Quality Electronic Devices, 181-185 2015/03 Refereed English Research paper(international conference proceedings) Disclose to all
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 87-93 , 87-93 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 87-93 2015/01 Refereed English Research paper(international conference proceedings) Disclose to all
Bishnu Prasad Das and Hidetoshi Onodera Bishnu Prasad Das and Hidetoshi Onodera Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs IEEE Transactions on Very Large Scale Integration (VLSI) Sytems, 22, 12, 2535-2548 , 22, 12, 2535-2548 IEEE Transactions on Very Large Scale Integration (VLSI) Sytems, 22, 12, 2535-2548 2014/12 Refereed English Research paper(scientific journal) Disclose to all
Hiroaki Kounoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Hasanori Hashimoto, Takao Onoye, Hidetoshi Onodera Hiroaki Kounoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Hasanori Hashimoto, Takao Onoye, Hidetoshi Onodera Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing IEICE Trans. Fundamentals, E97-A, 12, 2518-2529 , E97-A, 12, 2518-2529 IEICE Trans. Fundamentals, E97-A, 12, 2518-2529 2014/12 Refereed English Research paper(scientific journal) Disclose to all
Yukio Mitsuyama, Hidetoshi Onodera Yukio Mitsuyama, Hidetoshi Onodera Variability and Soft-error Resilience in Dependable VLSI Platform Variability and Soft-error Resilience in Dependable VLSI Platform 2014 IEEE 23rd Asian Test Symposium, 45-50 , 45-50 2014 IEEE 23rd Asian Test Symposium, 45-50 2014/11 Refereed English Research paper(international conference proceedings) Disclose to all
N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation IEEE Asian Solid-State Circuits Conference, 53-56 , 53-56 IEEE Asian Solid-State Circuits Conference, 53-56 2014/11 Refereed English Research paper(international conference proceedings) Disclose to all
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation IEEE International System-On-Chip Conference, 17-22 , 17-22 IEEE International System-On-Chip Conference, 17-22 2014/09 Refereed English Research paper(international conference proceedings) Disclose to all
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation IEEE International System-On-Chip Conference, 42-47 , 42-47 IEEE International System-On-Chip Conference, 42-47 2014/09 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability 2014 IEEE Proceedings of the Custom Integrated Circuits Conference 2014 IEEE Proceedings of the Custom Integrated Circuits Conference 2014/09 Refereed English Research paper(international conference proceedings) Disclose to all
K.Zhang, J.Furuta, K.Kobayashi, H.Onodera K.Zhang, J.Furuta, K.Kobayashi, H.Onodera Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process IEEE Transactions on Nuclear Science, 61, 4 part1, 1583-1589 , 61, 4 part1, 1583-1589 IEEE Transactions on Nuclear Science, 61, 4 part1, 1583-1589 2014/08 Refereed English Research paper(scientific journal) Disclose to all
K.Kobayashi, K.Kubota, M.Masuda, Y.Manzawa, J.Furuta, S.Kanda, H.Onodera K.Kobayashi, K.Kubota, M.Masuda, Y.Manzawa, J.Furuta, S.Kanda, H.Onodera A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI IEEE Transaction on Nuclear Science, 61, 4 part1, 1881-1888 , 61, 4 part1, 1881-1888 IEEE Transaction on Nuclear Science, 61, 4 part1, 1881-1888 2014/08 Refereed English Research paper(scientific journal) Disclose to all
K. Kishine, H. Inoue, H. Inaba, M. Nakamura, A. Tsuchiya, H. Onodera, H. Katsurai K. Kishine, H. Inoue, H. Inaba, M. Nakamura, A. Tsuchiya, H. Onodera, H. Katsurai A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops IEEE International Symposium on Circuits and Systems, 2704-2707 , 2704-2707 IEEE International Symposium on Circuits and Systems, 2704-2707 2014/06 Refereed English Research paper(international conference proceedings) Disclose to all
S. Kim; A. Tsuchiya; H. Onodera S. Kim; A. Tsuchiya; H. Onodera Radiation-hardened PLL with a switchable dual modular redundancy structure Radiation-hardened PLL with a switchable dual modular redundancy structure IEICE Transactions on Electronics, E97-C, 4, 325-331 , E97-C, 4, 325-331 IEICE Transactions on Electronics, E97-C, 4, 325-331 2014/04 Refereed English Research paper(scientific journal) Disclose to all
A.K.M. Mahfuzul Islam, and Hidetoshi Onodera A.K.M. Mahfuzul Islam, and Hidetoshi Onodera Characterization and compensation of performance variability using on-chip monitors Characterization and compensation of performance variability using on-chip monitors 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 19-22 , 19-22 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 19-22 2014/04 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam and Hidetoshi Onodera A.K.M. Mahfuzul Islam and Hidetoshi Onodera Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations Japanese Journal of Applied Physics, 53, 4S, 04EE08-1-04EE08-8 , 53, 4S, 04EE08-1-04EE08-8 Japanese Journal of Applied Physics, 53, 4S, 04EE08-1-04EE08-8 2014/04 Refereed English Research paper(scientific journal) Disclose to all
S. Kim; A. Tsuchiya; H. Onodera S. Kim; A. Tsuchiya; H. Onodera Analysis of radiation-induced clock-perturbation in phase-locked loop Analysis of radiation-induced clock-perturbation in phase-locked loop IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97-A, 3, 768-776 , E97-A, 3, 768-776 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97-A, 3, 768-776 2014/03 Refereed English Research paper(scientific journal) Disclose to all
N. Kamae; A. Tsuchiya; H. Onodera N. Kamae; A. Tsuchiya; H. Onodera A body bias generator with low supply voltage forwithin-die variability compensation A body bias generator with low supply voltage forwithin-die variability compensation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97-A, 3, 734-740 , E97-A, 3, 734-740 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97-A, 3, 734-740 2014/03 Refereed English Research paper(scientific journal) Disclose to all
Tomohiro Fujita, SinNyoung Kim, and Hidetoshi Onodera Tomohiro Fujita, SinNyoung Kim, and Hidetoshi Onodera Computer Simulation of Radiation-Induced Clock-Perturbation in Phase-Locked Loop with Analog Behavioral Model Computer Simulation of Radiation-Induced Clock-Perturbation in Phase-Locked Loop with Analog Behavioral Model Proceedings of 15th International Symposium on Quality Electronic Design(ISQED) Proceedings of 15th International Symposium on Quality Electronic Design(ISQED) 2014/03 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, and Hidetoshi Onodera A.K.M. Mahfuzul Islam, and Hidetoshi Onodera In-Situ Variability Characterization of Individual Transistors Using Topology-Reconfigurable Ring Oscillators In-Situ Variability Characterization of Individual Transistors Using Topology-Reconfigurable Ring Oscillators International Conference on Microelectronic Test Structures, 121 , 121 International Conference on Microelectronic Test Structures, 121 2014/03 Refereed English Research paper(international conference proceedings) Disclose to all
Bishnu Prasad Das, Hidetoshi Onodera Bishnu Prasad Das, Hidetoshi Onodera On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator IEEE Transactions on Circuits and Systems II, 61, 3, 183-187 , 61, 3, 183-187 IEEE Transactions on Circuits and Systems II, 61, 3, 183-187 2014/03 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai, 106-107 , 106-107 IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai, 106-107 2013/12 Refereed English Research paper(international conference proceedings) Disclose to all
S. Nishizawa; T. Ishihara; H. Onodera S. Nishizawa; T. Ishihara; H. Onodera Standard cell structure with flexible P/N well boundaries for near-threshold voltage operation Standard cell structure with flexible P/N well boundaries for near-threshold voltage operation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96-A, 12, 2499-2507 , E96-A, 12, 2499-2507 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96-A, 12, 2499-2507 2013/12 Refereed English Research paper(scientific journal) Disclose to all
A.K.M.M. Islam; T. Ishihara; H. Onodera A.K.M.M. Islam; T. Ishihara; H. Onodera Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 125-128 , 125-128 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 125-128 2013/11 Refereed English Research paper(international conference proceedings) Disclose to all
D. Alnajjar; H. Konoura; Y. Mitsuyama; H. Shimada; K. Kobayashi; H. Kanbara; H. Ochi; T. Imagawa; S. Noda; K. Wakabayashi; M. Hashimoto; T. Onoye; H. Onodera D. Alnajjar; H. Konoura; Y. Mitsuyama; H. Shimada; K. Kobayashi; H. Kanbara; H. Ochi; T. Imagawa; S. Noda; K. Wakabayashi; M. Hashimoto; T. Onoye; H. Onodera Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 313-316 , 313-316 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 313-316 2013/11 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam; H. Onodera A.K.M. Mahfuzul Islam; H. Onodera On-chip detection of process shift and process spread for post-silicon diagnosis and model-hardware correlation On-chip detection of process shift and process spread for post-silicon diagnosis and model-hardware correlation IEICE Transactions on Information and Systems, E96-D, 9, 1971-1979 , E96-D, 9, 1971-1979 IEICE Transactions on Information and Systems, E96-D, 9, 1971-1979 2013/09 Refereed English Research paper(scientific journal) Disclose to all
M. Kondo; S. Nishizawa; T. Ishihara; H. Onodera M. Kondo; S. Nishizawa; T. Ishihara; H. Onodera A standard cell optimization method for near-threshold voltage operations A standard cell optimization method for near-threshold voltage operations Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 7606, 32-41 , 7606, 32-41 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 7606, 32-41 2013/09 Refereed English Research paper(international conference proceedings) Disclose to all
A.K.M. Mahfuzul Islam, and Hidetoshi Onodera A.K.M. Mahfuzul Islam, and Hidetoshi Onodera Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations International Conference on Solid State Devices and Materials International Conference on Solid State Devices and Materials 2013/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera; Y.K. Cao H. Onodera; Y.K. Cao AMS verification in advanced technologies AMS verification in advanced technologies Proceedings of the Custom Integrated Circuits Conference Proceedings of the Custom Integrated Circuits Conference 2013/09 Refereed English Research paper(international conference proceedings) Disclose to all
S.N. Kim; A. Tsuchiya; H. Onodera S.N. Kim; A. Tsuchiya; H. Onodera Perturbation-immune radiation-hardened PLL with a switchable DMR structure Perturbation-immune radiation-hardened PLL with a switchable DMR structure Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013, 128-132 , 128-132 Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013, 128-132 2013/09 Refereed English Research paper(international conference proceedings) Disclose to all
S. Fujimoto; A.K.M. Mahfuzul Islam; T. Matsumoto; H. Onodera S. Fujimoto; A.K.M. Mahfuzul Islam; T. Matsumoto; H. Onodera Inhomogeneous ring oscillator for within-die variability and RTN characterization Inhomogeneous ring oscillator for within-die variability and RTN characterization IEEE Transactions on Semiconductor Manufacturing, 26, 3, 296-305 , 26, 3, 296-305 IEEE Transactions on Semiconductor Manufacturing, 26, 3, 296-305 2013/08 Refereed English Research paper(scientific journal) Disclose to all
S. Nishizawa; H. Onodera S. Nishizawa; H. Onodera A ring oscillator with calibration circuit for on-chip measurement of static IR-drop A ring oscillator with calibration circuit for on-chip measurement of static IR-drop IEEE Transactions on Semiconductor Manufacturing, 26, 3, 306-313 , 26, 3, 306-313 IEEE Transactions on Semiconductor Manufacturing, 26, 3, 306-313 2013/08 Refereed English Research paper(scientific journal) Disclose to all
M. Masuda, K. Kubota, R. Yamamoto(KIT), J. Furuta(Kyoto Univ.), K. Kobayashi(KIT), and H. Onodera(Kyoto Univ.) M. Masuda, K. Kubota, R. Yamamoto(KIT), J. Furuta(Kyoto Univ.), K. Kobayashi(KIT), and H. Onodera(Kyoto Univ.) A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop IEEE Trans. on Nuclear Science, vol.60, no.4, pp. 2750-2755, DOI: 10.1109/TNS.2013.2245344, 60, 4, 2750-2755 , 60, 4, 2750-2755 IEEE Trans. on Nuclear Science, vol.60, no.4, pp. 2750-2755, DOI: 10.1109/TNS.2013.2245344, 60, 4, 2750-2755 2013/08 Refereed English Research paper(scientific journal) Disclose to all
T. Amagai; A. Tsuchiya; S. Nakano; M. Nogawa; H. Koizumi; H. Onodera T. Amagai; A. Tsuchiya; S. Nakano; M. Nogawa; H. Koizumi; H. Onodera A slow-wave transmission line with thin pillars for millimeter-wave CMOS A slow-wave transmission line with thin pillars for millimeter-wave CMOS 2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013 2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013 2013/05 Refereed English Research paper(international conference proceedings) Disclose to all
K. Zhang; J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera K. Zhang; J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera A radiation-hard redundant flip-flop to suppress multiple cell upset by utilizing the parasitic bipolar effect A radiation-hard redundant flip-flop to suppress multiple cell upset by utilizing the parasitic bipolar effect IEICE Transactions on Electronics, E96-C, 4, 511-517 , E96-C, 4, 511-517 IEICE Transactions on Electronics, E96-C, 4, 511-517 2013/04 Refereed English Research paper(scientific journal) Disclose to all
T. Matsumoto; K. Kobayashi; H. Onodera T. Matsumoto; K. Kobayashi; H. Onodera Impact of body-biasing technique on random telegraph noise induced delay fluctuation Impact of body-biasing technique on random telegraph noise induced delay fluctuation Japanese Journal of Applied Physics, 52, 4 , 52, 4 Japanese Journal of Applied Physics, 52, 4 2013/04 Refereed English Research paper(scientific journal) Disclose to all
J. Furuta; K. Kobayashi; H. Onodera J. Furuta; K. Kobayashi; H. Onodera Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets IEEE International Reliability Physics Symposium Proceedings, 6C.3.1-6C.3.4 , 6C.3.1-6C.3.4 IEEE International Reliability Physics Symposium Proceedings, 6C.3.1-6C.3.4 2013/04 Refereed English Research paper(international conference proceedings) Disclose to all
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design Proc. of 2013 International Symposium on Quality Electronic Design (ISQED), pp.719-725, 703-708 , 703-708 Proc. of 2013 International Symposium on Quality Electronic Design (ISQED), pp.719-725, 703-708 2013/03 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera Effects of neutron-induced well potential perturbation for multiple cell upset of flip-flops in 65 nm Effects of neutron-induced well potential perturbation for multiple cell upset of flip-flops in 65 nm IEEE Transactions on Nuclear Science, 60, 1, 213-218 , 60, 1, 213-218 IEEE Transactions on Nuclear Science, 60, 1, 213-218 2013/02 Refereed English Research paper(scientific journal) Disclose to all
T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera A 25-Gb/s LD driver with area-effective inductor in a 0.18-μm CMOS A 25-Gb/s LD driver with area-effective inductor in a 0.18-μm CMOS Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 105-106 , 105-106 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 105-106 2013/01 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera Dependable VLSI platform using robust fabrics Dependable VLSI platform using robust fabrics Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 119-124 , 119-124 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 119-124 2013/01 Refereed English Research paper(international conference proceedings) Disclose to all
T. Matsumoto; K. Kobayashi; H. Onodera T. Matsumoto; K. Kobayashi; H. Onodera Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation Technical Digest - International Electron Devices Meeting, IEDM, 2012, 581-584 , 2012, 581-584 Technical Digest - International Electron Devices Meeting, IEDM, 2012, 581-584 2012/12 Refereed English Research paper(international conference proceedings) Disclose to all
Mahfuzul, Islam A. K. M.; Tsuchiya, Akira; Kobayashi, Kazutoshi; Onodera, Hidetoshi Mahfuzul, Islam A. K. M.; Tsuchiya, Akira; Kobayashi, Kazutoshi; Onodera, Hidetoshi Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 25, 4, 571-580 , 25, 4, 571-580 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 25, 4, 571-580 2012/11 Refereed English Research paper(scientific journal) Disclose to all
Das, B. P.; Onodera, H. Das, B. P.; Onodera, H. Area-efficient reconfigurable-array-based oscillator for standard cell characterisation Area-efficient reconfigurable-array-based oscillator for standard cell characterisation IET CIRCUITS DEVICES & SYSTEMS, 6, 6, 429-436 , 6, 6, 429-436 IET CIRCUITS DEVICES & SYSTEMS, 6, 6, 429-436 2012/11 Refereed English Research paper(scientific journal) Disclose to all
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera(Kyoto University) Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera(Kyoto University) A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation Proc. of the IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp.389-392 Proc. of the IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp.389-392 2012/11 Refereed English Research paper(international conference proceedings) Disclose to all
I.A.K.M. Mahfuzul; N. Kamae; T. Ishihara; H. Onodera I.A.K.M. Mahfuzul; N. Kamae; T. Ishihara; H. Onodera A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC, 101-104 , 101-104 Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC, 101-104 2012/11 Refereed English Research paper(international conference proceedings) Disclose to all
I.A.K.M. Mahfuzul; H. Onodera I.A.K.M. Mahfuzul; H. Onodera On-chip detection of process shift and process spread for silicon debugging and model-hardware correlation On-chip detection of process shift and process spread for silicon debugging and model-hardware correlation Proceedings of the Asian Test Symposium, 350-354 , 350-354 Proceedings of the Asian Test Symposium, 350-354 2012/11 Refereed English Research paper(international conference proceedings) Disclose to all
SinNyong Kim, Akira Tsuchiya, Hidetoshi Onodera(Kyoto University) SinNyong Kim, Akira Tsuchiya, Hidetoshi Onodera(Kyoto University) Modeling of Single-Event Failures in Divider and PFD of PLL based on Jitter Analysis Modeling of Single-Event Failures in Divider and PFD of PLL based on Jitter Analysis Proc. of the conference on Radiation and its Effects on Components and Systems(RADECS) Proc. of the conference on Radiation and its Effects on Components and Systems(RADECS) 2012/09 Refereed English Research paper(international conference proceedings) Disclose to all
Nishimura Shohei, Matsumoto Takashi(Kyoto University), Kobayashi Kazutoshi(KIT), Onodera Hidetoshi(Kyoto University) Nishimura Shohei, Matsumoto Takashi(Kyoto University), Kobayashi Kazutoshi(KIT), Onodera Hidetoshi(Kyoto University) Impact on delay due to random telegraph noise under low voltage operation in logic circuits Impact on delay due to random telegraph noise under low voltage operation in logic circuits Proc. of 2012 International Conference on Solid State Devices and Materials (SSDM2012), pp.170-171 Proc. of 2012 International Conference on Solid State Devices and Materials (SSDM2012), pp.170-171 2012/09 Refereed English Research paper(international conference proceedings) Disclose to all
S. Nishizawa; T. Ishihara; H. Onodera S. Nishizawa; T. Ishihara; H. Onodera A flexible structure of standard cell and its optimization method for near-threshold voltage operation A flexible structure of standard cell and its optimization method for near-threshold voltage operation Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 235-240 , 235-240 Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 235-240 2012/09 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta(Kyoto University), R. Yamamoto, K. Kobayashi(KIT), and H. Onodera(Kyoto University) J. Furuta(Kyoto University), R. Yamamoto, K. Kobayashi(KIT), and H. Onodera(Kyoto University) Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm Nuclear and Space Radiation Effects Conference (NSREC) Nuclear and Space Radiation Effects Conference (NSREC) 2012/07 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Impact of radiation loss in on-chip transmission-line for terahertz applications Impact of radiation loss in on-chip transmission-line for terahertz applications 2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings, 125-128 , 125-128 2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings, 125-128 2012/05 Refereed English Research paper(international conference proceedings) Disclose to all
T. Matsumoto; H. Makino; K. Kobayashi; H. Onodera T. Matsumoto; H. Makino; K. Kobayashi; H. Onodera Multicore large-scale integration lifetime extension by negative bias temperature instability recovery-based self-healing Multicore large-scale integration lifetime extension by negative bias temperature instability recovery-based self-healing Japanese Journal of Applied Physics, 51, 4 , 51, 4 Japanese Journal of Applied Physics, 51, 4 2012/04 Refereed English Research paper(scientific journal) Disclose to all
K. Zhang; R. Yamamoto; J. Furuta; K. Kobayashi; H. Onodera K. Zhang; R. Yamamoto; J. Furuta; K. Kobayashi; H. Onodera Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops IEEE International Reliability Physics Symposium Proceedings, 5B.2.1-5B.2.4 , 5B.2.1-5B.2.4 IEEE International Reliability Physics Symposium Proceedings, 5B.2.1-5B.2.4 2012/04 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates IEEE International Reliability Physics Symposium Proceedings, 2012 Vol.2, 906-910 , 2012 Vol.2, 906-910 IEEE International Reliability Physics Symposium Proceedings, 2012 Vol.2, 906-910 2012/04 Refereed English Research paper(international conference proceedings) Disclose to all
S. Fujimoto; I.A.K.M. Mahfzul; T. Matsumoto; H. Onodera S. Fujimoto; I.A.K.M. Mahfzul; T. Matsumoto; H. Onodera Inhomogeneous ring oscillator for WID variability and RTN characterization Inhomogeneous ring oscillator for WID variability and RTN characterization IEEE International Conference on Microelectronic Test Structures, 25-30 , 25-30 IEEE International Conference on Microelectronic Test Structures, 25-30 2012/03 Refereed English Research paper(international conference proceedings) Disclose to all
S. Nishizawa; H. Onodera S. Nishizawa; H. Onodera Ring oscillator with calibration circuit for accurate on-chip IR-drop measurement Ring oscillator with calibration circuit for accurate on-chip IR-drop measurement IEEE International Conference on Microelectronic Test Structures, 3-8 , 3-8 IEEE International Conference on Microelectronic Test Structures, 3-8 2012/03 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95A, 2, 479-486 , E95A, 2, 479-486 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95A, 2, 479-486 2012/02 Refereed English Research paper(scientific journal) Disclose to all
T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 561-562 , 561-562 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 561-562 2012/01 Refereed English Research paper(international conference proceedings) Disclose to all
R. Yamamoto; C. Hamanaka; J. Furuta; K. Kobayashi; H. Onodera R. Yamamoto; C. Hamanaka; J. Furuta; K. Kobayashi; H. Onodera An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets IEEE Transactions on Nuclear Science, 58, 6, 3053-3059 , 58, 6, 3053-3059 IEEE Transactions on Nuclear Science, 58, 6, 3053-3059 2011/12 Refereed English Research paper(scientific journal) Disclose to all
C. Hamanaka; R. Yamamoto; J. Furuta; K. Kubota; K. Kobayashi; H. Onodera C. Hamanaka; R. Yamamoto; J. Furuta; K. Kubota; K. Kobayashi; H. Onodera Variation-tolerance of a 65-nm error-hardened dual-modular-redundancy flip-flop measured by shift-register-based monitor structures Variation-tolerance of a 65-nm error-hardened dual-modular-redundancy flip-flop measured by shift-register-based monitor structures IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E94-A, 12, 2669-2675 , E94-A, 12, 2669-2675 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E94-A, 12, 2669-2675 2011/12 Refereed English Research paper(scientific journal) Disclose to all
S. Miyawaki; M. Nakamura; A. Tsuchiya; K. Kishine; H. Onodera S. Miyawaki; M. Nakamura; A. Tsuchiya; K. Kishine; H. Onodera A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS 2011 International SoC Design Conference, ISOCC 2011, 223-226 , 223-226 2011 International SoC Design Conference, ISOCC 2011, 223-226 2011/11 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; T. Kuboki; Y. Ohtomo; K. Kishine; S. Miyawaki; M. Nakamura; H. Onodera A. Tsuchiya; T. Kuboki; Y. Ohtomo; K. Kishine; S. Miyawaki; M. Nakamura; H. Onodera Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors 2011 International SoC Design Conference, ISOCC 2011, 36-39 , 36-39 2011 International SoC Design Conference, ISOCC 2011, 36-39 2011/11 Refereed English Research paper(international conference proceedings) Disclose to all
N. Kamae; A. Tsuchiya; H. Onodera N. Kamae; A. Tsuchiya; H. Onodera An area effective forward/reverse body bias generator for within-die variability compensation An area effective forward/reverse body bias generator for within-die variability compensation 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, 217-220 , 217-220 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, 217-220 2011/11 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera J. Furuta; R. Yamamoto; K. Kobayashi; H. Onodera Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, 209-212 , 209-212 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, 209-212 2011/11 Refereed English Research paper(international conference proceedings) Disclose to all
Bishnu Prasad Das, Hidetoshi Onodera Bishnu Prasad Das, Hidetoshi Onodera Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization Proceedings of 2011 International Workshop on RTL and Higl Level Testing, pp.113-118 Proceedings of 2011 International Workshop on RTL and Higl Level Testing, pp.113-118 2011/11 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera Dependable VLSI program in Japan - Program overview and the current status of dependable VLSI platform project Dependable VLSI program in Japan - Program overview and the current status of dependable VLSI platform project Proceedings of the Asian Test Symposium, 492-495 , 492-495 Proceedings of the Asian Test Symposium, 492-495 2011/11 Refereed English Research paper(scientific journal) Disclose to all
Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi and Hidetoshi Onodera Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi and Hidetoshi Onodera Multi-core LSI Lifetime Extension by NBTI-Recovery-bases Self-healing Multi-core LSI Lifetime Extension by NBTI-Recovery-bases Self-healing Proceedings of International Conference on Solid State Devices and Materials, pp.1045-1046 Proceedings of International Conference on Solid State Devices and Materials, pp.1045-1046 2011/09 Refereed English Research paper(international conference proceedings) Disclose to all
R. Yamamoto, C. Hamanaka(Kyoto Institute of Technology), J. Furuta(Kyoto University), K. Kobayashi(Kyoto Institute of Technology), and H. Onodera(Kyoto University) R. Yamamoto, C. Hamanaka(Kyoto Institute of Technology), J. Furuta(Kyoto University), K. Kobayashi(Kyoto Institute of Technology), and H. Onodera(Kyoto University) An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets IEEE Nuclear and Space Radiation Effects Conference IEEE Nuclear and Space Radiation Effects Conference 2011/07 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Gradient resistivity method for numerical evaluation of anomalous skin effect Gradient resistivity method for numerical evaluation of anomalous skin effect 2011 IEEE 15th Workshop on Signal Propagation on Interconnects, SPI 2011 - Proceedings, 139-142 , 139-142 2011 IEEE 15th Workshop on Signal Propagation on Interconnects, SPI 2011 - Proceedings, 139-142 2011/05 Refereed English Research paper(international conference proceedings) Disclose to all
K. Ito; T. Matsumoto; S. Nishizawa; H. Sunagawa; K. Kobayashi; H. Onodera K. Ito; T. Matsumoto; S. Nishizawa; H. Sunagawa; K. Kobayashi; H. Onodera The impact of RTN on performance fluctuation in CMOS logic circuits The impact of RTN on performance fluctuation in CMOS logic circuits IEEE International Reliability Physics Symposium Proceedings, CR.5.1-CR.5.4 , CR.5.1-CR.5.4 IEEE International Reliability Physics Symposium Proceedings, CR.5.1-CR.5.4 2011/04 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera Measurement of neutron-induced SET pulse width using propagation-induced pulse shrinking Measurement of neutron-induced SET pulse width using propagation-induced pulse shrinking IEEE International Reliability Physics Symposium Proceedings IEEE International Reliability Physics Symposium Proceedings 2011/04 Refereed English Research paper(international conference proceedings) Disclose to all
T. Matsumoto; H. Makino; K. Kobayashi; H. Onodera T. Matsumoto; H. Makino; K. Kobayashi; H. Onodera A 65 nm complementary metal-oxide-semiconductor 400 ns measurement delay negative-bias-temperature-instability recovery sensor with minimum assist circuit A 65 nm complementary metal-oxide-semiconductor 400 ns measurement delay negative-bias-temperature-instability recovery sensor with minimum assist circuit Japanese Journal of Applied Physics, 50, 4,Issue 2, 1-4 , 50, 4,Issue 2, 1-4 Japanese Journal of Applied Physics, 50, 4,Issue 2, 1-4 2011/04 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera H. Onodera Message from the editor-in-chief Message from the editor-in-chief IPSJ Transactions on System LSI Design Methodology, 4, 1 , 4, 1 IPSJ Transactions on System LSI Design Methodology, 4, 1 2011/04 Refereed English Research paper(scientific journal) Disclose to all
I.A.K.M. Mahfuzul; A. Tsuchiya; K. Kobayashi; H. Onodera I.A.K.M. Mahfuzul; A. Tsuchiya; K. Kobayashi; H. Onodera Variation-sensitive monitor circuits for estimation of die-to-die process variation Variation-sensitive monitor circuits for estimation of die-to-die process variation IEEE International Conference on Microelectronic Test Structures IEEE International Conference on Microelectronic Test Structures 2011/03 Refereed English Research paper(international conference proceedings) Disclose to all
K. Ito; T. Matsumoto; S. Nishizawa; H. Sunagawa; K. Kobayashi; H. Onodera K. Ito; T. Matsumoto; S. Nishizawa; H. Sunagawa; K. Kobayashi; H. Onodera Modeling of Random Telegraph Noise under circuit operation Simulation and measurement of RTN-induced delay fluctuation Modeling of Random Telegraph Noise under circuit operation Simulation and measurement of RTN-induced delay fluctuation Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, 22-27 , 22-27 Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, 22-27 2011/03 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 83-84 , 83-84 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 83-84 2011/01 Refereed English Research paper(international conference proceedings) Disclose to all
B.P. Das; H. Onodera B.P. Das; H. Onodera Warning prediction sequential for transient error prevention Warning prediction sequential for transient error prevention Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 382-390 , 382-390 Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 382-390 2010/10 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera T. Kuboki; Y. Ohtomo; A. Tsuchiya; K. Kishine; H. Onodera A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS Proceedings of the Custom Integrated Circuits Conference, 2010, 395-398 , 2010, 395-398 Proceedings of the Custom Integrated Circuits Conference, 2010, 395-398 2010/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Sunagawa; H. Onodera H. Sunagawa; H. Onodera Variation-tolerant design of D-flipflops Variation-tolerant design of D-flipflops Proceedings - IEEE International SOC Conference, SOCC 2010, 147-151 , 147-151 Proceedings - IEEE International SOC Conference, SOCC 2010, 147-151 2010/09 Refereed English Research paper(international conference proceedings) Disclose to all
S. Kim; A. Tsuchiya; H. Onodera S. Kim; A. Tsuchiya; H. Onodera A design procedure of predictive RF MOSFET model for compatibility with ITRS A design procedure of predictive RF MOSFET model for compatibility with ITRS Proceedings - IEEE International SOC Conference, SOCC 2010, 396-399 , 396-399 Proceedings - IEEE International SOC Conference, SOCC 2010, 396-399 2010/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Sunagawa; H. Terada; A. Tsuchiya; K. Kobayashi; H. Onodera H. Sunagawa; H. Terada; A. Tsuchiya; K. Kobayashi; H. Onodera Effect of regularity-enhanced layout on variability and circuit performance of standard cells Effect of regularity-enhanced layout on variability and circuit performance of standard cells IPSJ Transactions on System LSI Design Methodology, 3, 130-139 , 3, 130-139 IPSJ Transactions on System LSI Design Methodology, 3, 130-139 2010/09 Refereed English Research paper(scientific journal) Disclose to all
J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera J. Furuta; C. Hamanaka; K. Kobayashi; H. Onodera A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 123-124 , 123-124 IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 123-124 2010/06 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Measurement of on-chip transmission-line with stacked split-ring resonators Measurement of on-chip transmission-line with stacked split-ring resonators 2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings, 137-140 , 137-140 2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings, 137-140 2010/05 Refereed English Research paper(international conference proceedings) Disclose to all
J. Furuta; K. Kobayashi; H. Onodera J. Furuta; K. Kobayashi; H. Onodera An area/delay efficient dual-modular flip-flop with higher SEU/SET immunity An area/delay efficient dual-modular flip-flop with higher SEU/SET immunity IEICE Transactions on Electronics, E93C, 3, 340-346 , E93C, 3, 340-346 IEICE Transactions on Electronics, E93C, 3, 340-346 2010/03 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera H. Onodera IPSJ Transactions on System LSI Design Methodology: Message from the editor-in-chief IPSJ Transactions on System LSI Design Methodology: Message from the editor-in-chief IPSJ Transactions on System LSI Design Methodology, 3, 1 , 3, 1 IPSJ Transactions on System LSI Design Methodology, 3, 1 2010/01 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera On-chip metamaterial transmission-line based on stacked split-ring resonator for millimeter-wave LSIs On-chip metamaterial transmission-line based on stacked split-ring resonator for millimeter-wave LSIs APMC 2009 - Asia Pacific Microwave Conference 2009, 1458-1461 , 1458-1461 APMC 2009 - Asia Pacific Microwave Conference 2009, 1458-1461 2009/12 Refereed English Research paper(international conference proceedings) Disclose to all
T. Fukuoka; A. Tsuchiya; H. Onodera T. Fukuoka; A. Tsuchiya; H. Onodera Statistical gate delay model for multiple input switching Statistical gate delay model for multiple input switching IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92A, 12, 3070-3078 , E92A, 12, 3070-3078 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92A, 12, 3070-3078 2009/12 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; H. Terada H. Onodera; H. Terada Characterization of WID delay variability using RO-array test structures Characterization of WID delay variability using RO-array test structures ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 658-661 , 658-661 ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 658-661 2009/10 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Effect of dummy fills on characteristics of passive devices in CMOS millimeter-wave circuits Effect of dummy fills on characteristics of passive devices in CMOS millimeter-wave circuits ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 296-299 , 296-299 ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 296-299 2009/10 Refereed English Research paper(international conference proceedings) Disclose to all
G. Gildenblat; H. Onodera G. Gildenblat; H. Onodera Modeling of passive elements and reliability Modeling of passive elements and reliability Proceedings of the Custom Integrated Circuits Conference Proceedings of the Custom Integrated Circuits Conference 2009/09 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kishine; H. Inaba; M. Nakamura; M. Nakamura; Y. Ohtomo; H. Onodera K. Kishine; H. Inaba; M. Nakamura; M. Nakamura; Y. Ohtomo; H. Onodera Low-jitter design method based on ω<sub>n</sub>-domain jitter analysis for 10Gbit/s clock and data recovery ICs Low-jitter design method based on ω<sub>n</sub>-domain jitter analysis for 10Gbit/s clock and data recovery ICs Electronics Letters, 45, 16, 808-U11 , 45, 16, 808-U11 Electronics Letters, 45, 16, 808-U11 2009/07 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Effect of underlayer dummy fills on on-chip transmission line Effect of underlayer dummy fills on on-chip transmission line 2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09 2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09 2009/05 Refereed English Research paper(international conference proceedings) Disclose to all
H. Sunagawa; H. Terada; A. Tsuchiya; K. Kobayashiy; H. Onodera H. Sunagawa; H. Terada; A. Tsuchiya; K. Kobayashiy; H. Onodera Effect of regularity-enhanced layout on printability and circuit performance of standard cells Effect of regularity-enhanced layout on printability and circuit performance of standard cells Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, 195-200 , 195-200 Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, 195-200 2009/03 Refereed English Research paper(international conference proceedings) Disclose to all
S. Sakai; H. Onodera; H. Yasuura; J.C. Hoe S. Sakai; H. Onodera; H. Yasuura; J.C. Hoe Dependable VLSI: Device, design and architecture-How should they co-operate ? Dependable VLSI: Device, design and architecture-How should they co-operate ? Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 859-860 , 859-860 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 859-860 2009/01 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera IPSJ Transactions on System LSI Design Methodology: Message from the editor-in-chief IPSJ Transactions on System LSI Design Methodology: Message from the editor-in-chief IPSJ Transactions on System LSI Design Methodology, 2, 1 , 2, 1 IPSJ Transactions on System LSI Design Methodology, 2, 1 2009/01 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera H. Onodera Variability modeling and impact on design Variability modeling and impact on design Technical Digest - International Electron Devices Meeting, IEDM Technical Digest - International Electron Devices Meeting, IEDM 2008/12 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill IEEE Transactions on Microwave Theory and Techniques, 56, 12, 3217-3222 , 56, 12, 3217-3222 IEEE Transactions on Microwave Theory and Techniques, 56, 12, 3217-3222 2008/12 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; H.-H. Vuong H. Onodera; H.-H. Vuong Statistical Modeling Statistical Modeling Proceedings of the Custom Integrated Circuits Conference Proceedings of the Custom Integrated Circuits Conference 2008/09 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Sugihara; Y. Kume; K. Kobayashi; H. Onodera Y. Sugihara; Y. Kume; K. Kobayashi; H. Onodera Performance optimization by track swapping on critical paths utilizing random variations for FPGAs Performance optimization by track swapping on critical paths utilizing random variations for FPGAs Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 502-505 , 502-505 Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 502-505 2008/09 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; Y. Kume; C.L. Ngo; Y. Sugihara; H. Onodera K. Kobayashi; Y. Kume; C.L. Ngo; Y. Sugihara; H. Onodera A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAs A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAs Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 107-112 , 107-112 Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 107-112 2008/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Terada; T. Fukuoka; A. Tsuchiya; H. Onodera H. Terada; T. Fukuoka; A. Tsuchiya; H. Onodera Accurate estimation of the worst-case delay in statistical static timing analysis Accurate estimation of the worst-case delay in statistical static timing analysis IPSJ Transactions on System LSI Design Methodology, 1, 116-125 , 1, 116-125 IPSJ Transactions on System LSI Design Methodology, 1, 116-125 2008/09 Refereed English Research paper(scientific journal) Disclose to all
H. Shinohara; K. Nii; H. Onodera H. Shinohara; K. Nii; H. Onodera Analytical model of static noise margin in CMOS SRAM for variation consideration Analytical model of static noise margin in CMOS SRAM for variation consideration IEICE Transactions on Electronics, E91C, 9, 1488-1500 , E91C, 9, 1488-1500 IEICE Transactions on Electronics, E91C, 9, 1488-1500 2008/09 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors IEEE MTT-S International Microwave Symposium Digest, 787-790 , 787-790 IEEE MTT-S International Microwave Symposium Digest, 787-790 2008/06 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera Timing analysis considering temporal supply voltage fluctuation Timing analysis considering temporal supply voltage fluctuation IEICE Transactions on Information and Systems, E91D, 3, 655-660 , E91D, 3, 655-660 IEICE Transactions on Information and Systems, E91D, 3, 655-660 2008/03 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; H. Onodera K. Kobayashi; H. Onodera Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 793-794 , 793-794 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 793-794 2008/01 Refereed English Research paper(international conference proceedings) Disclose to all
T. Fukuoka; A. Tsuchiya; H. Onodera T. Fukuoka; A. Tsuchiya; H. Onodera Statistical gate delay model for multiple input switching Statistical gate delay model for multiple input switching Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 205-210 , 205-210 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 205-210 2008/01 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera Welcome to TSLDM-A new open-access online journal from IPSJ Welcome to TSLDM-A new open-access online journal from IPSJ IPSJ Transactions on System LSI Design Methodology, 1, 1 , 1, 1 IPSJ Transactions on System LSI Design Methodology, 1, 1 2008/01 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; J. Yamaguchi; H. Onodera M. Hashimoto; J. Yamaguchi; H. Onodera Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2661-2668 , E90A, 12, 2661-2668 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2661-2668 2007/12 Refereed English Research paper(scientific journal) Disclose to all
H. Muta; H. Onodera H. Muta; H. Onodera Manufacturability-aware design of standard cells Manufacturability-aware design of standard cells IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2682-2690 , E90A, 12, 2682-2690 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90A, 12, 2682-2690 2007/12 Refereed English Research paper(scientific journal) Disclose to all
Kobayashi, Kazutoshi; Katsuki, Kazuya; Kotani, Manabu; Sugihara, Yuuri; Kume, Yohei; Onodera, Hidetoshi Kobayashi, Kazutoshi; Katsuki, Kazuya; Kotani, Manabu; Sugihara, Yuuri; Kume, Yohei; Onodera, Hidetoshi A 90 nm 48 x 48 LUT-based FPGA enhancing speed and yield utilizing within-die delay variations A 90 nm 48 x 48 LUT-based FPGA enhancing speed and yield utilizing within-die delay variations IEICE TRANSACTIONS ON ELECTRONICS, E90C, 10, 1919-1926 , E90C, 10, 1919-1926 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 10, 1919-1926 2007/10 Refereed English Research paper(scientific journal) Disclose to all
T. Kouno; H. Onodera T. Kouno; H. Onodera Consideration of transition-time variability in statistical timing analysis Consideration of transition-time variability in statistical timing analysis 2006 IEEE International Systems-on-Chip Conference, SOC, 207-210 , 207-210 2006 IEEE International Systems-on-Chip Conference, SOC, 207-210 2007/09 Refereed English Research paper(international conference proceedings) Disclose to all
M. Yamaoka; H. Onodera M. Yamaoka; H. Onodera A detailed Vth-variation analysis for sub-100-nm embedded SRAM design A detailed Vth-variation analysis for sub-100-nm embedded SRAM design 2006 IEEE International Systems-on-Chip Conference, SOC, 315-318 , 315-318 2006 IEEE International Systems-on-Chip Conference, SOC, 315-318 2007/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera Toward variability-aware design Toward variability-aware design Digest of Technical Papers - Symposium on VLSI Technology, 92-93 , 92-93 Digest of Technical Papers - Symposium on VLSI Technology, 92-93 2007/06 Refereed English Research paper(international conference proceedings) Disclose to all
Tsuchiya, Akira; Hashimoto, Masanori; Onodera, Hidetoshi Tsuchiya, Akira; Hashimoto, Masanori; Onodera, Hidetoshi Optimal termination of on-chip transmission-lines for high-speed signaling Optimal termination of on-chip transmission-lines for high-speed signaling IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1267-1273 , E90C, 6, 1267-1273 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1267-1273 2007/06 Refereed English Research paper(scientific journal) Disclose to all
Kuboki, Takeshi; Tsuchiya, Akira; Onodera, Hidetoshi Kuboki, Takeshi; Tsuchiya, Akira; Onodera, Hidetoshi Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1274-1281 , E90C, 6, 1274-1281 IEICE TRANSACTIONS ON ELECTRONICS, E90C, 6, 1274-1281 2007/06 Refereed English Research paper(scientific journal) Disclose to all
T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 227-230 , 227-230 Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 227-230 2007/05 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Effect of dummy fills on high-frequency characteristics of on-chip interconnects Effect of dummy fills on high-frequency characteristics of on-chip interconnects Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 275-278 , 275-278 Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, 275-278 2007/05 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Measurement of interconnect loss due to dummy fills Measurement of interconnect loss due to dummy fills Proceedings - 11th IEEE Workshop on Signal Propagation on Interconnects, SPI 2007, 241-244 , 241-244 Proceedings - 11th IEEE Workshop on Signal Propagation on Interconnects, SPI 2007, 241-244 2007/05 Refereed English Research paper(international conference proceedings) Disclose to all
K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera A 90 nm LUT array for speed and yield enhancement by utilizing within-die delay variations A 90 nm LUT array for speed and yield enhancement by utilizing within-die delay variations IEICE Transactions on Electronics, E90C, 4, 699-707 , E90C, 4, 699-707 IEICE Transactions on Electronics, E90C, 4, 699-707 2007/04 Refereed English Research paper(scientific journal) Disclose to all
T. Fukuoka; A. Tsuchiya; H. Onodera T. Fukuoka; A. Tsuchiya; H. Onodera Worst-case delay analysis considering the variability of transistors and interconnects Worst-case delay analysis considering the variability of transistors and interconnects Proceedings of the International Symposium on Physical Design, 35-42 , 35-42 Proceedings of the International Symposium on Physical Design, 35-42 2007/03 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera ASP-DAC 2007 General Chair\\'s message ASP-DAC 2007 General Chair\\'s message Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2007/01 Refereed English Research paper(international conference proceedings) Disclose to all
T. Kuboki; A. Tsuchiya; H. Onodera T. Kuboki; A. Tsuchiya; H. Onodera A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 120-121 , 120-121 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 120-121 2007/01 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Sugihara; M. Kotani; K. Katsuki; K. Kobayashi; H. Onodera Y. Sugihara; M. Kotani; K. Katsuki; K. Kobayashi; H. Onodera A 90nm 8×16 FPGA enhancing speed and yield utilizing within-die variations A 90nm 8×16 FPGA enhancing speed and yield utilizing within-die variations Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 122-123 , 122-123 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 122-123 2007/01 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Interconnect RL extraction based on transfer characteristics of transmission-line Interconnect RL extraction based on transfer characteristics of transmission-line IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3585-3593 , E89A, 12, 3585-3593 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3585-3593 2006/12 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; M. Ikeda; T. Ishihara; T. Isshiki; K. Inoue; K. Okada; S. Kajihara; M. Kaneko; H. Kawaguchi; S. Kimura; M. Kuga; A. Kurokawa; T. Sato; T. Shibuya; Y. Shiraishi; K. Takagi; A. Takahashi; Y. Takeuchi; N. Togawa; H. Tomiyama; Y. Nakamura; K. Hamaguchi; Y. Miura; S.-I. Minato; R. Yamaguchi; M. Yamada; Y. Yuminaka; T. Watanabe; M. Hashimoto; M. Miyazaki H. Onodera; M. Ikeda; T. Ishihara; T. Isshiki; K. Inoue; K. Okada; S. Kajihara; M. Kaneko; H. Kawaguchi; S. Kimura; M. Kuga; A. Kurokawa; T. Sato; T. Shibuya; Y. Shiraishi; K. Takagi; A. Takahashi; Y. Takeuchi; N. Togawa; H. Tomiyama; Y. Nakamura; K. Hamaguchi; Y. Miura; S.-I. Minato; R. Yamaguchi; M. Yamada; Y. Yuminaka; T. Watanabe; M. Hashimoto; M. Miyazaki Special section on VLSI Design and CAD Algorithms Special section on VLSI Design and CAD Algorithms IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377 , E89-A, 12, 3377 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, 3377 2006/12 Refereed English Research paper(scientific journal) Disclose to all
T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3560-3568 , E89A, 12, 3560-3568 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89A, 12, 3560-3568 2006/12 Refereed English Research paper(scientific journal) Disclose to all
T. Kouno; M. Hashimoto; H. Onodera T. Kouno; M. Hashimoto; H. Onodera Input capacitance modeling of logic gates for accurate static timing analysis Input capacitance modeling of logic gates for accurate static timing analysis 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, 453-456 , 453-456 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, 453-456 2006/11 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; H. Onodera A. Tsuchiya; H. Onodera Analytical estimation of interconnect loss due to dummy fills Analytical estimation of interconnect loss due to dummy fills Electrical Performance of Electronic Packaging, EPEP, 149-152 , 149-152 Electrical Performance of Electronic Packaging, EPEP, 149-152 2006/10 Refereed English Research paper(international conference proceedings) Disclose to all
M. Kotani; K. Katsuki; K. Kobayashi; H. Onodera M. Kotani; K. Katsuki; K. Kobayashi; H. Onodera A 90nm 8×16 LUT-based FPGA enhancing speed and yield utilizing within-die variations A 90nm 8×16 LUT-based FPGA enhancing speed and yield utilizing within-die variations ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, 110-113 , 110-113 ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, 110-113 2006/09 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; M. Kotani; K. Katsuki; Y. Takatsukasa; K. Ogata; Y. Sugihara; H. Onodera K. Kobayashi; M. Kotani; K. Katsuki; Y. Takatsukasa; K. Ogata; Y. Sugihara; H. Onodera A yield and speed enhancement technique using reconfigurable devices against within-die variations on the nanometer regime A yield and speed enhancement technique using reconfigurable devices against within-die variations on the nanometer regime Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 625-628 , 625-628 Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 625-628 2006/08 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; A. Higuchi; H. Onodera K. Kobayashi; A. Higuchi; H. Onodera A leakage reduction scheme for sleep transistors with decoupling capacitors in the deep submicron era A leakage reduction scheme for sleep transistors with decoupling capacitors in the deep submicron era IEICE Transactions on Electronics, E89C, 6, 838-843 , E89C, 6, 838-843 IEICE Transactions on Electronics, E89C, 6, 838-843 2006/06 Refereed English Research paper(scientific journal) Disclose to all
Y. Yuyama; A. Tsuchiya; K. Kobayashi; H. Onodera Y. Yuyama; A. Tsuchiya; K. Kobayashi; H. Onodera Alternate self-shielding for high-speed and reliable on-chip global interconnect Alternate self-shielding for high-speed and reliable on-chip global interconnect IEICE Transactions on Electronics, E89C, 3, 327-333 , E89C, 3, 327-333 IEICE Transactions on Electronics, E89C, 3, 327-333 2006/03 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera H. Onodera Variability: Modeling and its impact on design Variability: Modeling and its impact on design IEICE Transactions on Electronics, E89C, 3, 342-348 , E89C, 3, 342-348 IEICE Transactions on Electronics, E89C, 3, 342-348 2006/03 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Interconnect RL extraction at a single representative frequency Interconnect RL extraction at a single representative frequency Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 515-520 , 2006, 515-520 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 515-520 2006/01 Refereed English Research paper(international conference proceedings) Disclose to all
K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 110-111 , 2006, 110-111 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 110-111 2006/01 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; T. Yamamoto; H. Onodera M. Hashimoto; T. Yamamoto; H. Onodera Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3375-3381 , E88A, 12, 3375-3381 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3375-3381 2005/12 Refereed English Research paper(scientific journal) Disclose to all
T. Sato; M. Hashimoto; H. Onodera T. Sato; M. Hashimoto; H. Onodera Successive pad assignment for minimizing supply voltage drop Successive pad assignment for minimizing supply voltage drop IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3429-3436 , E88A, 12, 3429-3436 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3429-3436 2005/12 Refereed English Research paper(scientific journal) Disclose to all
A. Muramatsu; M. Hashimoto; H. Onodera A. Muramatsu; M. Hashimoto; H. Onodera Effects of on-chip inductance on power distribution grid Effects of on-chip inductance on power distribution grid IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3564-3572 , E88A, 12, 3564-3572 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 12, 3564-3572 2005/12 Refereed English Research paper(scientific journal) Disclose to all
K. Kishine; H. Onodera K. Kishine; H. Onodera Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs Electronics Letters, 41, 23, 1273-1275 , 41, 23, 1273-1275 Electronics Letters, 41, 23, 1273-1275 2005/11 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; A. Tsuchiya; A. Shinmyo; H. Onodera M. Hashimoto; A. Tsuchiya; A. Shinmyo; H. Onodera Performance prediction of on-chip high-throughput global signaling Performance prediction of on-chip high-throughput global signaling IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 79-82 , 79-82 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 79-82 2005/10 Refereed English Research paper(international conference proceedings) Disclose to all
K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera K. Katsuki; M. Kotani; K. Kobayashi; H. Onodera A yield and speed enhancement scheme under within-die variations on 90nm LUT array A yield and speed enhancement scheme under within-die variations on 90nm LUT array Proceedings of the Custom Integrated Circuits Conference, 601-604 , 601-604 Proceedings of the Custom Integrated Circuits Conference, 601-604 2005/09 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Design guideline for resistive termination of on-chip high-speed interconnects Design guideline for resistive termination of on-chip high-speed interconnects Proceedings of the Custom Integrated Circuits Conference, 613-616 , 613-616 Proceedings of the Custom Integrated Circuits Conference, 613-616 2005/09 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, 201-202 , 201-202 Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, 201-202 2005/05 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Performance limitation of on-chip global interconnects for high-speed signaling Performance limitation of on-chip global interconnects for high-speed signaling IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 4, 885-891 , E88A, 4, 885-891 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E88A, 4, 885-891 2005/04 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; M. Aramoto; H. Onodera K. Kobayashi; M. Aramoto; H. Onodera A resource-shared VLIW processor for low-power on-chip multiprocessing in the nanometer era A resource-shared VLIW processor for low-power on-chip multiprocessing in the nanometer era IEICE Transactions on Electronics, E88C, 4, 552-558 , E88C, 4, 552-558 IEICE Transactions on Electronics, E88C, 4, 552-558 2005/04 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; T. Yamamoto; H. Onodera M. Hashimoto; T. Yamamoto; H. Onodera Statistical analysis of clock skew variation in H-tree structure Statistical analysis of clock skew variation in H-tree structure Proceedings - International Symposium on Quality Electronic Design, ISQED, 402-407 , 402-407 Proceedings - International Symposium on Quality Electronic Design, ISQED, 402-407 2005/03 Refereed English Research paper(international conference proceedings) Disclose to all
T. Miyazaki; M. Hashimoto; H. Onodera T. Miyazaki; M. Hashimoto; H. Onodera A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL IEICE Transactions on Electronics, E88C, 3, 437-444 , E88C, 3, 437-444 IEICE Transactions on Electronics, E88C, 3, 437-444 2005/03 Refereed English Research paper(scientific journal) Disclose to all
T. Sato; M. Hashimoto; H. Onodera T. Sato; M. Hashimoto; H. Onodera Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 723-728 , 2, 723-728 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 723-728 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Return path selection for loop RL extraction Return path selection for loop RL extraction Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1078-1081 , 2, 1078-1081 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1078-1081 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera Timing analysis considering temporal supply voltage fluctuation Timing analysis considering temporal supply voltage fluctuation Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1098-1101 , 2, 1098-1101 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 1098-1101 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
A. Shinmyo; M. Hashimoto; H. Onodera A. Shinmyo; M. Hashimoto; H. Onodera Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, D9-D10 , 2, D9-D10 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, D9-D10 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; M. Aramoto; Y. Yuyama; A. Higuchi; H. Onodera K. Kobayashi; M. Aramoto; Y. Yuyama; A. Higuchi; H. Onodera A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1, 619-622 , 1, 619-622 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1, 619-622 2005/01 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; H. Onodera K. Okada; H. Onodera Statistical parameter extraction for intra- and inter-chip variabilities of metal-oxide-semiconductor field-effect transistor characteristics Statistical parameter extraction for intra- and inter-chip variabilities of metal-oxide-semiconductor field-effect transistor characteristics Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 44, 1A, 131-134 , 44, 1A, 131-134 Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 44, 1A, 131-134 2005/01 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; H. Onodera M. Hashimoto; H. Onodera Crosstalk noise optimization by post-layout transistor sizing Crosstalk noise optimization by post-layout transistor sizing IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 12, 3251-3257 , E87A, 12, 3251-3257 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 12, 3251-3257 2004/12 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; J. Yamaguchi; H. Onodera M. Hashimoto; J. Yamaguchi; H. Onodera Timing analysis considering spatial power/ground level variation Timing analysis considering spatial power/ground level variation IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 814-820 , 814-820 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 814-820 2004/11 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; A. Tsuchiya; H. Onodera M. Hashimoto; A. Tsuchiya; H. Onodera On-chip global signaling by wave pipelining On-chip global signaling by wave pipelining IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 311-314 , 311-314 IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 311-314 2004/10 Refereed English Research paper(international conference proceedings) Disclose to all
S. Rochel; H. Onodera S. Rochel; H. Onodera Simulation and modeling for RF and mixed signal designs Simulation and modeling for RF and mixed signal designs Proceedings of the Custom Integrated Circuits Conference, 107- , 107- Proceedings of the Custom Integrated Circuits Conference, 107- 2004/09 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; Y. Gotoh; M. Hashimoto; H. Onodera A. Tsuchiya; Y. Gotoh; M. Hashimoto; H. Onodera Performance limitation of on-chip global interconnects for high-speed signaling Performance limitation of on-chip global interconnects for high-speed signaling Proceedings of the Custom Integrated Circuits Conference, 489-492 , 489-492 Proceedings of the Custom Integrated Circuits Conference, 489-492 2004/09 Refereed English Research paper(international conference proceedings) Disclose to all
A. Shinmyo; M. Hashimoto; H. Onodera A. Shinmyo; M. Hashimoto; H. Onodera Design and optimization of CMOS current mode logic dividers Design and optimization of CMOS current mode logic dividers Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 434-435 , 434-435 Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 434-435 2004/08 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; H. Hoshino; H. Onodera K. Okada; H. Hoshino; H. Onodera Design optimization methodology for on-chip spiral inductors Design optimization methodology for on-chip spiral inductors IEICE Transactions on Electronics, E87C, 6, 933-941 , E87C, 6, 933-941 IEICE Transactions on Electronics, E87C, 6, 933-941 2004/06 Refereed English Research paper(scientific journal) Disclose to all
K. Okada; H. Hoshino; H. Onodera K. Okada; H. Hoshino; H. Onodera Modeling and optimization of on-chip spiral inductor in S-parameter domain Modeling and optimization of on-chip spiral inductor in S-parameter domain Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-153-V-156 , 5, V-153-V-156 Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-153-V-156 2004/05 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Yuyama; M. Aramoto; K. Kobayashi; H. Onodera Y. Yuyama; M. Aramoto; K. Kobayashi; H. Onodera RTL/ISS CO-modeling methodology for embedded processor using systemc RTL/ISS CO-modeling methodology for embedded processor using systemc Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-305-V-308 , 5, V-305-V-308 Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-305-V-308 2004/05 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; Y. Yamada; H. Onodera M. Hashimoto; Y. Yamada; H. Onodera Equivalent Waveform Propagation for Static Timing Analysis Equivalent Waveform Propagation for Static Timing Analysis IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23, 4, 498-508 , 23, 4, 498-508 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23, 4, 498-508 2004/04 Refereed English Research paper(scientific journal) Disclose to all
A. Higuchi; K. Kobayashi; H. Onodera A. Higuchi; K. Kobayashi; H. Onodera Instruction-level power estimation method by considering hamming distance of registers Instruction-level power estimation method by considering hamming distance of registers IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 4, 823-829 , E87A, 4, 823-829 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 4, 823-829 2004/04 Refereed English Research paper(scientific journal) Disclose to all
H. Sugawara; Y. Yokoyama; S. Gomi; H. Ito; K. Okada; H. Hoshino; H. Onodera; K. Masu H. Sugawara; Y. Yokoyama; S. Gomi; H. Ito; K. Okada; H. Hoshino; H. Onodera; K. Masu Variable RF inductor on Si CMOS chip Variable RF inductor on Si CMOS chip Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 43, 4B, 2293-2296 , 43, 4B, 2293-2296 Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 43, 4B, 2293-2296 2004/04 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; K. Fujimori; H. Onodera M. Hashimoto; K. Fujimori; H. Onodera Automatic generation of standard cell library in VDSM technologies Automatic generation of standard cell library in VDSM technologies Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004, 36-41 , 36-41 Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004, 36-41 2004/03 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; H. Onodera K. Kobayashi; H. Onodera A Comprehensive Simulation and Test Environment for Prototype VLSI Verification A Comprehensive Simulation and Test Environment for Prototype VLSI Verification IEICE Transactions on Information and Systems, E87D, 3, 630-636 , E87D, 3, 630-636 IEICE Transactions on Information and Systems, E87D, 3, 630-636 2004/03 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; R. Nakanishi; H. Onodera K. Kobayashi; R. Nakanishi; H. Onodera An Efficient Motion Estimation Algorithm Using a Gyro Sensor An Efficient Motion Estimation Algorithm Using a Gyro Sensor IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 3, 530-538 , E87A, 3, 530-538 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87A, 3, 530-538 2004/03 Refereed English Research paper(scientific journal) Disclose to all
K. Asada; H. Onodera K. Asada; H. Onodera Greeting from conference chairs Greeting from conference chairs Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, i-ii , i-ii Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, i-ii 2004/01 Refereed English Research paper(international conference proceedings) Disclose to all
T. Miyazaki; M. Hashimoto; H. Onodera T. Miyazaki; M. Hashimoto; H. Onodera A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 545-546 , 545-546 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 545-546 2004/01 Refereed English Research paper(international conference proceedings) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Representative frequency for interconnect R(f)L(f)C extraction Representative frequency for interconnect R(f)L(f)C extraction Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 691-696 , 691-696 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 691-696 2004/01 Refereed English Research paper(international conference proceedings) Disclose to all
Y. Yuyama; M. Aramoto; K. Kobayashi; H. Onodera Y. Yuyama; M. Aramoto; K. Kobayashi; H. Onodera An SoC architecture and its design methodology using unifunctional heterogeneous processor array An SoC architecture and its design methodology using unifunctional heterogeneous processor array Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 737-742 , 737-742 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 737-742 2004/01 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; K. Yamaoka; H. Onodera K. Okada; K. Yamaoka; H. Onodera Statistical Gate-Delay Modeling with Intra-Gate Variability Statistical Gate-Delay Modeling with Intra-Gate Variability IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2914-2922 , E86A, 12, 2914-2922 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2914-2922 2003/12 Refereed English Research paper(scientific journal) Disclose to all
A. Tsuchiya; M. Hashimoto; H. Onodera A. Tsuchiya; M. Hashimoto; H. Onodera Representative Frequency for Interconnect R(f)L(f)C Extraction Representative Frequency for Interconnect R(f)L(f)C Extraction IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2942-2951 , E86A, 12, 2942-2951 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2942-2951 2003/12 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; M. Takahashi; H. Onodera M. Hashimoto; M. Takahashi; H. Onodera Crosstalk Noise Estimation for Generic RC Trees Crosstalk Noise Estimation for Generic RC Trees IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2965-2973 , E86A, 12, 2965-2973 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 2965-2973 2003/12 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; Y. Hayashi; H. Onodera M. Hashimoto; Y. Hayashi; H. Onodera Experimental Study on Cell-Base High-Performance Datapath Design Experimental Study on Cell-Base High-Performance Datapath Design IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 3204-3207 , E86A, 12, 3204-3207 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 12, 3204-3207 2003/12 Refereed English Research paper(scientific journal) Disclose to all
A. Kuehlmann; H. Onodera A. Kuehlmann; H. Onodera IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers: Foreword IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers: Foreword IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, iv , iv IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, iv 2003/11 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; Y. Yamada; H. Onodera M. Hashimoto; Y. Yamada; H. Onodera Equivalent waveform propagation for static timing analysis Equivalent waveform propagation for static timing analysis IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 169-175 , 169-175 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 169-175 2003/11 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; K. Yamaoka; H. Onodera K. Okada; K. Yamaoka; H. Onodera A Statistical Gate-Delay Model Considering Intra-Gate Variability A Statistical Gate-Delay Model Considering Intra-Gate Variability IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 908-913 , 908-913 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 908-913 2003/11 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; K. Yamaoka; H. Onodera K. Okada; K. Yamaoka; H. Onodera Statistical modeling of gate-delay variation with consideration of intra-gate variability Statistical modeling of gate-delay variation with consideration of intra-gate variability Proceedings - IEEE International Symposium on Circuits and Systems, 5, V513-V516 , 5, V513-V516 Proceedings - IEEE International Symposium on Circuits and Systems, 5, V513-V516 2003/05 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; H. Onodera K. Okada; H. Onodera Realistic delay calculation based on measured intra-chip and inter-chip variabilities with the size dependence Realistic delay calculation based on measured intra-chip and inter-chip variabilities with the size dependence IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 4, 746-751 , E86A, 4, 746-751 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86A, 4, 746-751 2003/04 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; Y. Yamada; H. Onodera M. Hashimoto; Y. Yamada; H. Onodera Capturing crosstalk-induced waveform for accurate static timing analysis Capturing crosstalk-induced waveform for accurate static timing analysis Proceedings of the International Symposium on Physical Design, 18-23 , 18-23 Proceedings of the International Symposium on Physical Design, 18-23 2003/03 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; H. Onodera M. Hashimoto; H. Onodera Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85A, 12, 2799-2802 , E85A, 12, 2799-2802 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85A, 12, 2799-2802 2002/12 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; J. Yamaguchi; H. Onodera K. Kobayashi; J. Yamaguchi; H. Onodera Measurement results of on-chip IR-drop Measurement results of on-chip IR-drop Proceedings of the Custom Integrated Circuits Conference, 521-524 , 521-524 Proceedings of the Custom Integrated Circuits Conference, 521-524 2002/09 Refereed English Research paper(international conference proceedings) Disclose to all
岡田健一;小野寺秀俊 岡田健一;小野寺秀俊 Design Technologies and Design Automation of Electronic Systems. Statistical Modeling of MOS Transistors with Intra-chip Variability. Design Technologies and Design Automation of Electronic Systems. Statistical Modeling of MOS Transistors with Intra-chip Variability. 情報処理学会論文誌, 43, 5, 1330-1337 , 43, 5, 1330-1337 情報処理学会論文誌, 43, 5, 1330-1337 2002/05 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; M. Takahashi; H. Onodera M. Hashimoto; M. Takahashi; H. Onodera Crosstalk noise optimization by post-layout transistor sizing Crosstalk noise optimization by post-layout transistor sizing Proceedings of the International Symposium on Physical Design, 126-130 , 126-130 Proceedings of the International Symposium on Physical Design, 126-130 2002/04 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera H. Onodera Foreword: Special section on VLSI design and CAD algorithms Foreword: Special section on VLSI design and CAD algorithms IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, 11, 2613- , E84-A, 11, 2613- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, 11, 2613- 2001/11 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; H. Onodera M. Hashimoto; H. Onodera Post-layout transistor sizing for power reduction in cell-base design Post-layout transistor sizing for power reduction in cell-base design IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84A, 11, 2769-2777 , E84A, 11, 2769-2777 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84A, 11, 2769-2777 2001/11 Refereed English Research paper(scientific journal) Disclose to all
Yasuda, T; Fujita, H; Onodera, H Yasuda, T; Fujita, H; Onodera, H A dynamically phase adjusting PLL for improvement of lock-up performance A dynamically phase adjusting PLL for improvement of lock-up performance IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 11, 2793-2801 , E84A, 11, 2793-2801 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, 11, 2793-2801 2001/11 Refereed English Research paper(scientific journal) Disclose to all
M. Takahashi; M. Hashimoto; H. Onodera M. Takahashi; M. Hashimoto; H. Onodera Crosstalk noise estimation for generic RC trees Crosstalk noise estimation for generic RC trees Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 110-116 , 110-116 Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 110-116 2001/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera; M. Hashimoto; T. Hashimoto H. Onodera; M. Hashimoto; T. Hashimoto ASIC design methodology with on-demand library generation ASIC design methodology with on-demand library generation IEEE Symposium on VLSI Circuits, Digest of Technical Papers, CIRCUITS SYMP., 57-60 , CIRCUITS SYMP., 57-60 IEEE Symposium on VLSI Circuits, Digest of Technical Papers, CIRCUITS SYMP., 57-60 2001/06 Refereed English Research paper(international conference proceedings) Disclose to all
M. Hashimoto; H. Onodera M. Hashimoto; H. Onodera Increase in delay uncertainty by performance optimization Increase in delay uncertainty by performance optimization Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 379-382 , 2001, Vol.5, 379-382 Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 379-382 2001/05 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; H. Onodera K. Kobayashi; H. Onodera ST: Perl package for simulation and test environment ST: Perl package for simulation and test environment Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 89-92 , 2001, Vol.5, 89-92 Proceedings - IEEE International Symposium on Circuits and Systems, 2001, Vol.5, 89-92 2001/05 Refereed English Research paper(international conference proceedings) Disclose to all
T. Fujita; H. Onodera T. Fujita; H. Onodera A hierarchical statistical optimization method driven by constraint generation based on mahalanobis\\' distance A hierarchical statistical optimization method driven by constraint generation based on mahalanobis\\' distance IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84A, 3, 727-734 , E84A, 3, 727-734 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84A, 3, 727-734 2001/03 Refereed English Research paper(scientific journal) Disclose to all
K. Okada; H. Onodera K. Okada; H. Onodera Statistical modeling of device characteristics with systematic variability Statistical modeling of device characteristics with systematic variability IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, 2, 529-536 , E84-A, 2, 529-536 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, 2, 529-536 2001/02 Refereed English Research paper(scientific journal) Disclose to all
Kobayashi, K; Eguchi, M; Iwahashi, T; Shibayama, T; Li, X; Takai, K; Onodera, H Kobayashi, K; Eguchi, M; Iwahashi, T; Shibayama, T; Li, X; Takai, K; Onodera, H A low-power high-performance vector-pipeline DSP for low-rate videophones A low-power high-performance vector-pipeline DSP for low-rate videophones IEICE TRANSACTIONS ON ELECTRONICS, E84C, 2, 193-201 , E84C, 2, 193-201 IEICE TRANSACTIONS ON ELECTRONICS, E84C, 2, 193-201 2001/02 Refereed English Research paper(scientific journal) Disclose to all
T.Yasuda, H. Fujita, H.Onodera T.Yasuda, H. Fujita, H.Onodera A Dynamically Phase Adjusting PLI wiyh a Variable Delay A Dynamically Phase Adjusting PLI wiyh a Variable Delay Proc. of the Asia and South Pacific Design Automation Conference 2001(ASP-DAC2001),/,275-280, 275-280 , 275-280 Proc. of the Asia and South Pacific Design Automation Conference 2001(ASP-DAC2001),/,275-280, 275-280 2001/01 Refereed English Research paper(international conference proceedings) Disclose to all
M. Kondo; H. Onodera; K. Tamaru M. Kondo; H. Onodera; K. Tamaru MOSFET statistical modeling method using an intermediate model MOSFET statistical modeling method using an intermediate model Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 84, 1, 57-66 , 84, 1, 57-66 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 84, 1, 57-66 2001/01 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; M. Yamaoka; Y. Kobayashi; H. Onodera; K. Tamaru K. Kobayashi; M. Yamaoka; Y. Kobayashi; H. Onodera; K. Tamaru Architecture and performance evaluation of a new functional memory: Functional memory for addition Architecture and performance evaluation of a new functional memory: Functional memory for addition IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2400-2408 , E83A, 12, 2400-2408 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2400-2408 2000/12 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; H. Onodera M. Hashimoto; H. Onodera A performance optimization method by gate resizing based on statistical static timing analysis A performance optimization method by gate resizing based on statistical static timing analysis IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2558-2568 , E83A, 12, 2558-2568 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2558-2568 2000/12 Refereed English Research paper(scientific journal) Disclose to all
T. Fujita; H. Onodera T. Fujita; H. Onodera A method for linking process-level variability to system performances A method for linking process-level variability to system performances IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2592-2599 , E83A, 12, 2592-2599 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83A, 12, 2592-2599 2000/12 Refereed English Research paper(scientific journal) Disclose to all
Takuya Iwahashi; Takehide Shibayama; Masanori Hashimoto; Kazutoshi Kobayashi; Hidetoshi Onodera Takuya Iwahashi; Takehide Shibayama; Masanori Hashimoto; Kazutoshi Kobayashi; Hidetoshi Onodera Vector quantization processor for mobile video communication Vector quantization processor for mobile video communication Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 75-79 , 75-79 Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 75-79 2000/09 Refereed English Research paper(international conference proceedings) Disclose to all
Kenichi Okada; Hidetoshi Onodera Kenichi Okada; Hidetoshi Onodera Statistical modeling of device characteristics with systematic fluctuation Statistical modeling of device characteristics with systematic fluctuation Proceedings - IEEE International Symposium on Circuits and Systems, 2, II-437-II-440 , 2, II-437-II-440 Proceedings - IEEE International Symposium on Circuits and Systems, 2, II-437-II-440 2000/05 Refereed English Research paper(international conference proceedings) Disclose to all
Tomohiro Fujita; Hidetoshi Onodera Tomohiro Fujita; Hidetoshi Onodera Statistical delay calculation with vector synthesis model Statistical delay calculation with vector synthesis model Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-473-V-476 , 5, V-473-V-476 Proceedings - IEEE International Symposium on Circuits and Systems, 5, V-473-V-476 2000/05 Refereed English Research paper(international conference proceedings) Disclose to all
Masanori Hashimoto; Hidetoshi Onodera Masanori Hashimoto; Hidetoshi Onodera Performance optimization method by gate sizing using statistical static timing analysis Performance optimization method by gate sizing using statistical static timing analysis Proceedings of the International Symposium on Physical Design, 111-116 , 111-116 Proceedings of the International Symposium on Physical Design, 111-116 2000/03 Refereed English Research paper(international conference proceedings) Disclose to all
K. Okada; H. Onodera; K. Tamaru K. Okada; H. Onodera; K. Tamaru Layout dependent matching analysis of CMOS circuits Layout dependent matching analysis of CMOS circuits Analog Integrated Circuits and Signal Processing, 25, 3, 309-318 , 25, 3, 309-318 Analog Integrated Circuits and Signal Processing, 25, 3, 309-318 2000/03 Refereed English Research paper(scientific journal) Disclose to all
Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Practical gate resizing technique considering glitch reduction for low power design Practical gate resizing technique considering glitch reduction for low power design Proceedings - Design Automation Conference, 446-451 , 446-451 Proceedings - Design Automation Conference, 446-451 1999/06 Refereed English Research paper(international conference proceedings) Disclose to all
Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Systematic and physical application of multivariate statistics to MOSFET I-V models Systematic and physical application of multivariate statistics to MOSFET I-V models International Workshop on Statistical Metrology, Proceedings, IWSM, 99 TH8391, 34-37 , 99 TH8391, 34-37 International Workshop on Statistical Metrology, Proceedings, IWSM, 99 TH8391, 34-37 1999/06 Refereed English Research paper(international conference proceedings) Disclose to all
Kobayashi, K; Terada, K; Onodera, H; Tamaru, K Kobayashi, K; Terada, K; Onodera, H; Tamaru, K A real-time low-rate video compression algorithm using multi-stage hierarchical vector quantization A real-time low-rate video compression algorithm using multi-stage hierarchical vector quantization IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 2, 215-222 , E82A, 2, 215-222 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E82A, 2, 215-222 1999/02 Refereed English Research paper(scientific journal) Disclose to all
Kenichi Okada; Hidetoshi Onodera; Keikichi Tamaru Kenichi Okada; Hidetoshi Onodera; Keikichi Tamaru Layout dependent matching analysis of CMOS circuits Layout dependent matching analysis of CMOS circuits IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82A, 2, 348-355 , E82A, 2, 348-355 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82A, 2, 348-355 1999/02 Refereed English Research paper(scientific journal) Disclose to all
M. Hashimoto; H. Onodera; K. Tamaru M. Hashimoto; H. Onodera; K. Tamaru A power and delay optimization method using input reordering in cell-based CMOS circuits A power and delay optimization method using input reordering in cell-based CMOS circuits IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82A, 1, 159-166 , E82A, 1, 159-166 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82A, 1, 159-166 1999/01 Refereed English Research paper(scientific journal) Disclose to all
Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru Proposal of a timing model for CMOS logic gates driving a CRC π load Proposal of a timing model for CMOS logic gates driving a CRC π load IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 537-544 , 537-544 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 537-544 1998/11 Refereed English Research paper(international conference proceedings) Disclose to all
A. Hirata; H. Onodera; K. Tamaru A. Hirata; H. Onodera; K. Tamaru Estimation of propagation delay considering short-circuit current for static CMOS gates Estimation of propagation delay considering short-circuit current for static CMOS gates IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 45, 11, 1194-1198 , 45, 11, 1194-1198 IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 45, 11, 1194-1198 1998/11 Refereed English Research paper(scientific journal) Disclose to all
Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Power optimization method considering glitch reduction by gate sizing Power optimization method considering glitch reduction by gate sizing Proceedings of the International Symposium on Low Power Design, 221-226 , 221-226 Proceedings of the International Symposium on Low Power Design, 221-226 1998/08 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; N. Nakamura; K. Terada; H. Onodera; K. Tamarin K. Kobayashi; N. Nakamura; K. Terada; H. Onodera; K. Tamarin An LSI For Low Bit-Rate Image Compression Using Vector Quantization An LSI For Low Bit-Rate Image Compression Using Vector Quantization IEICE Transactions on Electronics, E81C, 5, 718-724 , E81C, 5, 718-724 IEICE Transactions on Electronics, E81C, 5, 718-724 1998/05 Refereed English Research paper(scientific journal) Disclose to all
M. Kondo; H. Onodera; K. Tamaru M. Kondo; H. Onodera; K. Tamaru Model-Adaptable MOSFET Parameter-Extraction Method Using an Intermediate Model Model-Adaptable MOSFET Parameter-Extraction Method Using an Intermediate Model IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17, 5, 400-405 , 17, 5, 400-405 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17, 5, 400-405 1998/05 Refereed English Research paper(scientific journal) Disclose to all
A. Hirata; H. Onodera; K. Tamaru A. Hirata; H. Onodera; K. Tamaru Analytical formulas of output waveform and short-circuit power dissipation for static CMOS gates driving a CRC π load Analytical formulas of output waveform and short-circuit power dissipation for static CMOS gates driving a CRC π load IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E81A, 3, 462-469 , E81A, 3, 462-469 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E81A, 3, 462-469 1998/03 Refereed English Research paper(scientific journal) Disclose to all
K. Tamaru; K. Kobayashi; H. Onodera K. Tamaru; K. Kobayashi; H. Onodera Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP Computers and Electrical Engineering, 24, 1-2, 17-31 , 24, 1-2, 17-31 Computers and Electrical Engineering, 24, 1-2, 17-31 1998/01 Refereed English Research paper(scientific journal) Disclose to all
Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru Input reordering for power and delay optimization Input reordering for power and delay optimization Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 194-198 , 194-198 Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 194-198 1997/09 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetoshi Onodera; Akio Hirata; Teruo Kitamura; Keikichi Tamaru Hidetoshi Onodera; Akio Hirata; Teruo Kitamura; Keikichi Tamaru P2Lib: Process-portable library and its generation system P2Lib: Process-portable library and its generation system Proceedings of the Custom Integrated Circuits Conference, 341-344 , 341-344 Proceedings of the Custom Integrated Circuits Conference, 341-344 1997/09 Refereed English Research paper(international conference proceedings) Disclose to all
K. Kobayashi; M. Kinoshita; H. Onodera; K. Tamaru K. Kobayashi; M. Kinoshita; H. Onodera; K. Tamaru A memory-based parallel processor for vector quantization: fmpp-vq A memory-based parallel processor for vector quantization: fmpp-vq IEICE Transactions on Electronics, E80C, 7, 970-975 , E80C, 7, 970-975 IEICE Transactions on Electronics, E80C, 7, 970-975 1997/07 Refereed English Research paper(scientific journal) Disclose to all
V. Moshnyaga; Y. Mori; H. Onodera; K. Tamaru V. Moshnyaga; Y. Mori; H. Onodera; K. Tamaru Performance-driven macro-block placer for architectural evaluation of ASIC designs Performance-driven macro-block placer for architectural evaluation of ASIC designs IEE Proceedings: Circuits, Devices and Systems, 144, 3, 190-194 , 144, 3, 190-194 IEE Proceedings: Circuits, Devices and Systems, 144, 3, 190-194 1997/06 Refereed English Research paper(international conference proceedings) Disclose to all
M. Kondo; H. Onodera; K. Tamaru M. Kondo; H. Onodera; K. Tamaru A current mode cyclic A/D converter with submicron processes A current mode cyclic A/D converter with submicron processes IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E80A, 2, 360-364 , E80A, 2, 360-364 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E80A, 2, 360-364 1997/02 Refereed English Research paper(scientific journal) Disclose to all
K. Kobayashi; M. Kinoshita; M. Takeuchi; H. Onodera; K. Tamaru K. Kobayashi; M. Kinoshita; M. Takeuchi; H. Onodera; K. Tamaru Functional memory type parallel processor for vector quantization Functional memory type parallel processor for vector quantization Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 665-666 , 665-666 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 665-666 1997/01 Refereed English Research paper(international conference proceedings) Disclose to all
Masaki Kondo; Hidetoshi Onodera; Keikichi Tamara Masaki Kondo; Hidetoshi Onodera; Keikichi Tamara Current mode cyclic A/D converter with a 0.8 μm CMOS process Current mode cyclic A/D converter with a 0.8 μm CMOS process Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 683-684 , 683-684 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 683-684 1997/01 Refereed English Research paper(international conference proceedings) Disclose to all
M. Kondo; H. Onodera; K. Tamaru M. Kondo; H. Onodera; K. Tamaru A method of extracting MOSFET parameters with small model dependency using a common intermediate model A method of extracting MOSFET parameters with small model dependency using a common intermediate model Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 79, 9, 76-86 , 79, 9, 76-86 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 79, 9, 76-86 1996/09 Refereed English Research paper(scientific journal) Disclose to all
Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates Proceedings - IEEE International Symposium on Circuits and Systems, 4, 751-754 , 4, 751-754 Proceedings - IEEE International Symposium on Circuits and Systems, 4, 751-754 1996/05 Refereed English Research paper(international conference proceedings) Disclose to all
Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Global routing algorithm for analog circuits using a resistor array model Global routing algorithm for analog circuits using a resistor array model Proceedings - IEEE International Symposium on Circuits and Systems, 4, 667-670 , 4, 667-670 Proceedings - IEEE International Symposium on Circuits and Systems, 4, 667-670 1996/05 Refereed English Research paper(international conference proceedings) Disclose to all
G. Chen; H. Onodera; K. Tamaru G. Chen; H. Onodera; K. Tamaru Timing and power optimization by gate sizing considering false path Timing and power optimization by gate sizing considering false path Proceedings of the IEEE Great Lakes Symposium on VLSI, 154-159 , 154-159 Proceedings of the IEEE Great Lakes Symposium on VLSI, 154-159 1996/05 Refereed English Research paper(international conference proceedings) Disclose to all
A. Hirata; H. Onodera; K. Tamaru A. Hirata; H. Onodera; K. Tamaru Estimation of Short-Circuit Power Dissipation for Static CMOS Gates Estimation of Short-Circuit Power Dissipation for Static CMOS Gates IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E79A, 3, 304-311 , E79A, 3, 304-311 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E79A, 3, 304-311 1996/03 Refereed English Research paper(scientific journal) Disclose to all
Kazutoshi Kobayashi; Hidetoshi Onodera; Keikichi Tamaru Kazutoshi Kobayashi; Hidetoshi Onodera; Keikichi Tamaru Bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and multiplication Bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and multiplication IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 61-62 , 61-62 IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 61-62 1995/06 Refereed English Research paper(international conference proceedings) Disclose to all
Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Compaction with shape optimization and its application to layout recycling Compaction with shape optimization and its application to layout recycling IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E78A, 2, 169-176 , E78A, 2, 169-176 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E78A, 2, 169-176 1995/02 Refereed English Research paper(scientific journal) Disclose to all
Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru Development of module generators from extracted design procedures - application to analog device generation - Development of module generators from extracted design procedures - application to analog device generation - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E78A, 2, 160-168 , E78A, 2, 160-168 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E78A, 2, 160-168 1995/02 Refereed English Research paper(scientific journal) Disclose to all
Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru Iterative gate sizing approach with accurate delay evaluation Iterative gate sizing approach with accurate delay evaluation IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 422-427 , 422-427 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 422-427 1995/01 Refereed English Research paper(international conference proceedings) Disclose to all
Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Model-adaptable MOSFET parameter extraction system Model-adaptable MOSFET parameter extraction system Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 373-377 , 373-377 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 373-377 1995/01 Refereed English Research paper(international conference proceedings) Disclose to all
Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Kazuhisa Okada; Hidetoshi Onodera; Keikichi Tamaru Compaction with shape optimization Compaction with shape optimization Proceedings of the Custom Integrated Circuits Conference, 545-548 , 545-548 Proceedings of the Custom Integrated Circuits Conference, 545-548 1994/11 Refereed English Research paper(international conference proceedings) Disclose to all
Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru Experiments with power optimization in gate sizing Experiments with power optimization in gate sizing IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E77A, 11, 1913-1916 , E77A, 11, 1913-1916 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E77A, 11, 1913-1916 1994/11 Refereed English Research paper(scientific journal) Disclose to all
Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru Model-adaptable MOSFET parameter extraction method using a common intermediate model Model-adaptable MOSFET parameter extraction method using a common intermediate model Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 323-326 , 323-326 Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 323-326 1994/09 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru Method for analog circuit design that stores and reuses design procedures Method for analog circuit design that stores and reuses design procedures Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 77, 3, 87-96 , 77, 3, 87-96 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 77, 3, 87-96 1994/03 Refereed English Research paper(scientific journal) Disclose to all
Vasily G. Moshnyaga; Hiroshi Mori; Hidetoshi Onodera; Keikichi Tamaru Vasily G. Moshnyaga; Hiroshi Mori; Hidetoshi Onodera; Keikichi Tamaru Layout-driven module selection for register-transfer synthesis of sub-micron ASIC\\'s Layout-driven module selection for register-transfer synthesis of sub-micron ASIC\\'s Proc. of the 1993 IEEE/ACM International Conference on Computer Aided Design,/,100-103 Proc. of the 1993 IEEE/ACM International Conference on Computer Aided Design,/,100-103 1993/11 Refereed English Research paper(international conference proceedings) Disclose to all
Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru Takashi Morie; Hidetoshi Onodera; Keikichi Tamaru System for analog circuit design that stores and re-uses design procedures System for analog circuit design that stores and re-uses design procedures Proceedings of the Custom Integrated Circuits Conference, 13.4.1-13.4.4 , 13.4.1-13.4.4 Proceedings of the Custom Integrated Circuits Conference, 13.4.1-13.4.4 1993/09 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru Branch-and-bound placement for building block layout Branch-and-bound placement for building block layout Electronics and Communications in Japan Part III: Fundamental Electronic Science, 76, 7, 15-26 , 76, 7, 15-26 Electronics and Communications in Japan Part III: Fundamental Electronic Science, 76, 7, 15-26 1993/07 Refereed English Research paper(scientific journal) Disclose to all
Kazutoshi Kobayashi; Keikichi Tamaru; Hirito Yasuura; Hidetoshi Onodera Kazutoshi Kobayashi; Keikichi Tamaru; Hirito Yasuura; Hidetoshi Onodera Bit-parallel block-parallel functional memory type parallel processor architecture Bit-parallel block-parallel functional memory type parallel processor architecture IEICE Transactions on Electronics, E76C, 7, 1151-1158 , E76C, 7, 1151-1158 IEICE Transactions on Electronics, E76C, 7, 1151-1158 1993/07 Refereed English Research paper(scientific journal) Disclose to all
Hdetoshi Onodera; Kiyoshi Takeshita; Keikichi Tamaru Hdetoshi Onodera; Kiyoshi Takeshita; Keikichi Tamaru Hardware architecture for Kohonen network Hardware architecture for Kohonen network IEICE Transactions on Electronics, E76C, 7, 1159-1167 , E76C, 7, 1159-1167 IEICE Transactions on Electronics, E76C, 7, 1159-1167 1993/07 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; K. Tamaru H. Onodera; K. Tamaru Analog circuit placement - Branch-and-bound placement with shape optimization Analog circuit placement - Branch-and-bound placement with shape optimization Proceedings of the Custom Integrated Circuits Conference, 11.5.1-11.5.6 , 11.5.1-11.5.6 Proceedings of the Custom Integrated Circuits Conference, 11.5.1-11.5.6 1992/09 Refereed English Research paper(international conference proceedings) Disclose to all
AWAI, I; ONODERA, H; CHOI, Y; NAKAJIMA, M; IKENOUE, J AWAI, I; ONODERA, H; CHOI, Y; NAKAJIMA, M; IKENOUE, J IMPROVED METHOD OF LOSS MEASUREMENT FOR OPTICAL WAVE-GUIDES BY USE OF A RECTANGULAR GLASS PROBE IMPROVED METHOD OF LOSS MEASUREMENT FOR OPTICAL WAVE-GUIDES BY USE OF A RECTANGULAR GLASS PROBE APPLIED OPTICS, 31, 12, 2078-2084 , 31, 12, 2078-2084 APPLIED OPTICS, 31, 12, 2078-2084 1992/04 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru Branch-and-bound placement for building block layout Branch-and-bound placement for building block layout Proceedings - Design Automation Conference, 433-439 , 433-439 Proceedings - Design Automation Conference, 433-439 1991/06 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera, Y. Taniguchi, K. Tamaru H. Onodera, Y. Taniguchi, K. Tamaru Branch-and-Bound Placement for Building Block Layout Branch-and-Bound Placement for Building Block Layout International Workshop on Layout Synthesis International Workshop on Layout Synthesis 1990/07 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetoshi Onodera; Kiyoshi Takeshita; Keikichi Tamaru Hidetoshi Onodera; Kiyoshi Takeshita; Keikichi Tamaru Hardware architecture for Kohonen network Hardware architecture for Kohonen network Proceedings - IEEE International Symposium on Circuits and Systems, 2, 1073-1077 , 2, 1073-1077 Proceedings - IEEE International Symposium on Circuits and Systems, 2, 1073-1077 1990/05 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetoshi Onodera; Hiroyuki Kanbara; Keikichi Tamaru Hidetoshi Onodera; Hiroyuki Kanbara; Keikichi Tamaru Operational-amplifier compilation with performance optimization Operational-amplifier compilation with performance optimization IEEE Journal of Solid-State Circuits, 25, 2, 466-473 , 25, 2, 466-473 IEEE Journal of Solid-State Circuits, 25, 2, 466-473 1990/04 Refereed English Research paper(scientific journal) Disclose to all
Mamoru Sakamoto; Hidetoshi Onodera; Keikichi Tamaru Mamoru Sakamoto; Hidetoshi Onodera; Keikichi Tamaru Shiftcompaction. Quasi-two-dimensional compaction method for symbolic layout Shiftcompaction. Quasi-two-dimensional compaction method for symbolic layout Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 73, 8, 40-51 , 73, 8, 40-51 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 73, 8, 40-51 1990 Refereed English Research paper(scientific journal) Disclose to all
Ryosuke Okuda; Keikichi Tamaru; Hidetoshi Onodera Ryosuke Okuda; Keikichi Tamaru; Hidetoshi Onodera Layout design methodology using data description with correspondence between circuit and layout Layout design methodology using data description with correspondence between circuit and layout Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 72, 12, 55-62 , 72, 12, 55-62 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 72, 12, 55-62 1989/12 Refereed English Research paper(scientific journal) Disclose to all
R. Okuda, T. Sato, H. Onodera, K. Tamaru R. Okuda, T. Sato, H. Onodera, K. Tamaru An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints Proc. of International Conference on Computer-Aided Design,/,148-151 Proc. of International Conference on Computer-Aided Design,/,148-151 1989/11 Refereed English Research paper(international conference proceedings) Disclose to all
Hidetoshi Onodera; Keikichi Tamaru Hidetoshi Onodera; Keikichi Tamaru Block placement procedure using a force model Block placement procedure using a force model Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 72, 11, 87-96 , 72, 11, 87-96 Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 72, 11, 87-96 1989/11 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; H. Kanbara; K. Tamaru H. Onodera; H. Kanbara; K. Tamaru Operational amplifier compilation with performance optimization Operational amplifier compilation with performance optimization Proceedings of the Custom Integrated Circuits Conference, 17.4.1-17.4.6 , 17.4.1-17.4.6 Proceedings of the Custom Integrated Circuits Conference, 17.4.1-17.4.6 1989/09 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera; M. Sakamoto; T. Kurihara; K. Tamaru H. Onodera; M. Sakamoto; T. Kurihara; K. Tamaru Step by step placement strategies for building block layout Step by step placement strategies for building block layout Proceedings - IEEE International Symposium on Circuits and Systems, 2, 921-926 , 2, 921-926 Proceedings - IEEE International Symposium on Circuits and Systems, 2, 921-926 1989/05 Refereed English Research paper(international conference proceedings) Disclose to all
ONODERA H;KANBARA H;TAMARU K ONODERA H;KANBARA H;TAMARU K Module generation of a CMOS op amp using a non-linear optimization method. Module generation of a CMOS op amp using a non-linear optimization method. Trans Inst Electron Inf Commun Eng E, 71, 10, 947-949 , 71, 10, 947-949 Trans Inst Electron Inf Commun Eng E, 71, 10, 947-949 1988/10 Refereed English Research paper(scientific journal) Disclose to all
ONODERA, H; TATEISHI, T; TAMARU, K ONODERA, H; TATEISHI, T; TAMARU, K A CYCLIC A/D CONVERTER THAT DOES NOT REQUIRE RATIO-MATCHED COMPONENTS A CYCLIC A/D CONVERTER THAT DOES NOT REQUIRE RATIO-MATCHED COMPONENTS IEEE JOURNAL OF SOLID-STATE CIRCUITS, 23, 1, 152-158 , 23, 1, 152-158 IEEE JOURNAL OF SOLID-STATE CIRCUITS, 23, 1, 152-158 1988/02 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera; Tetsuo Tateishi; Keikichi Tamaru Hidetoshi Onodera; Tetsuo Tateishi; Keikichi Tamaru CYCLIC SWITCHED CAPACITOR A-D, D-A CONVERTER. CYCLIC SWITCHED CAPACITOR A-D, D-A CONVERTER. Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 70, 9, 56-65 , 70, 9, 56-65 Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 70, 9, 56-65 1987/09 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; T. Tateishi; K. Tamaru H. Onodera; T. Tateishi; K. Tamaru CYCLIC A/D CONVERTER THAT DOES NOT REQUIRE RATIO-MATCHED COMPONENTS. CYCLIC A/D CONVERTER THAT DOES NOT REQUIRE RATIO-MATCHED COMPONENTS. Digest of Technical Papers - Symposium on VLSI Technology, 117-118 , 117-118 Digest of Technical Papers - Symposium on VLSI Technology, 117-118 1987/06 Refereed English Research paper(international conference proceedings) Disclose to all
Keikichi Tamaru; Hidetoshi Onodera Keikichi Tamaru; Hidetoshi Onodera SYSTEM DESIGN OF A SPECIAL-PURPOSE COMPUTER FOR LSI DESIGN RULE CHECKING. SYSTEM DESIGN OF A SPECIAL-PURPOSE COMPUTER FOR LSI DESIGN RULE CHECKING. Systems and Computers in Japan, 18, 2, 43-54 , 18, 2, 43-54 Systems and Computers in Japan, 18, 2, 43-54 1987/02 Refereed English Research paper(scientific journal) Disclose to all
ONODERA, H; NAKAJIMA, M ONODERA, H; NAKAJIMA, M HIGH-EFFICIENCY LIGHT-MODULATOR USING GUIDED-TO-RADIATION MODE-COUPLING IN A GRADED-INDEX WAVE-GUIDE HIGH-EFFICIENCY LIGHT-MODULATOR USING GUIDED-TO-RADIATION MODE-COUPLING IN A GRADED-INDEX WAVE-GUIDE APPLIED OPTICS, 25, 13, 2175-2183 , 25, 13, 2175-2183 APPLIED OPTICS, 25, 13, 2175-2183 1986/07 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera; Keikichi Tamaru Hidetoshi Onodera; Keikichi Tamaru CYCLIC ANALOG-TO-DIGITAL CONVERTER USING SWITCHED CAPACITOR INTEGRATOR. CYCLIC ANALOG-TO-DIGITAL CONVERTER USING SWITCHED CAPACITOR INTEGRATOR. Proceedings - IEEE International Symposium on Circuits and Systems, 333-336 , 333-336 Proceedings - IEEE International Symposium on Circuits and Systems, 333-336 1985/05 Refereed English Research paper(international conference proceedings) Disclose to all
H. Onodera, M. Nakajima H. Onodera, M. Nakajima High-Efficiency Light Modulator Using Guided-to-Radiation Mode Coupling (共著) High-Efficiency Light Modulator Using Guided-to-Radiation Mode Coupling (共著) Sino-Japanese Joint Meeting on Optical Fiber Science and Electromagnetic Theory,/,183-188 Sino-Japanese Joint Meeting on Optical Fiber Science and Electromagnetic Theory,/,183-188 1985/03 Refereed English Research paper(international conference proceedings) Disclose to all
Ikuo Awai; Hidetoshi Onodera; Masamtisu Nakajima; Jun-ichi Ikenoue Ikuo Awai; Hidetoshi Onodera; Masamtisu Nakajima; Jun-ichi Ikenoue METHOD OF MEASURING LOSS FOR OPTICAL WAVEGUIDES BY USE OF A RECTANGULAR GLASS PROBE. METHOD OF MEASURING LOSS FOR OPTICAL WAVEGUIDES BY USE OF A RECTANGULAR GLASS PROBE. Memoirs of the Faculty of Engineering, Kyoto University, 46, pt 4, 24-41 , 46, pt 4, 24-41 Memoirs of the Faculty of Engineering, Kyoto University, 46, pt 4, 24-41 1984/04 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera; Masahiro Okuda; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue Hidetoshi Onodera; Masahiro Okuda; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue Nb-DIFFUSED LiTaO//3 WAVEGUIDES AND LIGHT MODULATORS BY USE OF GUIDED-TO-RADIATION MODE COUPLING. Nb-DIFFUSED LiTaO//3 WAVEGUIDES AND LIGHT MODULATORS BY USE OF GUIDED-TO-RADIATION MODE COUPLING. Electronics & communications in Japan, 67, 4, 110-118 , 67, 4, 110-118 Electronics & communications in Japan, 67, 4, 110-118 1984/04 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue Hidetoshi Onodera; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue LIGHT INTENSITY MODULATION BASED ON GUIDED-TO-RADIATION MODE COUPLING IN HETEROSTRUCTURE WAVEGUIDES. LIGHT INTENSITY MODULATION BASED ON GUIDED-TO-RADIATION MODE COUPLING IN HETEROSTRUCTURE WAVEGUIDES. Applied Optics, 23, 1, 118-123 , 23, 1, 118-123 Applied Optics, 23, 1, 118-123 1984/01 Refereed English Research paper(scientific journal) Disclose to all
Hidetoshi Onodera; Ikuo Awai; Jun-ichi Ikenoue Hidetoshi Onodera; Ikuo Awai; Jun-ichi Ikenoue REFRACTIVE-INDEX MEASUREMENT OF BULK MATERIALS: PRISM COUPLING METHOD. REFRACTIVE-INDEX MEASUREMENT OF BULK MATERIALS: PRISM COUPLING METHOD. Applied Optics, 22, 8, 1194-1197 , 22, 8, 1194-1197 Applied Optics, 22, 8, 1194-1197 1983/08 Refereed English Research paper(scientific journal) Disclose to all
Naoki Shibanuma; Hidetoshi Onodera; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue Naoki Shibanuma; Hidetoshi Onodera; Ikuo Awai; Masamitsu Nakajima; Jun-ichi Ikenoue ANALYSIS OF GRADED-INDEX FIBERS BY MEANS OF THE TRANSVERSE RESONANCE METHOD. ANALYSIS OF GRADED-INDEX FIBERS BY MEANS OF THE TRANSVERSE RESONANCE METHOD. Journal of the Optical Society of America, 72, 11, 1502-1505 , 72, 11, 1502-1505 Journal of the Optical Society of America, 72, 11, 1502-1505 1982/11 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Nakajima; Hidetoshi Onodera; Jun-ichi Ikenoue Masamitsu Nakajima; Hidetoshi Onodera; Jun-ichi Ikenoue COUPLED MULTIMODE ANALYSIS OF ANISOTROPIC HETEROSTRUCTURE WAVEGUIDES AND ITS APPLICATION TO A LIGHT MODULATOR. COUPLED MULTIMODE ANALYSIS OF ANISOTROPIC HETEROSTRUCTURE WAVEGUIDES AND ITS APPLICATION TO A LIGHT MODULATOR. Radio Science, 17, 1, 117-124 , 17, 1, 117-124 Radio Science, 17, 1, 117-124 1982/01 Refereed English Research paper(scientific journal) Disclose to all
Masamitsu Nakajima; Hidetoshi Onodera; Ikuo Awai; Jun-ichi Ikenoue Masamitsu Nakajima; Hidetoshi Onodera; Ikuo Awai; Jun-ichi Ikenoue HIGH-EFFICIENCY LIGHT MODULATOR USING GUIDED-TO-RADIATION MODE COUPLING: A PROPOSAL. HIGH-EFFICIENCY LIGHT MODULATOR USING GUIDED-TO-RADIATION MODE COUPLING: A PROPOSAL. Applied Optics, 20, 14, 2439-2443 , 20, 14, 2439-2443 Applied Optics, 20, 14, 2439-2443 1981/07 Refereed English Research paper(scientific journal) Disclose to all
H. Onodera; I. Awai; M. Nakajima; J. Ikenoue H. Onodera; I. Awai; M. Nakajima; J. Ikenoue EXPERIMENT ON LIGHT INTENSITY MODULATION BASED ON GUIDED-TO-RADIATION MODE COUPLING IN HETERO-STRUCTURE THIN FILM WAVEGUIDE. EXPERIMENT ON LIGHT INTENSITY MODULATION BASED ON GUIDED-TO-RADIATION MODE COUPLING IN HETERO-STRUCTURE THIN FILM WAVEGUIDE. IEEE MTT-S International Microwave Symposium Digest, 525-527 , 525-527 IEEE MTT-S International Microwave Symposium Digest, 525-527 1981/05 Refereed English Research paper(international conference proceedings) Disclose to all
ONODERA H;AWAI I;NAKAJIMA M;IKENOUE J ONODERA H;AWAI I;NAKAJIMA M;IKENOUE J Guided-to-radiation mode conversion in hetero-structure planar waveguides and its application to a light modulator. Guided-to-radiation mode conversion in hetero-structure planar waveguides and its application to a light modulator. IEEE MTT-S Int Microw Symp Dig, 1980, 311-313 , 1980, 311-313 IEEE MTT-S Int Microw Symp Dig, 1980, 311-313 1980/05 Refereed English Research paper(international conference proceedings) Disclose to all

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Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Bibliography Bibliography(Japanese) Bibliography(English) Publication date Refereed paper Language Publishing type Disclose
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design 8th International Workshop on Variability Modeling and Charactorization (VMC) 8th International Workshop on Variability Modeling and Charactorization (VMC) 8th International Workshop on Variability Modeling and Charactorization (VMC) 2015/11 Refereed Disclose to all
竹下俊宏,西澤真一,Islam A.K.M. Mahfuzul,石原 亨,小野寺秀俊 竹下俊宏,西澤真一,Islam A.K.M. Mahfuzul,石原 亨,小野寺秀俊 動作状況に応じた電源電圧と基板バイアスの同時調節によるLSIのエネルギー効率最大化 動作状況に応じた電源電圧と基板バイアスの同時調節によるLSIのエネルギー効率最大化 電子情報通信学会 2014年総合大会 電子情報通信学会 2014年総合大会 2014/03/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera 雨貝太郎、土谷亮、中野慎介、野河正史、小泉弘、小野寺秀俊 Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera Effect of Low Shield in On-Chip Millimeter-Wave Transmission Line ミリ波帯オンチップ伝送線路における下層シールドの影響 Effect of Low Shield in On-Chip Millimeter-Wave Transmission Line 2013 IEICE General Conference 電子情報通信学会総合大会 2013 IEICE General Conference 2013/03/19 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera 松本高士、小林和淑、小野寺秀俊 Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty ランダム・テレグラフ・ノイズがCMOS組合せ回路の遅延ゆらぎに及ぼす影響 Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty ACM The TAU Workshop (TAU) 2013, 2, C-12-54, 125-125 電子情報通信学会 総合大会, 2, C-12-54, 125-125 ACM The TAU Workshop (TAU) 2013, 2, C-12-54, 125-125 2013/03 Japanese Summary of the papers read (national conference and other science council) Disclose to all
古田 潤;小林 和淑;小野寺 秀俊 古田 潤;小林 和淑;小野寺 秀俊 A-3-7 ソフトエラーによる多ビットエラーのラッチ間距離依存性の評価(A-3.VLSI設計技術,一般セッション) A-3-7 ソフトエラーによる多ビットエラーのラッチ間距離依存性の評価(A-3.VLSI設計技術,一般セッション) 電子情報通信学会ソサイエティ大会講演論文集, 2012, 0 電子情報通信学会ソサイエティ大会講演論文集, 2012, 0 , 2012, 0 2012/10 Japanese Summary of the papers read (national conference and other science council) Disclose to all
三木淳司、松本高士(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 三木淳司、松本高士(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 劣化測定と回復測定を高速に切り替え可能なNBTI測定回路の特性評価 劣化測定と回復測定を高速に切り替え可能なNBTI測定回路の特性評価 電子情報通信学会ソサイエティ大会 電子情報通信学会ソサイエティ大会 2012/09/14 Japanese Summary of the papers read (national conference and other science council) Disclose to all
古田潤(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) 古田潤(京都大学)、小林和淑(京都工芸繊維大学)、小野寺秀俊(京都大学) ソフトエラーによる多ビットエラーのラッチ間距離依存性の評価 ソフトエラーによる多ビットエラーのラッチ間距離依存性の評価 電子情報通信学会ソサイエティ大会 電子情報通信学会ソサイエティ大会 2012/09/14 Japanese Summary of the papers read (national conference and other science council) Disclose to all
三木 淳司;松本 高士;小林 和淑;小野寺 秀俊 三木 淳司;松本 高士;小林 和淑;小野寺 秀俊 C-12-44 劣化測定と回復測定を高速に切り替え可能なNBTI測定回路の特性評価(デバイス・回路協調設計技術(2),C-12. 集積回路,一般セッション) C-12-44 劣化測定と回復測定を高速に切り替え可能なNBTI測定回路の特性評価(デバイス・回路協調設計技術(2),C-12. 集積回路,一般セッション) 電子情報通信学会ソサイエティ大会講演論文集, 2012, 2 電子情報通信学会ソサイエティ大会講演論文集, 2012, 2 , 2012, 2 2012/08/28 Japanese Summary of the papers read (national conference and other science council) Disclose to all
榎並 達也、宮脇 成和、土谷 亮、小野寺 秀俊 榎並 達也、宮脇 成和、土谷 亮、小野寺 秀俊 インダクティブピーキングを用いた増幅回路における解析的ジッタ予測手法 インダクティブピーキングを用いた増幅回路における解析的ジッタ予測手法 2012年電子情報通信学会総合大会, C-12-61, C-12-61-C-12-61 2012年電子情報通信学会総合大会, C-12-61, C-12-61-C-12-61 , C-12-61-C-12-61 2012/03/22 Japanese Summary of the papers read (national conference and other science council) Disclose to all
川中 啓敬、岸根 桂路、土谷 亮、小野寺 秀俊 川中 啓敬、岸根 桂路、土谷 亮、小野寺 秀俊 完全差動回路構成GVCOの高速化設計 完全差動回路構成GVCOの高速化設計 2012年電子情報通信学会総合大会, C-12-46, C-12-46-C-12-46 2012年電子情報通信学会総合大会, C-12-46, C-12-46-C-12-46 , C-12-46-C-12-46 2012/03/22 Japanese Summary of the papers read (national conference and other science council) Disclose to all
釡江 典裕、土谷 亮、小野寺 秀俊 釡江 典裕、土谷 亮、小野寺 秀俊 細粒度基板電圧制御に用いるDA変換回路 細粒度基板電圧制御に用いるDA変換回路 2012年電子情報通信学会総合大会, C-12-51, C-12-51-C-12-51 2012年電子情報通信学会総合大会, C-12-51, C-12-51-C-12-51 , C-12-51-C-12-51 2012/03/22 Japanese Summary of the papers read (national conference and other science council) Disclose to all
三木 淳司、松本松本 高士、小林 和淑、小野寺 秀俊 三木 淳司、松本松本 高士、小林 和淑、小野寺 秀俊 劣化回復測定を高速に切り替え可能なNBTI評価回路 劣化回復測定を高速に切り替え可能なNBTI評価回路 2012年電子情報通信学会総合大会, C-12-24, C-12-24-C-12-24 2012年電子情報通信学会総合大会, C-12-24, C-12-24-C-12-24 , C-12-24-C-12-24 2012/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
古田潤(京都大)、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) 古田潤(京都大)、 小林和淑(京都工繊大)、 小野寺秀俊(京都大) チェインにおけるパルス幅縮小を利用したSETパルス幅測定回路 チェインにおけるパルス幅縮小を利用したSETパルス幅測定回路 電子情報通信学会基礎・境界ソサイエティ大会, C-12-21, C-12-21-C-12-21 電子情報通信学会基礎・境界ソサイエティ大会, C-12-21, C-12-21-C-12-21 , C-12-21-C-12-21 2011/09/13 Japanese Summary of the papers read (national conference and other science council) Disclose to all
松本高士(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) 松本高士(京都大学)、 小林和淑(京都工芸繊維大学)、 小野寺秀俊(京都大学) ディジタル回路遅延の経年劣化とそのモデル化について ディジタル回路遅延の経年劣化とそのモデル化について 電子情報通信学会基礎・境界ソサイエティ大会, C-12-20, C-12-20-C-12-20 電子情報通信学会基礎・境界ソサイエティ大会, C-12-20, C-12-20-C-12-20 , C-12-20-C-12-20 2011/09/13 Japanese Summary of the papers read (national conference and other science council) Disclose to all
宮脇成和、土谷 亮、小野寺秀俊 宮脇成和、土谷 亮、小野寺秀俊 MOSトランジスタの基板抵抗がインダクティブピーキング回路の周波数特性に与える影響 MOSトランジスタの基板抵抗がインダクティブピーキング回路の周波数特性に与える影響 2010年 電子情報通信学会ソサイエティ大会, C-12-26-C-12-26 2010年 電子情報通信学会ソサイエティ大会, C-12-26-C-12-26 , C-12-26-C-12-26 2010/09/17 Japanese Summary of the papers read (national conference and other science council) Disclose to all
釡江典裕、土谷 亮、小野寺秀俊 釡江典裕、土谷 亮、小野寺秀俊 基板電圧の制御回路とその面積オーバヘッド 基板電圧の制御回路とその面積オーバヘッド 2010年 電子情報通信学会ソサイエティ大会, C-12-22-C-12-22 2010年 電子情報通信学会ソサイエティ大会, C-12-22-C-12-22 , C-12-22-C-12-22 2010/09/16 Japanese Summary of the papers read (national conference and other science council) Disclose to all
牧野紘明、松本高士、小林和淑、小野寺秀俊 牧野紘明、松本高士、小林和淑、小野寺秀俊 Subthreshold Leak電流によるNBTI劣化,回復の測定 Subthreshold Leak電流によるNBTI劣化,回復の測定 電子情報通信学会総合大会, C-12-68-C-12-68 電子情報通信学会総合大会, C-12-68-C-12-68 , C-12-68-C-12-68 2010/03/19 Japanese Summary of the papers read (national conference and other science council) Disclose to all
砂川洋輝、土谷亮、小野寺秀俊 砂川洋輝、土谷亮、小野寺秀俊 ランダムばらつきがD-FFのタイミング制約に与える影響 ランダムばらつきがD-FFのタイミング制約に与える影響 電子情報通信学会総合大会, C-12-61-C-12-61 電子情報通信学会総合大会, C-12-61-C-12-61 , C-12-61-C-12-61 2010/03/19 Japanese Summary of the papers read (national conference and other science council) Disclose to all
岸根桂路、稲葉博美、大友祐輔、中村誠、小野寺秀俊 岸根桂路、稲葉博美、大友祐輔、中村誠、小野寺秀俊 ωn ドメイン設計手法によるCDR-ICの低ジッタ化 ωn ドメイン設計手法によるCDR-ICの低ジッタ化 電子情報通信学会総合大会, C-12-56-C-12-56 電子情報通信学会総合大会, C-12-56-C-12-56 , C-12-56-C-12-56 2010/03/19 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera 牧野紘明、小林和淑、小野寺秀俊 Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera A Circuit to Measure the Frequency Dependance of NBTI NBTI周波数依存性測定回路の検討 A Circuit to Measure the Frequency Dependance of NBTI IEICE Society Conference, C-12-30, 94-94 2009年電子情報通信学会ソサイエティ大会, C-12-30, 94-94 IEICE Society Conference, C-12-30, 94-94 2009/09/16 Japanese Summary of the papers read (national conference and other science council) Disclose to all
小野寺秀俊 小野寺秀俊 ディペンダブルVLSIプラットフォームへの挑戦 ディペンダブルVLSIプラットフォームへの挑戦 2009年電子情報通信学会総合大会 基礎・境界講演論文集, Al-1-3, SS-35-SS-36 2009年電子情報通信学会総合大会 基礎・境界講演論文集, Al-1-3, SS-35-SS-36 , Al-1-3, SS-35-SS-36 2009/03/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
牧野紘明、小林和淑、小野寺秀俊 牧野紘明、小林和淑、小野寺秀俊 リーク電流によるNBTI特性の実測による評価 リーク電流によるNBTI特性の実測による評価 2009年電子情報通信学会総合大会 エレクトロニクス講演論文集2, C-12-18, 106-106 2009年電子情報通信学会総合大会 エレクトロニクス講演論文集2, C-12-18, 106-106 , C-12-18, 106-106 2009/03/17 Japanese Summary of the papers read (national conference and other science council) Disclose to all
砂川 洋輝、土谷 亮、小野寺 秀俊 砂川 洋輝、土谷 亮、小野寺 秀俊 レイアウト規則性導入によるパターン転写精度の改善効果 レイアウト規則性導入によるパターン転写精度の改善効果 2008年電子情報通信学会ソサイエティ大会, C-12-40, 109-109 2008年電子情報通信学会ソサイエティ大会, C-12-40, 109-109 , C-12-40, 109-109 2008/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
久保木 猛、土谷 亮、小野寺 秀俊 久保木 猛、土谷 亮、小野寺 秀俊 オンチップ差動伝送線路の構造と下層配線からのノイズの関係 オンチップ差動伝送線路の構造と下層配線からのノイズの関係 2008年電子情報通信学会ソサイエティ大会, C-12-39, 108-198 2008年電子情報通信学会ソサイエティ大会, C-12-39, 108-198 , C-12-39, 108-198 2008/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
土谷 亮、小野寺 秀俊 土谷 亮、小野寺 秀俊 土谷 亮、小野寺 秀俊 Modeling of On-Chip Transmission-Line for Millimeter Wave CMOS Circuits CMOSミリ波回路におけるオンチップ伝送線路のモデル化 Modeling of On-Chip Transmission-Line for Millimeter Wave CMOS Circuits 2008年電子情報通信学会ソサイエティ大会, CK-2-10, SS-18-SS-19 2008年電子情報通信学会ソサイエティ大会, CK-2-10, SS-18-SS-19 2008年電子情報通信学会ソサイエティ大会, CK-2-10, SS-18-SS-19 2008/09/16 Japanese Summary of the papers read (national conference and other science council) Disclose to all
小野寺秀俊 小野寺秀俊 ばらつき考慮DFMの課題と期待 ばらつき考慮DFMの課題と期待 電子情報通信学会総合大会予稿集, AT1-1-AT1-1 電子情報通信学会総合大会予稿集, AT1-1-AT1-1 , AT1-1-AT1-1 2008/03/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera 久米洋平、小林和淑、小野寺秀俊 Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera Accelaration of Variation Measurement Using a Portable Test Equipment 卓上テスト環境によるばらつき測定の高速化 Accelaration of Variation Measurement Using a Portable Test Equipment IEICE General Conference, C-12-3-C-12-3 電子情報通信学会総合大会予稿集, C-12-3-C-12-3 IEICE General Conference, C-12-3-C-12-3 2007/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
関 良平、土谷 亮、小野寺 秀俊 関 良平、土谷 亮、小野寺 秀俊 将来の微細プロセスにおけるDVSとPower Gatingの比較 将来の微細プロセスにおけるDVSとPower Gatingの比較 電子情報通信学会ソサイエティ大会, 56-56 電子情報通信学会ソサイエティ大会, 56-56 , 56-56 2006/09/21 Japanese Summary of the papers read (national conference and other science council) Disclose to all
上村 晋一郎、土谷 亮、橋本 昌宜、小野寺 秀俊 上村 晋一郎、土谷 亮、橋本 昌宜、小野寺 秀俊 ロードマップに準拠したSPICEトランジスタモデルの構築 ロードマップに準拠したSPICEトランジスタモデルの構築 電子情報通信学会総合大会, 81-81 電子情報通信学会総合大会, 81-81 , 81-81 2006/03/25 Japanese Summary of the papers read (national conference and other science council) Disclose to all
河野 武志、小野寺 秀俊 河野 武志、小野寺 秀俊 SSTAにおける多入力ゲートの出力遷移時間の扱い方 SSTAにおける多入力ゲートの出力遷移時間の扱い方 電子情報通信学会総合大会, 78-78 電子情報通信学会総合大会, 78-78 , 78-78 2006/03/25 Japanese Summary of the papers read (national conference and other science council) Disclose to all
福岡 孝之、土谷 亮、小野寺 秀俊 福岡 孝之、土谷 亮、小野寺 秀俊 配線とトランジスタのばらつきを考慮したバッファの挿入方法 配線とトランジスタのばらつきを考慮したバッファの挿入方法 電子情報通信学会総合大会, 77-77 電子情報通信学会総合大会, 77-77 , 77-77 2006/03/25 Japanese Summary of the papers read (national conference and other science council) Disclose to all
S. Uemura, M. Hashimoto, H. Onodera 上村 晋一朗 橋本昌宜 小野寺秀俊 S. Uemura, M. Hashimoto, H. Onodera Estimation for Equivalent Parallel Resistance of LC Oscillators Including Resitance Components of MOSFETs LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり Estimation for Equivalent Parallel Resistance of LC Oscillators Including Resitance Components of MOSFETs IEICE Society Conference, C-12-39, 119-119 電子情報通信学会ソサイエティ大会, C-12-39, 119-119 IEICE Society Conference, C-12-39, 119-119 2005/09/21 Japanese Summary of the papers read (national conference and other science council) Disclose to all
土谷亮、橋本昌宜、小野寺秀俊 土谷亮、橋本昌宜、小野寺秀俊 オンチップ伝送線路の基板損失に対する下層配線の影響 オンチップ伝送線路の基板損失に対する下層配線の影響 2005年電子情報通信学会総合大会, 77-77 2005年電子情報通信学会総合大会, 77-77 , 77-77 2005/03/24 Japanese Summary of the papers read (national conference and other science council) Disclose to all
橋本昌宜、小野寺秀俊 橋本昌宜、小野寺秀俊 微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応-- 微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応-- 2004年電子情報通信学会ソサイエティ大会講演論文集, 予稿なし 2004年電子情報通信学会ソサイエティ大会講演論文集, 予稿なし , 予稿なし 2004/09/23 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Muramatsu, M. Hashimoto, H. Onodera 村松篤、橋本昌宜、小野寺秀俊 A. Muramatsu, M. Hashimoto, H. Onodera Effect of On-chip Wire Inductance on Power Supply Fluctuation 電源電圧変動に対するオンチップ配線インダクタンスの影響 Effect of On-chip Wire Inductance on Power Supply Fluctuation Proc. General Conference of IEICE, A-3-22, 89-89 2004年電子情報通信学会総合大会, A-3-22, 89-89 Proc. General Conference of IEICE, A-3-22, 89-89 2004/03/11 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Higuchi, K. Kobayashi, H. Onodera 樋口昭彦、小林和淑、小野寺秀俊 A. Higuchi, K. Kobayashi, H. Onodera Power Model Analysis for a Register File on a Soft-core Processor ソフトコアプロセッサにおけるレジスタファイルの消費電力モデル Power Model Analysis for a Register File on a Soft-core Processor Proc. General Conference of IEICE, A-3-4, 71-71 2004年電子情報通信学会総合大会, A-3-4, 71-71 Proc. General Conference of IEICE, A-3-4, 71-71 2004/03/11 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Muramatsu, M. Hashimoto, H. Onodera 村松篤、橋本昌宜、小野寺秀俊 A. Muramatsu, M. Hashimoto, H. Onodera Fast Power Grid Analysis with Simplified Equivalent Circuit 電源配線の等価回路簡略化による電源解析高速化の検討 Fast Power Grid Analysis with Simplified Equivalent Circuit 情報処理学会関西支部支部大会, 169-172 情報処理学会関西支部支部大会, 169-172 情報処理学会関西支部支部大会, 169-172 2003/10/31 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Aramoto, Y. Yuyama, K. Kobayashi, H. Onodera 荒本雅夫、湯山洋一、小林和淑、小野寺秀俊 M. Aramoto, Y. Yuyama, K. Kobayashi, H. Onodera Area/Throughput Trade-off on Behavioral Synthesis 動作合成における制約条件の検討 Area/Throughput Trade-off on Behavioral Synthesis Proc. IEICE General Conference, A-3-7, 74 電子情報通信学会総合大会, A-3-7, 74 Proc. IEICE General Conference, A-3-7, 74 2003/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Okada, K. Yamaoka, H. Onodera 岡田健一、山岡健人、小野寺秀俊 K. Okada, K. Yamaoka, H. Onodera Statistical Gate-delay Modeling with Intra-gate Variability ゲート内ばらつきを考慮した遅延ばらつきのモデル化手法 Statistical Gate-delay Modeling with Intra-gate Variability Proc. IEICE General Conference, A-3-22, 89 電子情報通信学会総合大会, A-3-22, 89 Proc. IEICE General Conference, A-3-22, 89 2003/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera 土谷亮、橋本昌宜、小野寺秀俊 A. Tsuchiya, M. Hashimoto, H. Onodera Effects of orthogonal layer interconnects on coupling with interconnects in a lower layer 信号配線と下層配線との結合に対する直交配線の影響 Effects of orthogonal layer interconnects on coupling with interconnects in a lower layer Proc. IEICE General Conference, A-3-14, 81 電子情報通信学会総合大会, A-3-14, 81 Proc. IEICE General Conference, A-3-14, 81 2003/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Muramatsu, M. Hashimoto, H. Onodera 村松篤、橋本昌宜、小野寺秀俊 A. Muramatsu, M. Hashimoto, H. Onodera Optimal parasitic resistance of on-chip decoupling capacitor オンチップデカップリング容量の最適寄生抵抗値の決定法 Optimal parasitic resistance of on-chip decoupling capacitor Proc. IEICE General Conference, A-3-13, 80 電子情報通信学会総合大会, A-3-13, 80 Proc. IEICE General Conference, A-3-13, 80 2003/03/20 Japanese Summary of the papers read (national conference and other science council) Disclose to all
T. Miyazaki, A. Shinmyo, M. Hashimoto, H. Onodera 宮崎崇仁、新名亮規、橋本昌宜、小野寺秀俊 T. Miyazaki, A. Shinmyo, M. Hashimoto, H. Onodera Wide Frequency Range Sample and Hold Circuit for On-Chip Oscilloscope オンチップオシロ用サンプルホールド回路の広周波数帯域化 Wide Frequency Range Sample and Hold Circuit for On-Chip Oscilloscope Proc. IEICE General Conference, C-12-34, 103 電子情報通信学会総合大会, C-12-34, 103 Proc. IEICE General Conference, C-12-34, 103 2003/03/19 Japanese Summary of the papers read (national conference and other science council) Disclose to all
山田祐嗣、橋本昌宜、小野寺秀俊 山田祐嗣、橋本昌宜、小野寺秀俊 容量性クロストークを考慮した高精度タイミング解析に関する研究 容量性クロストークを考慮した高精度タイミング解析に関する研究 情報処理学会関西支部支部大会, 113-114 情報処理学会関西支部支部大会, 113-114 , 113-114 2002/11/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
樋口昭彦、小林和淑、小野寺秀俊 樋口昭彦、小林和淑、小野寺秀俊 プロセッサと専用ハードウェアでの消費エネルギー比較 プロセッサと専用ハードウェアでの消費エネルギー比較 情報処理学会関西支部支部大会, 111-112 情報処理学会関西支部支部大会, 111-112 , 111-112 2002/11/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
岡田健一、山岡健人、小野寺秀俊 岡田健一、山岡健人、小野寺秀俊 CMOS論理ゲートにおける統計的遅延モデル化手法 CMOS論理ゲートにおける統計的遅延モデル化手法 情報処理学会関西支部支部大会, 109-110 情報処理学会関西支部支部大会, 109-110 , 109-110 2002/11/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera 土谷亮、橋本昌宜、小野寺秀俊 A. Tsuchiya, M. Hashimoto, H. Onodera Effects of orthogonal layer interconnects on LSI interconnect inductance LSI配線インダクタンスに対する直交配線の影響 Effects of orthogonal layer interconnects on LSI interconnect inductance Proc. IEICE General Conference, A-3-23, 102 電子情報通信学会総合大会, A-3-23, 102 Proc. IEICE General Conference, A-3-23, 102 2002/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
J. Yamaguchi, K. Kobayashi, H. Onodera 山口隼司、小林和淑、小野寺秀俊 J. Yamaguchi, K. Kobayashi, H. Onodera IR-drop measurement of an actual LSI 実チップにおけるIRドロップの測定 IR-drop measurement of an actual LSI Proc. IEICE General Conference, A-3-21, 100 電子情報通信学会総合大会, A-3-21, 100 Proc. IEICE General Conference, A-3-21, 100 2002/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Aramoto, Y. Yuyama, K. Kobayashi, H. Onodera 荒本雅夫、湯山洋一、小林和淑、小野寺秀俊 M. Aramoto, Y. Yuyama, K. Kobayashi, H. Onodera A Design of MPEG-4 Encoder Using SystemC SystemCを用いたMPEG-4エンコーダの設計 A Design of MPEG-4 Encoder Using SystemC Proc. IEICE General Conference, A-3-9, 88 電子情報通信学会総合大会, A-3-9, 88 Proc. IEICE General Conference, A-3-9, 88 2002/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Y. Yamada, M. Hashimoto, H. Onodera 山田祐嗣、橋本昌宜、小野寺秀俊 Y. Yamada, M. Hashimoto, H. Onodera Evaluation of Error Sources and its Effects in Deriving Gate Output Waveform ゲート出力波形導出時の誤差要因とその影響の評価 Evaluation of Error Sources and its Effects in Deriving Gate Output Waveform Proc. IEICE General Conference, A-3-3, 82 電子情報通信学会総合大会, A-3-3, 82 Proc. IEICE General Conference, A-3-3, 82 2002/03/29 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Yamaoka, K. Okada, H. Onodera 山岡健人、岡田健一、小野寺秀俊 K. Yamaoka, K. Okada, H. Onodera Statistical Characterization of Gate Delay with Intra-Chip Variability チップ内ばらつきを考慮したゲート遅延の統計モデル作成手法 Statistical Characterization of Gate Delay with Intra-Chip Variability Proc. IEICE General Conference, A-3-2, 81 電子情報通信学会総合大会, A-3-2, 81 Proc. IEICE General Conference, A-3-2, 81 2002/03/29 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Okada, H. Onodera 岡田健一、小野寺秀俊 K. Okada, H. Onodera A Statistical Timing Analysis with Intra-Chip Manufacturing Variability ゲート遅延におけるチップ内ばらつきを考慮した統計遅延解析手法 A Statistical Timing Analysis with Intra-Chip Manufacturing Variability Proc. IEICE General Conference, A-3-1, 80 電子情報通信学会総合大会, A-3-1, 80 Proc. IEICE General Conference, A-3-1, 80 2002/03/29 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Takahashi, M. Hashimoto, H. Onodera 高橋正郎、橋本昌宜、小野寺秀俊 M. Takahashi, M. Hashimoto, H. Onodera Estimation of Crosstalk-Induced Delay by Waveform Superposition 波形重ね合せによるクロストーク遅延変動量の見積もり手法 Estimation of Crosstalk-Induced Delay by Waveform Superposition Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-9, 63-63 2001年電子情報通信学会基礎・境界ソサイエティ大会, A-3-9, 63-63 Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-9, 63-63 2001/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Hashimoto, M. Takahashi, H. Onodera 橋本昌宜、高橋正郎、小野寺秀俊 M. Hashimoto, M. Takahashi, H. Onodera Crosstalk Noise Optimization by Post-Layout Transistor Sizing ポストレイアウト トランジスタ寸法最適化によるクロストークノイズ削減手法 Crosstalk Noise Optimization by Post-Layout Transistor Sizing Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-8, 62-62 2001年電子情報通信学会基礎・境界ソサイエティ大会, A-3-8, 62-62 Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-8, 62-62 2001/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A. Tsuchiya, M. Hashimoto, H. Onodera 土谷亮、橋本昌宜、小野寺秀俊 A. Tsuchiya, M. Hashimoto, H. Onodera Deterioration of Circuit Design for High-Performance Long Interconnects Based on RC Model 長距離高速配線におけるRCモデルに基づく回路設計の限界 Deterioration of Circuit Design for High-Performance Long Interconnects Based on RC Model Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-6, 60-60 2001年電子情報通信学会基礎・境界ソサイエティ大会, A-3-6, 60-60 Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-6, 60-60 2001/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Okada, H. Onodera 岡田健一、小野寺秀俊 K. Okada, H. Onodera Statistical Modeling of Device Characteristics with Intra-Chip Variability トランジスタ特性におけるチップ内ばらつきのモデル化手法 Statistical Modeling of Device Characteristics with Intra-Chip Variability Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-4, 58-58 2001年電子情報通信学会基礎・境界ソサイエティ大会, A-3-4, 58-58 Proceedings of the 2001 Engineering Sciences Society Conference of IEICE, A-3-4, 58-58 2001/09/18 Japanese Summary of the papers read (national conference and other science council) Disclose to all
R. Nakanishi, K. Kobayashi, H. Onodera 中西龍太、小林和淑、小野寺秀俊 R. Nakanishi, K. Kobayashi, H. Onodera Motion Compensation Using Camera Vectors カメラの動きを用いた動き補償の検討 Motion Compensation Using Camera Vectors Proceedings of IEICE General Conference, D-11-47, 47-47 電子情報通信学会総合大会, D-11-47, 47-47 Proceedings of IEICE General Conference, D-11-47, 47-47 2001/03/27 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Takai, Y. Yuyama, K. Kobayashi, H. Onodera 高井幸輔、湯山洋一、小林和淑、小野寺秀俊 K. Takai, Y. Yuyama, K. Kobayashi, H. Onodera Hardware Design using SystemC: Translation from an RTL SystemC Source to an HDL SystemCを用いたハードウェア設計 -SystemCのRTL記述からHDLへの変換 Hardware Design using SystemC: Translation from an RTL SystemC Source to an HDL Proceedings of IEICE General Conference, A-3-13, 91-91 電子情報通信学会総合大会, A-3-13, 91-91 Proceedings of IEICE General Conference, A-3-13, 91-91 2001/03/26 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Hashimoto, M. Takahashi, H. Onodera 橋本昌宜、高橋正郎、小野寺秀俊 M. Hashimoto, M. Takahashi, H. Onodera An Analytic Crosstalk Noise Model Considering Coupling Location -Application to Practical Circuits- 隣接位置を考慮した解析的クロストークノイズモデル -実回路への適用- An Analytic Crosstalk Noise Model Considering Coupling Location -Application to Practical Circuits- Proceedings of IEICE General Conference, A-3-6, 84-84 電子情報通信学会総合大会, A-3-6, 84-84 Proceedings of IEICE General Conference, A-3-6, 84-84 2001/03/26 Japanese Summary of the papers read (national conference and other science council) Disclose to all
M. Takahashi, M. Hashimoto, H. Onodera 高橋正郎、橋本昌宜、小野寺秀俊 M. Takahashi, M. Hashimoto, H. Onodera An Analytic Crosstalk Noise Model Considering Coupling Location -Derivation and Evaluation- 隣接位置を考慮した解析的クロストークノイズモデル -導出と評価- An Analytic Crosstalk Noise Model Considering Coupling Location -Derivation and Evaluation- Proceedings of IEICE General Conference, A-3-5, 83-83 電子情報通信学会総合大会, A-3-5, 83-83 Proceedings of IEICE General Conference, A-3-5, 83-83 2001/03/26 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K. Fujimori, H. Onodera 藤森一憲、小野寺秀俊 K. Fujimori, H. Onodera Low power design of D-flipflop Dフリップフロップの低消費電力化設計 Low power design of D-flipflop Proceedings of IEICE General Conference, A-3-4, 82-82 電子情報通信学会総合大会, A-3-4, 82-82 Proceedings of IEICE General Conference, A-3-4, 82-82 2001/03/26 Japanese Summary of the papers read (national conference and other science council) Disclose to all
T. Fujita, H. Onodera 藤田智弘、小野寺秀俊 T. Fujita, H. Onodera A Global Optimization Method Using Stochastic Process and Its Application to Parametric Yield Optimization 確率過程モデルによる大域的最適化手法と回路の歩留まり最適化問題への応用 A Global Optimization Method Using Stochastic Process and Its Application to Parametric Yield Optimization Proceedings of IEICE General Conference, A-3-2, 80-80 電子情報通信学会総合大会, A-3-2, 80-80 Proceedings of IEICE General Conference, A-3-2, 80-80 2001/03/26 Japanese Summary of the papers read (national conference and other science council) Disclose to all
T.Yasuda, H.Fujita, H.Onodera 安田岳雄、藤田浩章、小野寺秀俊 T.Yasuda, H.Fujita, H.Onodera Phase adjust PLL with variable delay circuit Phase adjust PLL with variable delay circuit Phase adjust PLL with variable delay circuit Proceedings of IEICE Society Conference, A-1-39, 39-39 電子情報通信学会ソサイエティ大会, A-1-39, 39-39 Proceedings of IEICE Society Conference, A-1-39, 39-39 2000/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
T.Fujita, H.Onodera 藤田智弘、小野寺秀俊 T.Fujita, H.Onodera An Application of Table Base Satistical Cell Delay Model to Intra-Chip Variability テーブルによるセル統計的遅延モデルのチップ内ばらつきへの適用 An Application of Table Base Satistical Cell Delay Model to Intra-Chip Variability Proceedings of IEICE Society Conference, A-3-10, 77-77 電子情報通信学会ソサイエティ大会, A-3-10, 77-77 Proceedings of IEICE Society Conference, A-3-10, 77-77 2000/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Masanori HASHIMOTO, Hidetoshi ONODERA 橋本昌宜、小野寺秀俊 Masanori HASHIMOTO, Hidetoshi ONODERA A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits パスバランス回路における遅延不確かさの統計的解析 A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-9, 76-76 2000/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Masanori Hashimoto, Hidetoshi Onodera 橋本昌宜、小野寺秀俊 Masanori Hashimoto, Hidetoshi Onodera Worst-Case Delay Calculation using Statistical Static Timing Analysis 静的統計遅延解析を用いた最悪遅延時間計算手法 Worst-Case Delay Calculation using Statistical Static Timing Analysis Proc. IEICE General Conference, A-3-13-A-3-13 電子情報通信学会総合大会論文集, A-3-13-A-3-13 Proc. IEICE General Conference, A-3-13-A-3-13 2000/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Takehide Sibayama, Makoto Eguchi, Takuya Iwahashi, Kazutoshi Kobayashi, Hidetoshi Onodera 柴山武英、江口真、岩橋卓也、小林和淑、小野寺秀俊 Takehide Sibayama, Makoto Eguchi, Takuya Iwahashi, Kazutoshi Kobayashi, Hidetoshi Onodera Design of a 16 Parallel Pipeline DSP for Mobile Videophone 携帯TV電話に適した16並列パイプラインDSPの設計 Design of a 16 Parallel Pipeline DSP for Mobile Videophone Proc. IEICE General Conference, C-12-26-C-12-26 電子情報通信学会総合大会論文集, C-12-26-C-12-26 Proc. IEICE General Conference, C-12-26-C-12-26 2000/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Makoto Eguchi, Takehide Sibayama, Takuya Iwahashi, Hidetoshi Onodera 江口真、柴山武英、岩橋卓也、小林和淑、小野寺秀俊 Makoto Eguchi, Takehide Sibayama, Takuya Iwahashi, Hidetoshi Onodera Videophone System with a Vector Pipeline DSP ベクトルDSPを用いた携帯端末におけるテレビ電話システム Videophone System with a Vector Pipeline DSP Proc. IEICE General Conference, C-12-27-C-12-27 電子情報通信学会総合大会論文集, C-12-27-C-12-27 Proc. IEICE General Conference, C-12-27-C-12-27 2000/03/30 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Ryota Nishikawa, Hidetoshi Onodera, Kazutoshi Kobayashi 西川 亮太、小野寺 秀俊 Ryota Nishikawa, Hidetoshi Onodera, Kazutoshi Kobayashi Effective grounded capacitance modeling of coupled interconnects for delay analysis 隣接配線による遅延時間増加量の等価対地容量への縮約の検討 Effective grounded capacitance modeling of coupled interconnects for delay analysis Proc. IEICE Society Conference, A-3-6-A-3-6 電子情報通信学会ソサイエティ大会論文集, A-3-6-A-3-6 Proc. IEICE Society Conference, A-3-6-A-3-6 1999/09/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Kennichi OKADA, Hidetoshi ONODERA 岡田健一、小野寺秀俊 Kennichi OKADA, Hidetoshi ONODERA Modeling Systematic Fluctuation for Statistical Analysis CMOS回路の統計解析における大域ばらつきのモデル化 Modeling Systematic Fluctuation for Statistical Analysis Proc. IEICE Society Conference, A-3-5-A-3-5 電子通信情報学会ソサイエティ大会論文集, A-3-5-A-3-5 Proc. IEICE Society Conference, A-3-5-A-3-5 1999/09/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Masanori Hashimoto, Hidetoshi Onodera 橋本昌宜、小野寺秀俊 Masanori Hashimoto, Hidetoshi Onodera Impact on Power Dissipation of Adding Driving-Strength Variation in Standard Cell Library スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討 Impact on Power Dissipation of Adding Driving-Strength Variation in Standard Cell Library Proc. IEICE Society Conference, A-3-9-A-3-9 電子情報通信学会ソサイエティ大会論文集, A-3-9-A-3-9 Proc. IEICE Society Conference, A-3-9-A-3-9 1999/09/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Tomohiro Fujita, Hidetoshi Onodera 藤田智弘、小野寺秀俊 Tomohiro Fujita, Hidetoshi Onodera Comparison of Delay Worst-Case Model for LSI --- Vector Synthesis Model vs. Transistor Current Model 集積回路遅延ワーストケース解析の比較---ベクトル合成モデル Comparison of Delay Worst-Case Model for LSI --- Vector Synthesis Model vs. Transistor Current Model Society conference of IEICE, A-3-7-A-3-7 電子情報通信学会ソサイエティ大会, A-3-7-A-3-7 Society conference of IEICE, A-3-7-A-3-7 1999/09/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
A.Hirata, T.Hashimoto, H.Onodera, K.Tamaru 平田昭夫、橋本鉄太郎、小野寺秀俊、田丸啓吉 A.Hirata, T.Hashimoto, H.Onodera, K.Tamaru LSI Design with a Standard-cell Library Generated Target Specifications 設計対象毎に生成したスタンダードセルライブラリによるLSI設計 LSI Design with a Standard-cell Library Generated Target Specifications Proceedings of IEICE General Conference, A-3-16, 120-120 電子情報通信学会総合大会, A-3-16, 120-120 Proceedings of IEICE General Conference, A-3-16, 120-120 1999/03/25 Japanese Summary of the papers read (national conference and other science council) Disclose to all
K.Okada, H.Onodera, K.Tamaru 岡田健一、小野寺秀俊、田丸啓吉 K.Okada, H.Onodera, K.Tamaru Extracting Matching Parameters with Small Model Dependency using an Intermediate Model 中間モデルを用いたMOSFETモデルに依存しない比精度パラメータ抽出手法 Extracting Matching Parameters with Small Model Dependency using an Intermediate Model Proceedings of IEICE General Conference, A-3-10, 114-114 電子情報通信学会総合大会, A-3-10, 114-114 Proceedings of IEICE General Conference, A-3-10, 114-114 1999/03/25 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru 橋本昌宜、小野寺秀俊、田丸啓吉 Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru A Power Optimization Method Considering Glitch Reduction by Gate Sizing グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 -レイアウト設計への適用 A Power Optimization Method Considering Glitch Reduction by Gate Sizing 電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-5 電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-5 電子情報通信学会基礎・境界ソサイエティ大会講演論文集, A-3-5 1998/09/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
岡田健一, 小野寺秀俊, 田丸啓吉 岡田健一, 小野寺秀俊, 田丸啓吉 レイアウトを考慮したCMOS回路の比精度解析 レイアウトを考慮したCMOS回路の比精度解析 電子情報通信学会ソサイエティ大会講演論文集, 1997 電子情報通信学会ソサイエティ大会講演論文集, 1997 , 1997 1997/08 Japanese Summary of the papers read (national conference and other science council) Disclose to all
安慶武志、小林和淑、小野寺秀俊、田丸啓吉 安慶武志、小林和淑、小野寺秀俊、田丸啓吉 BPBP型FMPPを用いたプロセッサボードの設計 BPBP型FMPPを用いたプロセッサボードの設計 電子情報通信学会総合大会講演論文集, C-595, 188-188 電子情報通信学会総合大会講演論文集, C-595, 188-188 , C-595, 188-188 1995/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
W. Jungsuwadee、小林和淑、小野寺秀俊、田丸啓吉 W. Jungsuwadee、小林和淑、小野寺秀俊、田丸啓吉 ビット並列ブロック並列型FMPPにおける機能メモリのテスト方法 ビット並列ブロック並列型FMPPにおける機能メモリのテスト方法 電子情報通信学会総合大会講演論文集, C-571, 164-164 電子情報通信学会総合大会講演論文集, C-571, 164-164 , C-571, 164-164 1995/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
小林和淑、小野寺秀俊、田丸啓吉 小林和淑、小野寺秀俊、田丸啓吉 ビット並列ブロック並列型FMPPアーキテクチャをとるプロトタイプLSIチップの概要 ビット並列ブロック並列型FMPPアーキテクチャをとるプロトタイプLSIチップの概要 電子情報通信学会秋季大会講演論文集, C-488, 166-166 電子情報通信学会秋季大会講演論文集, C-488, 166-166 , C-488, 166-166 1994/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
竹村秀城、小林和淑、小野寺秀俊、田丸啓吉 竹村秀城、小林和淑、小野寺秀俊、田丸啓吉 機能メモリ型並列プロセッサ上での離散余弦変換の実現 機能メモリ型並列プロセッサ上での離散余弦変換の実現 電子情報通信学会春季大会講演論文集, C-639, 5-207-5-207 電子情報通信学会春季大会講演論文集, C-639, 5-207-5-207 , C-639, 5-207-5-207 1994/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
小林和淑、小野寺秀俊、田丸啓吉 小林和淑、小野寺秀俊、田丸啓吉 FMPP におけるパストランジスタを用いた並列演算手法 FMPP におけるパストランジスタを用いた並列演算手法 電子情報通信学会秋季大会講演論文集, C-431, 5-141-5-141 電子情報通信学会秋季大会講演論文集, C-431, 5-141-5-141 , C-431, 5-141-5-141 1993/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
小林和淑、小野寺秀俊、田丸啓吉、安浦寛人 小林和淑、小野寺秀俊、田丸啓吉、安浦寛人 ビット並列ブロック並列方式による機能メモリ型並列プロセッサFMPPの設計−レイアウト面積および動作速度評価− ビット並列ブロック並列方式による機能メモリ型並列プロセッサFMPPの設計−レイアウト面積および動作速度評価− 電子情報通信学会春季大会講演論文集, C-594, 5-224-5-224 電子情報通信学会春季大会講演論文集, C-594, 5-224-5-224 , C-594, 5-224-5-224 1993/10/01 Japanese Summary of the papers read (national conference and other science council) Disclose to all
Akira Tsuchiya, Taro Amagai, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera Akira Tsuchiya, Taro Amagai, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera On-Chip Coupled Inductor for Area-Efficient Inductive Peaking On-Chip Coupled Inductor for Area-Efficient Inductive Peaking Thailand-Japan Microwave Thailand-Japan Microwave 2014/11 Refereed English Research paper Disclose to all
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 28-32 , 28-32 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 28-32 2014/03 Refereed English Research paper Disclose to all
Norihiro Kamae, Islam A.K.M Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera Norihiro Kamae, Islam A.K.M Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera Cell-based Physical Design Automation for Analog and Mixed Signal Application Cell-based Physical Design Automation for Analog and Mixed Signal Application International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 13 , 13 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 13 2014/03 Refereed English Research paper Disclose to all
Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay TAU workshop TAU workshop 2013/03 Refereed English Research paper Disclose to all
T. Matsumoto(Kyoto Univ.), K. Kobayashi(KIT), and H. Onodera(Kyoto Univ.) T. Matsumoto(Kyoto Univ.), K. Kobayashi(KIT), and H. Onodera(Kyoto Univ.) Impact of Body-Biasing Technique on RTN-induced CMOS Logic Delay Uncertainty Impact of Body-Biasing Technique on RTN-induced CMOS Logic Delay Uncertainty Proc.of IEEE/ACM Workshop on Variability Modeling and Characterization Proc.of IEEE/ACM Workshop on Variability Modeling and Characterization 2012/11 Refereed English Research paper Disclose to all
Takashi Matsumoto(Kyoto Univ.), Kazutoshi Kobayashi(KIT), Hidetoshi Onodera(Kyoto Univ.) Takashi Matsumoto(Kyoto Univ.), Kazutoshi Kobayashi(KIT), Hidetoshi Onodera(Kyoto Univ.) Impact of RTN and NBTI on Synchrorous Circuit Reliability Impact of RTN and NBTI on Synchrorous Circuit Reliability IEEE/ACM Workshop on Variability Modeling and Characterization IEEE/ACM Workshop on Variability Modeling and Characterization 2011/11 Refereed English Research paper Disclose to all
Hidetoshi Onodera Hidetoshi Onodera Understanding CMOS Variability for More Moore Understanding CMOS Variability for More Moore Design, Automation & Test in Europe, pp. Design, Automation & Test in Europe, pp. 2010/03 Refereed English Lecture materials etc.(seminar, tutorial, course, lecture and others) Disclose to all
Hidetoshi Onodera Hidetoshi Onodera Dependable VLSI Platform Using Robust Fabrics Dependable VLSI Platform Using Robust Fabrics International Workshop on Emerging Circuits and Systems, pp. International Workshop on Emerging Circuits and Systems, pp. 2009/07 Refereed English Research paper Disclose to all

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Title language:
Conference Activities & Talks
Title Title(Japanese) Title(English) Conference Conference(Japanese) Conference(English) Promotor Promotor(Japanese) Promotor(English) Date Language Assortment Disclose
Reconfigurable Architecture for Dependability and Energy Efficiency[Invited] Reconfigurable Architecture for Dependability and Energy Efficiency [Invited] Reconfigurable Architecture for Dependability and Energy Efficiency [Invited] International Workshop on Cross-layer Resiliency International Workshop on Cross-layer Resiliency International Workshop on Cross-layer Resiliency 2019/07/30 English Oral presentation(invited, special) Disclose to all
Minimum Energy Operation of Voltage-Scaled Circuits[Invited] Minimum Energy Operation of Voltage-Scaled Circuits [Invited] Minimum Energy Operation of Voltage-Scaled Circuits [Invited] International Workshop on Cross-layer Resiliency International Workshop on Cross-layer Resiliency International Workshop on Cross-layer Resiliency 2018/08/17 English Oral presentation(invited, special) Disclose to all
Toward minimum energy operation of voltage-scaled circuits[Invited] Toward minimum energy operation of voltage-scaled circuits [Invited] Toward minimum energy operation of voltage-scaled circuits [Invited] IEEE/ACM 10th Workshop on Variability Modeling and Characterization IEEE/ACM 10th Workshop on Variability Modeling and Characterization IEEE/ACM 10th Workshop on Variability Modeling and Characterization 2017/11/16 English Oral presentation(invited, special) Disclose to all
Toward minimum energy operation[Invited] Toward minimum energy operation [Invited] Toward minimum energy operation [Invited] International Workshop on Cross-Layer Resiliency International Workshop on Cross-Layer Resiliency International Workshop on Cross-Layer Resiliency 2017/07/21 English Oral presentation(invited, special) Disclose to all
Circuit Aging - Measurement Techniques[Invited] Circuit Aging - Measurement Techniques [Invited] Circuit Aging - Measurement Techniques [Invited] IEEE International Reliability Physics Symposium, Monday Tutorial IEEE International Reliability Physics Symposium, Monday Tutorial IEEE International Reliability Physics Symposium, Monday Tutorial 2016/04/18 English Oral presentation(invited, special) Disclose to all
IoT時代の設計課題[Invited] IoT時代の設計課題 [Invited] 電子情報通信学会集積回路研究会 電子情報通信学会集積回路研究会 2016/03/04 Japanese Oral presentation(invited, special) Disclose to all
Design Challenges and Solutions in the era of IoT[Invited] Design Challenges and Solutions in the era of IoT [Invited] Design Challenges and Solutions in the era of IoT [Invited] IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2015/10/07 English Oral presentation(keynote) Disclose to all
Dependable VLSI Platform with Variability and Soft-Error Resilience[Invited] Dependable VLSI Platform with Variability and Soft-Error Resilience [Invited] Dependable VLSI Platform with Variability and Soft-Error Resilience [Invited] International Conference on Integrated Circutis, Design, and Verification International Conference on Integrated Circutis, Design, and Verification International Conference on Integrated Circutis, Design, and Verification 2015/08/11 English Oral presentation(invited, special) Disclose to all
Energy-Efficient Computing with Algorithm Embedded Hardware[Invited] Energy-Efficient Computing with Algorithm Embedded Hardware [Invited] Energy-Efficient Computing with Algorithm Embedded Hardware [Invited] International Workshop on Cross-Layer Resiliency International Workshop on Cross-Layer Resiliency International Workshop on Cross-Layer Resiliency 2015/07/20 English Oral presentation(invited, special) Disclose to all
ディペンダブルVLSIプラットフォームへの挑戦[Invited] ディペンダブルVLSIプラットフォームへの挑戦 [Invited] 電子情報通信学会総合全国大会 電子情報通信学会総合全国大会 2009/03/18 Japanese Oral presentation(invited, special) Disclose to all
サブ100nm CMOSデバイスによるアナログ回路設計の課題と展望[Invited] サブ100nm CMOSデバイスによるアナログ回路設計の課題と展望 [Invited] 電子情報通信学会集積回路研究会 電子情報通信学会集積回路研究会 2008/10/23 Japanese Symposium workshop panel(nominated) Disclose to all
ばらつき考慮設計に向けて[Invited] ばらつき考慮設計に向けて [Invited] 電子情報通信学会集積回路研究会 電子情報通信学会集積回路研究会 2008/10/23 Japanese Oral presentation(invited, special) Disclose to all
ばらつき考慮DFMの課題と期待[Invited] ばらつき考慮DFMの課題と期待 [Invited] 電子情報通信学会総合全国大会 電子情報通信学会総合全国大会 2008/03/18 Japanese Oral presentation(invited, special) Disclose to all
Toward Variability-Aware Design[Invited] Toward Variability-Aware Design [Invited] Toward Variability-Aware Design [Invited] VLSI Technology Symposium 20081017 VLSI Technology Symposium 2007/06/12 English Oral presentation(invited, special) Disclose to all
ばらつきを克服する設計技術[Invited] ばらつきを克服する設計技術 [Invited] 回路とシステム軽井沢ワークショップ 回路とシステム軽井沢ワークショップ 2006/04/24 Japanese Oral presentation(invited, special) Disclose to all
ばらつきを克服する設計技術[Invited] ばらつきを克服する設計技術 [Invited] 半導体技術ロードマップ専門委員会2005年度ワークショップ(第7回) 半導体技術ロードマップ専門委員会2005年度ワークショップ(第7回) 2006/03/09 Japanese Oral presentation(invited, special) Disclose to all
微細化限界を回路テクノロジで突破する[Invited] 微細化限界を回路テクノロジで突破する [Invited] システムLSIワークショップ システムLSIワークショップ 2005/11/28 Japanese Oral presentation(invited, special) Disclose to all
設計容易化技術[Invited] 設計容易化技術 [Invited] 日本学術振興会シリコン超集積化システム第165委員会第38回研究会 日本学術振興会シリコン超集積化システム第165委員会第38回研究会 2005/07/29 Japanese Symposium workshop panel(nominated) Disclose to all
ばらつきの要因とモデル化[Invited] ばらつきの要因とモデル化 [Invited] 日本学術振興会シリコン超集積化システム第165委員会第38回研究会 日本学術振興会シリコン超集積化システム第165委員会第38回研究会 2005/07/29 Japanese Oral presentation(invited, special) Disclose to all
Variability and Soft-error Resilience in Dependable VLSI Platform[Invited] Variability and Soft-error Resilience in Dependable VLSI Platform [Invited] 2014 IEEE 23rd Asian Test Symposium 2014 IEEE 23rd Asian Test Symposium 2014/11/17 English Oral presentation(invited, special) Disclose to all
Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability[Invited] Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability [Invited] 2014 IEEE Custom Integrated Circuits Conference 2014 IEEE Custom Integrated Circuits Conference 2014/09/17 English Oral presentation(invited, special) Disclose to all
Characterization and compensation of performance variability using on-chip monitors[Invited] Characterization and compensation of performance variability using on-chip monitors [Invited] 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2014/04/28 English Oral presentation(invited, special) Disclose to all
Variability in Timing Where is Statitical Timing?[Invited] Variability in Timing Where is Statitical Timing? [Invited] TAU TAU 2013/03/28 English Symposium workshop panel(nominated) Disclose to all
Dependable VLSI Platform using Robust Fabrics[Invited] Dependable VLSI Platform using Robust Fabrics [Invited] 18th Asia and South Pacific Design Automation Conference (ASP-DAC) 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) 2013 2013/01/23 English Oral presentation(invited, special) Disclose to all
The Empire Strikes Back or Attack of the Clones? The Once and Future CAD[Invited] The Empire Strikes Back or Attack of the Clones? The Once and Future CAD [Invited] ICCAD ICCAD 2012/11/05 English Symposium workshop panel(nominated) Disclose to all
Japan Science and Technology Agency (JST) program on Dependable VLSI Platform project[Invited] Japan Science and Technology Agency (JST) program on Dependable VLSI Platform project [Invited] Design, Automation & Test in Europe Design, Automation & Test in Europe 2012/03/16 English Oral presentation(invited, special) Disclose to all
Dependable VLSI Program in Japan -- Program overview and the curent status of dependable VLSI platform project --[Invited] Dependable VLSI Program in Japan -- Program overview and the curent status of dependable VLSI platform project -- [Invited] Asian Test Symposium Asian Test Symposium 2011/11/22 English Oral presentation(invited, special) Disclose to all
Understanding CMOS Variability for More Moore[Invited] Understanding CMOS Variability for More Moore [Invited] Design, Automation & Test in Europe Design, Automation & Test in Europe 2010/03/11 English Oral presentation(invited, special) Disclose to all
Characterization of WID Delay Variability Using RO-array Test Structures[Invited] Characterization of WID Delay Variability Using RO-array Test Structures [Invited] 2009 8th IEEE International Conference on ASIC 2009 8th IEEE International Conference on ASIC 2009/10/21 English Oral presentation(invited, special) Disclose to all
Dependable VLSI Platform Using Robust Fabric[Invited] Dependable VLSI Platform Using Robust Fabric [Invited] International Workshop on Emerging Circuits and Systems International Workshop on Emerging Circuits and Systems 2009/07/06 English Oral presentation(invited, special) Disclose to all
Variability Modeling and Impact on Design[Invited] Variability Modeling and Impact on Design [Invited] 2008 International Electron Devices Meeting 2008 International Electron Devices Meeting 2008/12/17 English Oral presentation(invited, special) Disclose to all
Toward Variability-aware Design of System-on-Chip[Invited] Toward Variability-aware Design of System-on-Chip [Invited] 1st International Symposium on Photonics and Electronics Science and Engineering 1st International Symposium on Photonics and Electronics Science and Engineering 2008/03/04 English Oral presentation(invited, special) Disclose to all
Recent Progress in SoC Design Technology[Invited] Recent Progress in SoC Design Technology [Invited] COE International Symposium on Advanced Photonic and Electronic Devices for Information and Electric Power Networks COE International Symposium on Advanced Photonic and Electronic Devices for Information and Electric Power Networks 2006/10/23 English Oral presentation(invited, special) Disclose to all
Recent Research on SoC Design Technology at Kyoto University[Invited] Recent Research on SoC Design Technology at Kyoto University [Invited] COE Workshop for SoC Design Technology and Automation COE Workshop for SoC Design Technology and Automation 2005/09/15 Japanese Oral presentation(invited, special) Disclose to all
Design Accommodating Variability[Invited] Design Accommodating Variability [Invited] the 6th International Workshop on Future Information Processing Technologies the 6th International Workshop on Future Information Processing Technologies 2005/08/30 English Symposium workshop panel(nominated) Disclose to all

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Title language:
Books etc
Author Author(Japanese) Author(English) Title Title(Japanese) Title(English) Publisher Publisher(Japanese) Publisher(English) Publication date Language Type Disclose
Hidetoshi Onodera Hidetoshi Onodera Hidetoshi Onodera VLSI Design and Test for Systems Dependability, Shojiro Asai Ed. VLSI Design and Test for Systems Dependability, Shojiro Asai Ed. VLSI Design and Test for Systems Dependability, Shojiro Asai Ed. Springer Springer Springer 2018/08 English Contributor Disclose to all
小野寺 秀俊 小野寺 秀俊 情報処理学会論文誌「システムLSI設計とその技術」 情報処理学会論文誌「システムLSI設計とその技術」 情報処理学会論文誌 情報処理学会論文誌 2007 Japanese Disclose to all
小野寺秀俊 小野寺秀俊 LSI配線の解析と合成 ---ディープサブミクロン世代のLSI設計技術--- LSI配線の解析と合成 ---ディープサブミクロン世代のLSI設計技術--- 培風館 培風館 2003 Japanese Disclose to all
Hidetoshi Onodera Hidetoshi Onodera IEICE Transactions on Fundamentals, Special Section on VLSI Design and CAD Algorithms IEICE Transactions on Fundamentals, Special Section on VLSI Design and CAD Algorithms IEICE Transactions on Fundamentals,E89-A,12 IEICE Transactions on Fundamentals,E89-A,12 2006 English Disclose to all
Hidetoshi Onodera Hidetoshi Onodera IEICE Transaction on Fundamentals IEICE Transaction on Fundamentals SepcialSection on CAD,Vol.E84-A,No. 11 SepcialSection on CAD,Vol.E84-A,No. 11 2001 English Disclose to all
Title language:
Patents
Inventor(s) Inventor(s) (Japanese) Inventor(s) (English) Title Title(Japanese) Title(English) Stage Patent number Date Disclose
Yusuke Ohtomo, Hiroaki Katsurai, Hidetoshi Onodera, Akira Tsuchiya Yusuke Ohtomo, Hiroaki Katsurai, Hidetoshi Onodera, Akira Tsuchiya Indoctor Indoctor Indoctor 特許登録 9082543 2015/07/14 Disclose to all
大友祐輔、桂井宏明、小野寺秀俊、土谷亮 大友祐輔、桂井宏明、小野寺秀俊、土谷亮 インダクタ インダクタ 特許登録 5463580 2014/01/31 Disclose to all
中村誠、小野寺秀俊、土谷亮 中村誠、小野寺秀俊、土谷亮 トランスインピーダンスアンプ トランスインピーダンスアンプ 特許登録 5137141 2013/11/22 Disclose to all
中村誠、岸根桂路、小野寺秀俊、土谷亮 中村誠、岸根桂路、小野寺秀俊、土谷亮 トランスインピーダンスアンプ トランスインピーダンスアンプ 特許登録 5147061 2012/12/07 Disclose to all
小野寺秀俊、イスラム・エイケイエム・マーフズル 小野寺秀俊、イスラム・エイケイエム・マーフズル 再構成可能な遅延回路、並びにその遅延回路を用いた遅延モニタ回路、ばらつき補正回路、ばらつき測定方法及びばらつき補正方法 再構成可能な遅延回路、並びにその遅延回路を用いた遅延モニタ回路、ばらつき補正回路、ばらつき測定方法及びばらつき補正方法 特許公開 WO2015/025682 2015/02/02 Disclose to all
中野慎介、野河正史、雨貝太郎、土谷亮、小野寺秀俊 中野慎介、野河正史、雨貝太郎、土谷亮、小野寺秀俊 ソレノイドインダクタ ソレノイドインダクタ 特許出願 特願2014-086116 2014/04/18 Disclose to all
中野慎介、野河正史、雨貝太郎、土谷亮、小野寺秀俊 中野慎介、野河正史、雨貝太郎、土谷亮、小野寺秀俊 直交型ソレノイドインダクタ 直交型ソレノイドインダクタ 特許出願 特願2014-086117 2014/04/18 Disclose to all
小野寺秀俊、イスラム・エイケイエム・マーフズル 小野寺秀俊、イスラム・エイケイエム・マーフズル 集積回路における信号伝搬時間を測定する遅延モニタ回路及び遅延モニタ回路に用いる遅延回路 集積回路における信号伝搬時間を測定する遅延モニタ回路及び遅延モニタ回路に用いる遅延回路 特許出願 特願2013-169965 2013/08/19 Disclose to all
中村誠、小野寺秀俊、土谷亮 中村誠、小野寺秀俊、土谷亮 ソレノイドインダクタ ソレノイドインダクタ 特許出願 特願2012-158359 2012/07/17 Disclose to all
中村誠、小野寺秀俊、土谷亮 中村誠、小野寺秀俊、土谷亮 可変インダクタおよびトランスインピーダンスアンプ 可変インダクタおよびトランスインピーダンスアンプ 特許出願 特願2012-122702 2012/05/30 Disclose to all
中村誠、小野寺秀俊、土谷亮、宮脇成和 中村誠、小野寺秀俊、土谷亮、宮脇成和 トランスインピーダンスアンプ トランスインピーダンスアンプ 特許出願 特願2012-118264 2012/05/24 Disclose to all
中村誠、小野寺秀俊、土谷亮 中村誠、小野寺秀俊、土谷亮 トランスインピーダンスアンプ トランスインピーダンスアンプ 特許出願 特願2011-128884 2011/06/09 Disclose to all
ONODERA Hidetoshi, ZHANG Xuliang, ONO Nobuto ONODERA Hidetoshi, ZHANG Xuliang, ONO Nobuto CMOS Model Generating Apparatus and Method, Program of the Method and Recording Medium CMOS Model Generating Apparatus and Method, Program of the Method and Recording Medium CMOS Model Generating Apparatus and Method, Program of the Method and Recording Medium 特許出願 7,937,252 2011/05/03 Disclose to all
大友祐輔、桂井宏明、小野寺秀俊、土谷亮 大友祐輔、桂井宏明、小野寺秀俊、土谷亮 インダクタ インダクタ 特許出願 特願2010-209549 2010/09/17 Disclose to all
小林和淑、古田潤、小野寺秀俊 小林和淑、古田潤、小野寺秀俊 フリップフロップ回路 フリップフロップ回路 特許出願 特願2010-134066 2010/06/11 Disclose to all
炭田昌哉、小野寺秀俊 炭田昌哉、小野寺秀俊 半導体集積回路の設計方法及び半導体集積回路設計装置 半導体集積回路の設計方法及び半導体集積回路設計装置 特許出願 特願2007-095293 2007/03/30 Disclose to all
高務祐哲、小林和淑、小野寺秀俊、石橋孝一郎、笹川幸宏、平田雅規 高務祐哲、小林和淑、小野寺秀俊、石橋孝一郎、笹川幸宏、平田雅規 半導体デバイス及び半導体デバイスの配線方法 半導体デバイス及び半導体デバイスの配線方法 特許出願 特願2006-029620 2006/02/07 Disclose to all
小野寺秀俊、張 徐亮、小野 信任 小野寺秀俊、張 徐亮、小野 信任 CMOSモデル作成装置、垓方法、垓方法のプログラム及び記録媒体 CMOSモデル作成装置、垓方法、垓方法のプログラム及び記録媒体 特許出願 特願2005-308700 2005/10/27 Disclose to all

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Title language:
Awards
Title(Japanese) Title(English) Organization name(Japanese) Organization name(English) Date
丹羽記念賞 Niwa Memorial Award 丹羽記念会 1984
Recognition of Service Award, for Technical Program Vice Chair ICCAD 02 ACM 2003
Recognition of Service Award, for Technical Program Chair ICCAD 03 ACM 2004
論文賞 Best Paper Award ASP-DAC 2004 ASP-DAC 2004 2004
貢献賞 Recognition of Service Award, for General Chair ICCAD 04 ACM 2005
貢献賞 Special Service Award, for outstanding service on the ICCAD executive committee 1999-2005 ICCAD 2005
貢献賞 Recognition of Service Award, for Program Chair ASPDAC'06 ACM 2006
貢献賞 Recognition of Service Award, for General Chair ASPDAC'07 ACM 2007
フェロー称号 Fellow 電子情報通信学会 The Institute of Electronics, Information and Communication Engineers 2007/09/11
功労賞 Outstanding Service Award 電子情報通信学会基礎境界ソサイエティ IEICE Fundamentals Society 2007
論文賞 Best Paper Award 電子情報通信学会 The Institute of Electronics, Information and Communication Engineers 2009/05/23
優秀論文賞 Best Paper Award 情報処理学会SLDM研究会 IPSJ SIG-SLDM 2009/05
ASICON貢献賞 The ASICON Contribution Award ASICON ASICON 2013
ASPDACリーダーシップアワード ASP-DAC Leadership Award ASP-DAC ASP-DAC 2015
貢献賞 Distinguished Service Award SIGDA/CEDA/ICCAD/DAC/DATE SIGDA/CEDA/ICCAD/DAC/DATE 2015
優秀リコンフィギャラブルシステム論文賞 Best Reconfigurable System Paper Award 情報処理学会RECOND研究会 IPSJ SIG-RECONF 2015/06/19
論文賞 Best Paper Award International System-On-Chip Conference 2016/09/07
論文賞 Best Paper Award International Conference on Microelectronic Test Structures (ICMTS) 2017/03/30
フェロー称号 Fellow IEEE 2018/01/01
論文賞 Best Paper Award 電子情報通信学会 The Institure of Electronic, Information and Communication Engineers 2018/06/01

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External funds: competitive funds and Grants-in-Aid for Scientific Research (Kakenhi)
Type Position Title(Japanese) Title(English) Period
基盤研究(C) Representative 超微細構造集積回路の詳細設計最適化手法 1998-1998
基盤研究(B)(2) Representative 低ビットレート・マルチメディア伝送を行う機能素子LSIの開発 Development of a Functional LSI Achieving Low-rate Multimedia Data Transmission 1998/04/01-2001/03/31
基盤研究(B)(2) Representative 大規模集積回路の総計的特性解析・最適化手法の開発 Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits 1999/04/01-2002/03/31
特定領域研究(2) Representative 動き補償を利用した動画像の実時間背景・対象物分離アル ゴリズムとハードウェアの開発 2001/04/01-2003/03/31
基盤研究(B)(2) Representative 集積回路における高速信号伝送技術の研究 Research of a High-speed Signal Transmission Scheme for Integrated Circuits 2002/04/01-2005/03/31
基盤研究(B) Representative ばらつきや欠陥を克服する集積回路ハードウェア設計技術 Variation and Defect Aware Design of Integrated Circuits 2007/04/01-2010/03/31
基盤研究(B) Representative 低電圧安定動作を実現する集積回路ハードウェア設計技術 Integrated Circuit Design for Robust Operation under Low Supply Voltage 2010/04/01-2013/03/31
基盤研究(B) Representative 自律的特性補償により閾値付近の低電圧まで安定動作する集積回路設計技術 2013/04/01-2016/03/31
基盤研究(B) Representative 自律的特性補償により閾値付近の低電圧まで安定動作する集積回路設計技術 (平成27年度分) 2015/04/01-2016/03/31
基盤研究(B) Representative 自律的特性補償により閾値付近の低電圧まで安定動作する集積回路設計技術 (平成28年度分) 2016/04/01-2017/03/31
基盤研究(A) Representative 自律的に最小エネルギー動作を実現する集積回路設計技術 (平成28年度分) 2016/04/01-2017/03/31
基盤研究(A) Representative 自律的に最小エネルギー動作を実現する集積回路設計技術 (平成29年度分) 2017/04/01-2018/03/31
基盤研究(A) Representative 自律的に最小エネルギー動作を実現する集積回路設計技術 (平成30年度分) 2018/04/01-2019/03/31
基盤研究(A) Representative 自律的に最小エネルギー動作を実現する集積回路設計技術 (平成30年度分) 2018/04/01-2019/03/31

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External funds: other than those above
System Main person Title(Japanese) Title(English) Period
JST 小野寺秀俊 超微細LSIにおけるオンチップ高速信号伝送技術の開発 2004/04/01-2005/03/31
JST 小野寺秀俊 クロック生成用PLLの製造プロセスに依存しない設計技術開発 2006/09/08-2007/02/28
JST CREST 小野寺秀俊 ロバストファブリックを用いたディペンダブルVLSIプラットフォーム Dependable VLSI Platform using Robust Fabrics 2007/10/01-2014/03/31
JST CREST 橋本昌宜 ビアスイッチの実現によるアルゴリズム・処理機構融合型 コンピューティングの創出 Energy-Efficient Computing with Algorithm Embedded Hardware Enabled by Via-Switch 2014/10/01-2020/03/31
Teaching subject(s)
Name(Japanese) Name(English) Term Department Period
Advanced Study in CCE II 通年 情報学研究科 2011/04-2012/03
Advanced Study in CCE I 通年 情報学研究科 2011/04-2012/03
論理回路 前期 工学部 2011/04-2012/03
ディジタル回路 前期 工学部 2011/04-2012/03
特別研究 通年集中 工学部 2011/04-2012/03
通信情報システム特別研究1 通年 情報学研究科 2011/04-2012/03
通信情報システム特別研究2 通年 情報学研究科 2011/04-2012/03
集積回路工学特論 前期 情報学研究科 2011/04-2012/03
通信情報システム特別セミナー 通年 情報学研究科 2011/04-2012/03
集積システム工学特別セミナー 通年 情報学研究科 2011/04-2012/03
ディジタル回路 Digital Circuits 前期 工学部 2012/04-2013/03
論理回路 Logic Circuits 前期 工学部 2012/04-2013/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2012/04-2013/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2012/04-2013/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2012/04-2013/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2012/04-2013/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2012/04-2013/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2012/04-2013/03
論理回路 Logic Circuits 前期 工学部 2013/04-2014/03
ディジタル回路 Digital Circuits 前期 工学部 2013/04-2014/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2013/04-2014/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2013/04-2014/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2013/04-2014/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2013/04-2014/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2013/04-2014/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2013/04-2014/03
論理回路 Logic Circuits 前期 工学部 2014/04-2015/03
ディジタル回路 Digital Circuits 前期 工学部 2014/04-2015/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2014/04-2015/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04-2015/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04-2015/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2014/04-2015/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2014/04-2015/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2014/04-2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2014/04-2015/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2014/04-2015/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04-2016/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04-2016/03
ディジタル回路 Digital Circuits 前期 工学部 2015/04-2016/03
論理回路 Logic Circuits 前期 工学部 2015/04-2016/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2015/04-2016/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2015/04-2016/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2015/04-2016/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2015/04-2016/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2015/04-2016/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2015/04-2016/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04-2017/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04-2017/03
ディジタル回路 Digital Circuits 前期 工学部 2016/04-2017/03
論理回路 Logic Circuits 前期 工学部 2016/04-2017/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2016/04-2017/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2016/04-2017/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2016/04-2017/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2016/04-2017/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2016/04-2017/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2016/04-2017/03
Advanced Study in CCE I Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04-2018/03
Advanced Study in CCE II Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04-2018/03
ディジタル回路 Digital Circuits 前期 工学部 2017/04-2018/03
論理回路 Logic Circuits 前期 工学部 2017/04-2018/03
通信情報システム特別セミナー Seminar on Communications and Computer Engineering, Advanced 通年 情報学研究科 2017/04-2018/03
通信情報システム特別研究2 Advanced Study in Communications and Computer Engineering II 通年 情報学研究科 2017/04-2018/03
通信情報システム特別研究1 Advanced Study in Communications and Computer Engineering I 通年 情報学研究科 2017/04-2018/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2017/04-2018/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2017/04-2018/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2017/04-2018/03
ディジタル回路 Digital Circuits 前期 工学部 2018/04-2019/03
論理回路 Logic Circuits 前期 工学部 2018/04-2019/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2018/04-2019/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 工学研究科 2018/04-2019/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2018/04-2019/03
ディジタル回路 Digital Circuits 前期 工学部 2019/04-2020/03
論理回路 Logic Circuits 前期 工学部 2019/04-2020/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2019/04-2020/03
集積回路工学特論 Integrated Circuits Engineering, Adv. 前期 情報学研究科 2019/04-2020/03

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School management (title, position)
Title Period
発明評価委員会(ソフトウェア・コンテンツ分野拠点) 委員 2009/04/01-2010/03/31
発明評価委員会(メディカル・バイオ分野拠点) 委員 2010/04/01-2011/03/31
京都大学公開講座等企画委員会 委員 2011/04/01-2013/03/31
オープンキャンパス委員会 委員 2012/04/01-2013/03/31
Faculty management (title, position)
Title Period
企画委員会委員 2011/04/01-2012/03/31
評価・広報委員会委員 2012/04/01-2014/03/31
専攻長会議 2014/04/01-2015/03/31
制規委員会委員 2014/04/01-2015/03/31
情報セキュリティ委員会委員 2014/04/01-2015/03/31
教務委員会委員 2016/04/01-2017/03/31
教務委員会委員長 2017/04/01-2018/03/31
連携推進WG委員 2018/04/01-2019/03/31
工学部教育制度委員会委員 2018/04/01-2020/03/31
連携推進WG委員 2019/04/01-2020/03/31
Other activities (awards)
Award name Organization name Date
琵琶湖ワークショップ優秀ポスター賞,11 IEEE SSCS Japan Chater 1998
Other activities (public organizations)
Committee(Japanese) Committee(English) Title Organization name Period
科学研究費委員会 専門委員 日本学術振興会 2000-2000
科学研究費委員会 専門委員 日本学術振興会 2001-2001
科学研究費委員会 専門委員 日本学術振興会 2002-2002
科学研究費委員会 専門委員 日本学術振興会 2008-2009
科学研究費委員会 専門委員 日本学術振興会 2009-2010
科学研究費委員会 専門委員 日本学術振興会 2010-2011
科学研究費委員会 専門委員 日本学術振興会 2011-2012
科学研究費委員会 専門委員 日本学術振興会 2012-2013
科学研究費委員会 専門委員 日本学術振興会 2013-2014
科学研究費委員会 専門委員 日本学術振興会 2014-2015
日本学術会議 連携会員 日本学術会議 2011-2017
学校協議会 北野高等学校学校協議会委員 大阪府教育委員会 2015-
日本学術会議 連携会員 日本学術会議 2017/10/02-2023/09/30
科学研究費委員会 専門委員 日本学術振興会 2015-2016
科学研究費委員会 専門委員 日本学術振興会 2017-2018
科学研究費委員会 専門委員 日本学術振興会 2018-2019

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