石原 亨

最終更新日時: 2018/06/13 16:10:03

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氏名(漢字/フリガナ/アルファベット表記)
石原 亨/イシハラ トオル/Tohru Ishihara
所属部署・職名(部局/所属/講座等/職名)
情報学研究科/通信情報システム専攻集積システム工学講座/准教授
学部兼担
部局 所属 講座等 職名
工学部 工学部 電気電子工学科
所属学会(国内)
学会名(日本語) 学会名(英語)
電子情報通信学会 The Institute of Electronics, Information and Communication Engineers
情報処理学会 The Information Processing Society of Japan
所属学会(海外)
学会名(英語) 国名
Institute of Electrical and Electronic Engineers 米国
Association for Computing Machinery 米国
取得学位
学位名(日本語) 学位名(英語) 大学(日本語) 大学(英語) 取得区分
修士(工学) 九州大学
博士(工学) 九州大学
出身大学院・研究科等
大学名(日本語) 大学名(英語) 研究科名(日本語) 研究科名(英語) 専攻名(日本語) 専攻名(英語) 修了区分
九州大学 大学院システム情報科学研究科情報工学専攻博士課程 修了
九州大学 大学院システム情報科学研究科情報工学専攻修士課程 修了
九州大学 大学院総合理工学研究科情報システム学専攻修士課程
出身学校・専攻等
大学名(日本語) 大学名(英語) 学部名(日本語) 学部名(英語) 学科名(日本語) 学科名(英語) 卒業区分
九州大学 工学部情報工学科 卒業
職歴
期間 組織名(日本語) 組織名(英語) 職名(日本語) 職名(英語)
2000/04/01〜2003/04/15 東京大学大規模集積システム設計教育研究センター VLSI Design and Education Center, the University of Tokyo 助手 Research Associate
2003/04/16〜2005/07/31 米国富士通研究所 Fujitsu Laboratories of America, Inc. 研究員 Member of Research Staff
2005/08/01〜2011/03/31 九州大学システムLSI研究センター System LSI Research Center, Kyushu University 准教授 Associate Professor
1997/04/01〜2000/03/31 日本学術振興会 Japan Society for the Promotion of Science 特別研究員 Research Fellowships for Young Scientists
プロフィール
(日本語)
2000年九州大学大学院システム情報科学研究科 博士課程修了。工学博士。東京大学助手、Fujitsu Laboratories of America研究員、九州大学准教授を経て、2011年より京都大学大学院情報学 研究科(通信情報システム専攻)准教授。専門は計算機工学、とりわけ、大規模集積回路の設計技術と組込みシステムの制御技術。情報処理学会、電子情報通信学会、IEEE、ACM各会員。
(英語)
Tohru Ishihara received the D.E. degree in computer science from Kyushu University in 2000. For the next three years, he was a Research Associate in the University of Tokyo. From 2003 to 2005, he was a Research Staff in Fujitsu Laboratories of America. From 2005 to 2011, he was an Associate Professor of Kyushu University. In 2011, he joined Kyoto University as an Associate Professor, where he is currently with the Department of Communications and Computer Engineering. His research interests include design methodologies and control technologies for embedded systems. Dr. Ishihara is a member of the IPSJ, IEICE, IEEE and ACM.
個人ホームページ
URL
http://www.vlsi.kuee.kyoto-u.ac.jp/~ishihara/
研究テーマ
(日本語)
エネルギーの生産と消費のメカニズムを情報技術の立場から幅広く研究し、エネルギーを効率良く生産し利用する技術の確立を目指しています。この目標のために具体的には、1)エネルギー見える化、2)エネルギー最適化、3)IT機器の省エネルギー化、に関する研究を行っています。
研究概要
(日本語)
エネルギー見える化:IT機器の電力消費モデル(状態や設定に応じた電力消費を算出する計算式)を作ることによって、IT機器をどのように使用すればエネルギー消費をどれだけ減らせるかを“見える化”します。最初のステップとしては、電子機器に搭載されているマイクロプロセッサの消費電力を“見える化”することによって、マイクロプロセッサを省エネルギー化する研究に取り組んでいます。 エネルギー最適化:発電装置や蓄電装置およびIT機器の状態をリアルタイムに観測し制御することによって、エネルギーの生成から消費までの効率を最大化する研究に取り組んでいます。 IT機器の省エネルギー化: ピーク性能が高く平均消費電力の小さいメリハリの効いたスケーラブルプロセッサを開発しています。このスケーラブルプロセッサの消費エネルギーを、モデルを用いて“見える化”し、エネルギー管理技術によって最適に制御する研究も行っています。
論文
著者 著者(日本語) 著者(英語) タイトル タイトル(日本語) タイトル(英語) 書誌情報等 書誌情報等(日本語) 書誌情報等(英語) 出版年月 査読の有無 記述言語 掲載種別 公開
塩見準, 保木本修, 石原 亨, 小野寺秀俊 塩見準, 保木本修, 石原 亨, 小野寺秀俊 Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera Minimum Energy Point Tracking with All-Digital On-Chip Sensors Minimum Energy Point Tracking with All-Digital On-Chip Sensors Minimum Energy Point Tracking with All-Digital On-Chip Sensors ASP Journal of Low Power Electronics,14,2 ASP Journal of Low Power Electronics,14,2 ASP Journal of Low Power Electronics,14,2 2018/06 英語 研究論文(学術雑誌) 公開
石原 亨, 新家昭彦, 井上弘士, 野崎謙悟, 納富雅也 石原 亨, 新家昭彦, 井上弘士, 野崎謙悟, 納富雅也 Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi An Integrated Nanophotonic Parallel Adder An Integrated Nanophotonic Parallel Adder An Integrated Nanophotonic Parallel Adder ACM Journal on Emerging Technologies in Computing (JETC) ACM Journal on Emerging Technologies in Computing (JETC) ACM Journal on Emerging Technologies in Computing (JETC) 2018/06 英語 研究論文(学術雑誌) 公開
今井悠貴, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 今井悠貴, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters An Optical Parallel Multiplier Using Nanophotonic Analog Adders and Optoelectronic Analog-to-Digital Converters Proc. of OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018),JW2A.50 Proc. of OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018),JW2A.50 OSA Technical Digest of Conference on Lasers and Electro-Optics (CLEO 2018),JW2A.50 2018/05 英語 研究論文(国際会議プロシーディングス) 公開
保木本修, 塩見準, 石原 亨, 小野寺秀俊 保木本修, 塩見準, 石原 亨, 小野寺秀俊 Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors Proc. of Annual IEEE International Conference on Microelectronic Test Structures,128-133 Proc. of Annual IEEE International Conference on Microelectronic Test Structures,128-133 Proc. of Annual IEEE International Conference on Microelectronic Test Structures,128-133 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
岸本真, 石原 亨, 小野寺秀俊 岸本真, 石原 亨, 小野寺秀俊 Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Japanese Journal of Applied Physics,57,4S,04FF09-1-04FF09-6 Japanese Journal of Applied Physics,57,4S,04FF09-1-04FF09-6 Japanese Journal of Applied Physics,57,4S,04FF09-1-04FF09-6 2018/03 英語 研究論文(学術雑誌) 公開
岸本真, 石原 亨, 小野寺秀俊 岸本真, 石原 亨, 小野寺秀俊 Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation Proc. of Annual IEEE International Conference on Microelectronic Test Structures,111-116 Proc. of Annual IEEE International Conference on Microelectronic Test Structures,111-116 Proc. of Annual IEEE International Conference on Microelectronic Test Structures,111-116 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
今井悠貴, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 今井悠貴, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 Yuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,100-105 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,100-105 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,100-105 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
江川巧, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 江川巧, 石原 亨, 小野寺秀俊, 新家昭彦, 北 翔太, 野崎謙悟, 高田健太, 納富雅也 Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,320-325 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,320-325 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,320-325 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
長岡悠太, 石原 亨, 小野寺秀俊 長岡悠太, 石原 亨, 小野寺秀俊 Yuta Nagaoka, Tohru Ishihara, Hidetoshi Onodera Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,290-295 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,290-295 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,290-295 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
徐 宏傑, 塩見準, 石原 亨, 小野寺秀俊 徐 宏傑, 塩見準, 石原 亨, 小野寺秀俊 Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,56-61 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,56-61 Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies,56-61 2018/03 英語 研究論文(国際会議プロシーディングス) 公開
塩見準, 石原 亨, 小野寺秀俊 塩見準, 石原 亨, 小野寺秀俊 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation IEICE Transactions on Fundamentals,E100-A,12,2764-2775 IEICE Transactions on Fundamentals,E100-A,12,2764-2775 IEICE Transactions on Fundamentals,E100-A,12,2764-2775 2017/12 英語 研究論文(学術雑誌) 公開
保木本修, 石原 亨, 小野寺秀俊 保木本修, 石原 亨, 小野寺秀俊 Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing IEICE Transactions on Fundamentals,E100-A,12,2776-2784 IEICE Transactions on Fundamentals,E100-A,12,2776-2784 IEICE Transactions on Fundamentals,E100-A,12,2776-2784 2017/12 公開
塩見準, 石原 亨, 小野寺秀俊 塩見準, 石原 亨, 小野寺秀俊 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Elsevier: Integration, the VLSI Journal Elsevier: Integration, the VLSI Journal Elsevier: Integration, the VLSI Journal 2017/07 英語 研究論文(学術雑誌) 公開
鎌苅竜也, 塩見準, 石原 亨, 小野寺秀俊 鎌苅竜也, 塩見準, 石原 亨, 小野寺秀俊 Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Analytical Stability Modeling for CMOS Latches in Low Voltage Operation IEICE Transactions on Fundamentals,E99-A,12,2463-2472 IEICE Transactions on Fundamentals,E99-A,12,2463-2472 IEICE Transactions on Fundamentals,E99-A,12,2463-2472 2016/12 英語 研究論文(学術雑誌) 公開
イスラム マーフズ, 塩見準, 石原 亨, 小野寺秀俊 イスラム マーフズ, 塩見準, 石原 亨, 小野寺秀俊 A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring IEEE Journal of Solid-State Circuits,50,11,2475-2490 IEEE Journal of Solid-State Circuits,50,11,2475-2490 IEEE Journal of Solid-State Circuits,50,11,2475-2490 2015/11 英語 研究論文(学術雑誌) 公開
西澤真一, 石原 亨, 小野寺秀俊 西澤真一, 石原 亨, 小野寺秀俊 Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell IPSJ Transactions on System LSI Design Methodology,8,131-135 IPSJ Transactions on System LSI Design Methodology,8,131-135 IPSJ Transactions on System LSI Design Methodology,8,131-135 2015/08 英語 研究論文(学術雑誌) 公開
塩見準, 石原 亨, 小野寺秀俊 塩見準, 石原 亨, 小野寺秀俊 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization IEICE Transactions,E98.A,7,1455-1466 IEICE Transactions,E98.A,7,1455-1466 IEICE Transactions,E98.A,7,1455-1466 2015/07 英語 研究論文(学術雑誌) 公開
高瀬英希, 石原 亨, 冨山宏之, 高田広章他 高瀬英希, 石原 亨, 冨山宏之, 高田広章他 Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada An Integrated Framework for Energy Optimization of Embedded Real-Time Applications An Integrated Framework for Energy Optimization of Embedded Real-Time Applications An Integrated Framework for Energy Optimization of Embedded Real-Time Applications IEICE Transactions,E97.A,12,2477-2487 IEICE Transactions,E97.A,12,2477-2487 IEICE Transactions,E97.A,12,2477-2487 2014/12 英語 研究論文(学術雑誌) 公開
丸山修孝;石原亨;安浦寛人 丸山修孝;石原亨;安浦寛人 RTOSのハードウェア化によるソフトウェアベースTCP/IP処理の高速化と低消費電力化 RTOSのハードウェア化によるソフトウェアベースTCP/IP処理の高速化と低消費電力化 電子情報通信学会論文誌 A,J94-A,9,692-701 電子情報通信学会論文誌 A,J94-A,9,692-701 ,J94-A,9,692-701 2011/09/01 日本語 公開
J. Gu; H. Guo; T. Ishihara J. Gu; H. Guo; T. Ishihara DLIC: Decoded loop instructions caching for energy-aware embedded processors DLIC: Decoded loop instructions caching for energy-aware embedded processors Transactions on Embedded Computing Systems,13,1 ,13,1 Transactions on Embedded Computing Systems,13,1 2013 英語 公開
S. Nishizawa; T. Ishihara; H. Onodera S. Nishizawa; T. Ishihara; H. Onodera Standard cell structure with flexible P/N well boundaries for near-threshold voltage operation Standard cell structure with flexible P/N well boundaries for near-threshold voltage operation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E96-A,12,2499-2507 ,E96-A,12,2499-2507 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E96-A,12,2499-2507 2013 英語 公開
K. Lee; T. Ishihara K. Lee; T. Ishihara DC-DC converter-aware task scheduling and dynamic reconfiguration for energy harvesting embedded systems DC-DC converter-aware task scheduling and dynamic reconfiguration for energy harvesting embedded systems IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E96-A,12,2660-2667 ,E96-A,12,2660-2667 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E96-A,12,2660-2667 2013 英語 公開
M. Kondo; S. Nishizawa; T. Ishihara; H. Onodera M. Kondo; S. Nishizawa; T. Ishihara; H. Onodera A standard cell optimization method for near-threshold voltage operations A standard cell optimization method for near-threshold voltage operations Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),7606,32-41 ,7606,32-41 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),7606,32-41 2013 英語 公開
L. Gauthier; T. Ishihara L. Gauthier; T. Ishihara Processor energy characterization for compiler-assisted software energy reduction Processor energy characterization for compiler-assisted software energy reduction Journal of Electrical and Computer Engineering Journal of Electrical and Computer Engineering 2012 英語 公開
L. Gauthier; T. Ishihara L. Gauthier; T. Ishihara Implementation of stack data placement and run time management using a scratch-pad memory for energy consumption reduction of embedded applications Implementation of stack data placement and run time management using a scratch-pad memory for energy consumption reduction of embedded applications IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E94-A,12,2597-2608 ,E94-A,12,2597-2608 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E94-A,12,2597-2608 2011/12 英語 公開
M. Goudarzi; T. Ishihara; H. Noori M. Goudarzi; T. Ishihara; H. Noori Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),6590,275-299 ,6590,275-299 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),6590,275-299 2011 英語 公開
Y. Ishitobi; T. Ishihara; H. Yasuura Y. Ishitobi; T. Ishihara; H. Yasuura Code and data placement for embedded processors with scratchpad and cache memories Code and data placement for embedded processors with scratchpad and cache memories Journal of Signal Processing Systems,60,2,211-224 ,60,2,211-224 Journal of Signal Processing Systems,60,2,211-224 2010 英語 公開
M. Goudarzi; T. Ishihara M. Goudarzi; T. Ishihara SRAM leakage reduction by row/column redundancy under random within-die delay variation SRAM leakage reduction by row/column redundancy under random within-die delay variation IEEE Transactions on Very Large Scale Integration (VLSI) Systems,18,12,1660-1671 ,18,12,1660-1671 IEEE Transactions on Very Large Scale Integration (VLSI) Systems,18,12,1660-1671 2010 英語 公開
T. Ishihara T. Ishihara A multi-performance processor for reducing the energy consumption of real-time embedded systems A multi-performance processor for reducing the energy consumption of real-time embedded systems IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E93-A,12,2533-2541 ,E93-A,12,2533-2541 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E93-A,12,2533-2541 2010 英語 公開
M. Muroyama; T. Ishihara; H. Yasuura M. Muroyama; T. Ishihara; H. Yasuura Analysis of effects of input arrival time variations on on-chip bus power consumption Analysis of effects of input arrival time variations on on-chip bus power consumption Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),5349,62-71 ,5349,62-71 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),5349,62-71 2009 英語 公開
T. Matsumura; T. Ishihara; H. Yasuura T. Matsumura; T. Ishihara; H. Yasuura An optimization technique for low-energy embedded memory systems An optimization technique for low-energy embedded memory systems IPSJ Transactions on System LSI Design Methodology,2,239-249 ,2,239-249 IPSJ Transactions on System LSI Design Methodology,2,239-249 2009 英語 公開
S. Yamaguchi; Y. Ishitobi; T. Ishihara; H. Yasuura S. Yamaguchi; Y. Ishitobi; T. Ishihara; H. Yasuura Single-cycle-accessible two-level caches and compilation technique for energy reducion Single-cycle-accessible two-level caches and compilation technique for energy reducion IPSJ Transactions on System LSI Design Methodology,2,189-199 ,2,189-199 IPSJ Transactions on System LSI Design Methodology,2,189-199 2009 英語 公開
M. Goudarzi; T. Ishihara M. Goudarzi; T. Ishihara Value-dependence of SRAM leakage in deca-nanometer technologies Value-dependence of SRAM leakage in deca-nanometer technologies IEICE Electronics Express,5,1,23-28 ,5,1,23-28 IEICE Electronics Express,5,1,23-28 2008 英語 公開
M. Goudarzi; T. Ishihara; H. Noori M. Goudarzi; T. Ishihara; H. Noori Variation-aware software techniques for cache leakage reduction using value-dependence of SRAM leakage due to within-die process variation Variation-aware software techniques for cache leakage reduction using value-dependence of SRAM leakage due to within-die process variation Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),4917,224-239 ,4917,224-239 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),4917,224-239 2008 英語 公開
M. Goudarzi; T. Ishihara; H. Yasuura M. Goudarzi; T. Ishihara; H. Yasuura A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V<sub>th</sub> variation A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V<sub>th</sub> variation Microelectronics Journal,39,12,1797-1808 ,39,12,1797-1808 Microelectronics Journal,39,12,1797-1808 2008 英語 公開
M. Sugiharat; T. Ishihara; K. Murakami M. Sugiharat; T. Ishihara; K. Murakami Reliable cache architectures and task scheduling for multiprocessor systems Reliable cache architectures and task scheduling for multiprocessor systems IEICE Transactions on Electronics,E91-C,4,410-417 ,E91-C,4,410-417 IEICE Transactions on Electronics,E91-C,4,410-417 2008 英語 公開
M. Goudarzi; T. Matsumura; T. Ishihara M. Goudarzi; T. Matsumura; T. Ishihara Way-scaling to reduce power of cache with delay variation Way-scaling to reduce power of cache with delay variation IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E91-A,12,3576-3584 ,E91-A,12,3576-3584 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E91-A,12,3576-3584 2008 英語 公開
T. Ishihara T. Ishihara Energy-efficient embedded system design at 90nm and below - A system-level perspective - Energy-efficient embedded system design at 90nm and below - A system-level perspective - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),4759 LNCS,452-465 ,4759 LNCS,452-465 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),4759 LNCS,452-465 2008 英語 公開
H. Onodera; M. Ikeda; T. Ishihara; T. Isshiki; K. Inoue; K. Okada; S. Kajihara; M. Kaneko; H. Kawaguchi; S. Kimura; M. Kuga; A. Kurokawa; T. Sato; T. Shibuya; Y. Shiraishi; K. Takagi; A. Takahashi; Y. Takeuchi; N. Togawa; H. Tomiyama; Y. Nakamura; K. Hamaguchi; Y. Miura; S.-I. Minato; R. Yamaguchi; M. Yamada; Y. Yuminaka; T. Watanabe; M. Hashimoto; M. Miyazaki H. Onodera; M. Ikeda; T. Ishihara; T. Isshiki; K. Inoue; K. Okada; S. Kajihara; M. Kaneko; H. Kawaguchi; S. Kimura; M. Kuga; A. Kurokawa; T. Sato; T. Shibuya; Y. Shiraishi; K. Takagi; A. Takahashi; Y. Takeuchi; N. Togawa; H. Tomiyama; Y. Nakamura; K. Hamaguchi; Y. Miura; S.-I. Minato; R. Yamaguchi; M. Yamada; Y. Yuminaka; T. Watanabe; M. Hashimoto; M. Miyazaki Special section on VLSI Design and CAD Algorithms Special section on VLSI Design and CAD Algorithms IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,12,3377 ,E89-A,12,3377 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E89-A,12,3377 2006 英語 公開
H. Yasuura; T. Ishihara; M. Muroyama H. Yasuura; T. Ishihara; M. Muroyama Energy management techniques for SOC design Energy management techniques for SOC design Essential Issues in SOC Design: Designing Complex Systems-on-Chip,177-223 ,177-223 Essential Issues in SOC Design: Designing Complex Systems-on-Chip,177-223 2006 英語 公開
T. Okuma; H. Yasuura; T. Ishihara T. Okuma; H. Yasuura; T. Ishihara Software energy reduction techniques for variable-voltage processors Software energy reduction techniques for variable-voltage processors IEEE Design and Test of Computers,18,2,31-41 ,18,2,31-41 IEEE Design and Test of Computers,18,2,31-41 2001 英語 公開
A. Inoue; T. Ishihara; H. Yasuura A. Inoue; T. Ishihara; H. Yasuura Flexible system LSI for embedded systems and its optimization techniques Flexible system LSI for embedded systems and its optimization techniques Design Automation for Embedded Systems,5,2,179-205 ,5,2,179-205 Design Automation for Embedded Systems,5,2,179-205 2000 英語 公開
H. Yasuura; T. Ishihara H. Yasuura; T. Ishihara System LSI design methods for low power LSIs System LSI design methods for low power LSIs IEICE Transactions on Electronics,E83-C,2,143-152 ,E83-C,2,143-152 IEICE Transactions on Electronics,E83-C,2,143-152 2000 英語 公開
K. Indue; T. Ishihara K. Indue; T. Ishihara A high-performance and low-power cache architecture with speculative way-selection A high-performance and low-power cache architecture with speculative way-selection IEICE Transactions on Electronics,E83-C,2,186-193 ,E83-C,2,186-193 IEICE Transactions on Electronics,E83-C,2,186-193 2000 英語 公開
T. Ishihara; H. Yasuura T. Ishihara; H. Yasuura A memory power optimization technique for application specific embedded systems A memory power optimization technique for application specific embedded systems IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E82-A,11,2366-2374 ,E82-A,11,2366-2374 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E82-A,11,2366-2374 1999 英語 公開
T. Ishihara; H. Yasuura T. Ishihara; H. Yasuura Programmable power management architecture for power reduction Programmable power management architecture for power reduction IEICE Transactions on Electronics,E81-C,9,1473-1479 ,E81-C,9,1473-1479 IEICE Transactions on Electronics,E81-C,9,1473-1479 1998 英語 公開
H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E81-A,12,2621-2629 ,E81-A,12,2621-2629 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E81-A,12,2621-2629 1998 英語 公開
T. Ishihara T. Ishihara Experimental analysis of power estimation models of CMOS VLSI circuits Experimental analysis of power estimation models of CMOS VLSI circuits IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E80-A,3,480-486 ,E80-A,3,480-486 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,E80-A,3,480-486 1997 英語 公開

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著者 著者(日本語) 著者(英語) タイトル タイトル(日本語) タイトル(英語) 書誌情報等 書誌情報等(日本語) 書誌情報等(英語) 出版年月 査読の有無 記述言語 掲載種別 公開
竹下俊宏、石原 亨、小野寺 秀俊 竹下俊宏、石原 亨、小野寺 秀俊 Toshihiro Takeshita, Tohru Ishihara, Hidetoshi Onodera Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling International Symposium on VLSI Design, Automation and Test,1-4 International Symposium on VLSI Design, Automation and Test,1-4 International Symposium on VLSI Design, Automation and Test,1-4 2016/04 英語 研究発表要旨(国際会議) 公開
塩見準、石原 亨、小野寺秀俊 塩見準、石原 亨、小野寺秀俊 J Shiomi, T Ishihara, H Onodera Variability-and correlation-aware logical effort for near-threshold circuit design Variability-and correlation-aware logical effort for near-threshold circuit design Variability-and correlation-aware logical effort for near-threshold circuit design International Symposium on Quality Electronic Design,2016-May,18-23 International Symposium on Quality Electronic Design,2016-May,18-23 International Symposium on Quality Electronic Design,2016-May,18-23 2016/03 英語 研究発表要旨(国際会議) 公開
鎌苅 竜也、塩見 準、石原 亨、小野寺 秀俊 鎌苅 竜也、塩見 準、石原 亨、小野寺 秀俊 Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region 21st Asia and South Pacific Design Automation Conference,25-28-January-2016,691-696 21st Asia and South Pacific Design Automation Conference,25-28-January-2016,691-696 21st Asia and South Pacific Design Automation Conference,25-28-January-2016,691-696 2016/01 英語 研究発表要旨(国際会議) 公開
塩見 準、石原 亨、小野寺 秀俊 塩見 準、石原 亨、小野寺 秀俊 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design International Workshop on Variability Modeling and Charactorization International Workshop on Variability Modeling and Charactorization International Workshop on Variability Modeling and Charactorization 2015/11 英語 研究発表要旨(国際会議) 公開
石原 亨 石原 亨 Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera An impact of process variation on supply voltage dependence of logic path delay variation An impact of process variation on supply voltage dependence of logic path delay variation An impact of process variation on supply voltage dependence of logic path delay variation International Symposium on VLSI Design,1-4 International Symposium on VLSI Design,1-4 International Symposium on VLSI Design,1-4 2015/04 英語 総説・解説(国際会議プロシーディングス) 公開
石原 亨 石原 亨 Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera Energy reduction by built-in body biasing with single supply voltage operation Energy reduction by built-in body biasing with single supply voltage operation Energy reduction by built-in body biasing with single supply voltage operation International Symposium on Quality Electric Design,2015-April,181-185 International Symposium on Quality Electric Design,2015-April,181-185 International Symposium on Quality Electric Design,2015-April,181-185 2015/03 英語 総説・解説(国際会議プロシーディングス) 公開
石原 亨 石原 亨 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera An energy-efficient on-chip memory structure for variability-aware near-threshold operation An energy-efficient on-chip memory structure for variability-aware near-threshold operation An energy-efficient on-chip memory structure for variability-aware near-threshold operation International Symposium on Quality Electric Design,2015-April,23-28 International Symposium on Quality Electric Design,2015-April,23-28 International Symposium on Quality Electric Design,2015-April,23-28 2015/03 英語 総説・解説(国際会議プロシーディングス) 公開
石原 亨 石原 亨 Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera Microarchitectural-level statistical timing models for near-threshold circuit design Microarchitectural-level statistical timing models for near-threshold circuit design Microarchitectural-level statistical timing models for near-threshold circuit design Asia-South Pacific Design Automation Conference,87-93 Asia-South Pacific Design Automation Conference,87-93 Asia-South Pacific Design Automation Conference,87-93 2015/01 英語 総説・解説(国際会議プロシーディングス) 公開
石原 亨 石原 亨 Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation IEEE International System-on-Chip Conference,42-47 IEEE International System-on-Chip Conference,42-47 IEEE International System-on-Chip Conference,42-47 2014/09 英語 総説・解説(国際会議プロシーディングス) 公開
石原 亨 石原 亨 Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Variation-aware Flip-Flop energy optimization for ultra low voltage operation Variation-aware Flip-Flop energy optimization for ultra low voltage operation Variation-aware Flip-Flop energy optimization for ultra low voltage operation IEEE International System-on-Chip Conference,17-22 IEEE International System-on-Chip Conference,17-22 IEEE International System-on-Chip Conference,17-22 2014 英語 研究発表要旨(国際会議) 公開
S. Nishizawa; T. Ishihara; H. Onodera S. Nishizawa; T. Ishihara; H. Onodera Analysis and comparison of XOR cell structures for low voltage circuit design Analysis and comparison of XOR cell structures for low voltage circuit design Proceedings - International Symposium on Quality Electronic Design, ISQED,703-708 ,703-708 Proceedings - International Symposium on Quality Electronic Design, ISQED,703-708 2013 英語 公開
A.K.M.M. Islam; T. Ishihara; H. Onodera A.K.M.M. Islam; T. Ishihara; H. Onodera Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013,125-128 ,125-128 Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013,125-128 2013 英語 総説・解説(国際会議プロシーディングス) 公開
S. Nishizawa; T. Ishihara; H. Onodera S. Nishizawa; T. Ishihara; H. Onodera A flexible structure of standard cell and its optimization method for near-threshold voltage operation A flexible structure of standard cell and its optimization method for near-threshold voltage operation Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors,235-240 ,235-240 Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors,235-240 2012 英語 公開
I.A.K.M. Mahfuzul; N. Kamae; T. Ishihara; H. Onodera I.A.K.M. Mahfuzul; N. Kamae; T. Ishihara; H. Onodera A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC,101-104 ,101-104 Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC,101-104 2012 英語 公開
J. Gu; T. Ishihara; K. Lee J. Gu; T. Ishihara; K. Lee Loop instruction caching for energy-efficient embedded multitasking processors Loop instruction caching for energy-efficient embedded multitasking processors 2012 IEEE 10th Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2012,97-106 ,97-106 2012 IEEE 10th Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2012,97-106 2012 英語 公開
K. Lee; T. Ishihara K. Lee; T. Ishihara I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays 2012 IEEE 10th Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2012,48-55 ,48-55 2012 IEEE 10th Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2012,48-55 2012 英語 公開
K. Lee; T. Ishihara K. Lee; T. Ishihara A dynamic reconfiguration technique for PV and capacitor arrays to improve the efficiency in energy harvesting embedded systems A dynamic reconfiguration technique for PV and capacitor arrays to improve the efficiency in energy harvesting embedded systems SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems,175-182 ,175-182 SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems,175-182 2012 英語 公開
J. Gu; T. Ishihara J. Gu; T. Ishihara A case study of energy-efficient loop instruction cache design for embedded multitasking systems A case study of energy-efficient loop instruction cache design for embedded multitasking systems SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems,197-202 ,197-202 SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems,197-202 2012 英語 公開
H. Takase; G. Zeng; L. Gauthier; H. Kawashima; N. Atsumi; T. Tatematsu; Y. Kobayashi; S. Kohara; T. Koshiro; T. Ishihara; H. Tomiyama; H. Takada H. Takase; G. Zeng; L. Gauthier; H. Kawashima; N. Atsumi; T. Tatematsu; Y. Kobayashi; S. Kohara; T. Koshiro; T. Ishihara; H. Tomiyama; H. Takada An integrated optimization framework for reducing the energy consumption of embedded real-time applications An integrated optimization framework for reducing the energy consumption of embedded real-time applications Proceedings of the International Symposium on Low Power Electronics and Design,2011,271-276 ,2011,271-276 Proceedings of the International Symposium on Low Power Electronics and Design,2011,271-276 2011 英語 公開
T. Okuhira; T. Ishihara T. Okuhira; T. Ishihara Unified gated flip-flops for reducing the clocking power in register circuits Unified gated flip-flops for reducing the clocking power in register circuits Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),6951,237-246 ,6951,237-246 Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),6951,237-246 2011 英語 公開
A. Matsuda; T. Ishihara A. Matsuda; T. Ishihara Developing an integrated verification and debug methodology Developing an integrated verification and debug methodology Proceedings -Design, Automation and Test in Europe, DATE,503-504 ,503-504 Proceedings -Design, Automation and Test in Europe, DATE,503-504 2011 英語 公開
L. Gauthier; T. Ishihara L. Gauthier; T. Ishihara Compiler assisted energy reduction techniques for embedded multimedia processors Compiler assisted energy reduction techniques for embedded multimedia processors APSIPA ASC 2010 - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference,27-36 ,27-36 APSIPA ASC 2010 - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference,27-36 2010 英語 公開
N. Maruyama; T. Ishihara; H. Yasuura N. Maruyama; T. Ishihara; H. Yasuura An RTOS in hardware for energy efficient software-based TCP/IP processing An RTOS in hardware for energy efficient software-based TCP/IP processing Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP\\'10,58-63 ,58-63 Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP\\'10,58-63 2010 英語 公開
C. Zang; T. Ishihara C. Zang; T. Ishihara An implementation of energy efficient multi-performance processor for real-time applications An implementation of energy efficient multi-performance processor for real-time applications 1st International Conference on Green Circuits and Systems, ICGCS 2010,211-216 ,211-216 1st International Conference on Green Circuits and Systems, ICGCS 2010,211-216 2010 英語 公開
L. Gauthier; T. Ishihara; H. Takase; H. Tomiyama; H. Takada L. Gauthier; T. Ishihara; H. Takase; H. Tomiyama; H. Takada Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems Embedded Systems Week 2010 - Proceedings of the 2010 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES\\'10,157-166 ,157-166 Embedded Systems Week 2010 - Proceedings of the 2010 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES\\'10,157-166 2010 英語 公開
L. Gauthier; T. Ishihara L. Gauthier; T. Ishihara Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2009,116-125 ,116-125 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2009,116-125 2009 英語 公開
T. Ishihara T. Ishihara Real-time power management for a multi-performance processor Real-time power management for a multi-performance processor 2009 International SoC Design Conference, ISOCC 2009,147-152 ,147-152 2009 International SoC Design Conference, ISOCC 2009,147-152 2009 英語 公開
M. Goudarzi; T. Matsumura; T. Ishihara M. Goudarzi; T. Matsumura; T. Ishihara Cache power reduction in presence of within-die delay variation using spare ways Cache power reduction in presence of within-die delay variation using spare ways Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008,447-450 ,447-450 Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008,447-450 2008 英語 公開
T. Ishihara; S. Yamaguchi; Y. Ishitobi; T. Matsumura; Y. Kunitake; Y. Oyama; Y. Kaneda; M. Muroyama; T. Sato T. Ishihara; S. Yamaguchi; Y. Ishitobi; T. Matsumura; Y. Kunitake; Y. Oyama; Y. Kaneda; M. Muroyama; T. Sato AMPLE: An adaptive multi-performance processor for low-energy embedded applications AMPLE: An adaptive multi-performance processor for low-energy embedded applications 2008 Symposium on Application Specific Processors, SASP 2008,83-88 ,83-88 2008 Symposium on Application Specific Processors, SASP 2008,83-88 2008 英語 公開
M. Goudarzi; T. Ishihara M. Goudarzi; T. Ishihara Instruction cache leakage reduction by changing register operands and using asymmetric SRAM cells Instruction cache leakage reduction by changing register operands and using asymmetric SRAM cells Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI,383-386 ,383-386 Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI,383-386 2008 英語 公開
T. Matsumura; T. Ishihara; H. Yasuura T. Matsumura; T. Ishihara; H. Yasuura Simultaneous optimization of memory configuration and code allocation for low power embedded systems Simultaneous optimization of memory configuration and code allocation for low power embedded systems Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI,403-406 ,403-406 Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI,403-406 2008 英語 公開
M. Goudarzi; T. Ishihara M. Goudarzi; T. Ishihara Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation Proceedings of the International Symposium on Low Power Electronics and Design,93-98 ,93-98 Proceedings of the International Symposium on Low Power Electronics and Design,93-98 2008 英語 公開
G. Zeng; H. Tomiyama; H. Takada; T. Ishihara G. Zeng; H. Tomiyama; H. Takada; T. Ishihara A generalized framework for system-wide energy savings in hard real-time embedded systems A generalized framework for system-wide energy savings in hard real-time embedded systems Proceedings of The 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008,206-213 ,206-213 Proceedings of The 5th International Conference on Embedded and Ubiquitous Computing, EUC 2008,206-213 2008 英語 公開
S. Yamaguchi; T. Ishihara; H. Yasuura S. Yamaguchi; T. Ishihara; H. Yasuura A single cycle accessible two-level cache architecture for the energy consumption of embedded systems A single cycle accessible two-level cache architecture for the energy consumption of embedded systems 2008 International SoC Design Conference, ISOCC 2008,1,188-191 ,1,188-191 2008 International SoC Design Conference, ISOCC 2008,1,188-191 2008 英語 公開
G. Zeng; T. Yokoyama; H. Tomiyama; H. Takada; T. Ishihara G. Zeng; T. Yokoyama; H. Tomiyama; H. Takada; T. Ishihara A generalized framework for energy savings in real-time multiprocessor systems A generalized framework for energy savings in real-time multiprocessor systems 2008 International SoC Design Conference, ISOCC 2008,44-49 ,44-49 2008 International SoC Design Conference, ISOCC 2008,44-49 2008 英語 公開
M. Goudarzi; T. Ishihara M. Goudarzi; T. Ishihara Redundancy techniques for SRAM leakage reduction in presence of within-die delay variation Redundancy techniques for SRAM leakage reduction in presence of within-die delay variation 2008 International SoC Design Conference, ISOCC 2008,192-195 ,192-195 2008 International SoC Design Conference, ISOCC 2008,192-195 2008 英語 公開
M. Sugihara; T. Ishihara; K. Murakami M. Sugihara; T. Ishihara; K. Murakami Task scheduling for reliable cache architectures of multiprocessor systems Task scheduling for reliable cache architectures of multiprocessor systems Proceedings -Design, Automation and Test in Europe, DATE,1490-1495 ,1490-1495 Proceedings -Design, Automation and Test in Europe, DATE,1490-1495 2007 英語 公開
M. Goudarzi; T. Ishihara; H. Yasuura M. Goudarzi; T. Ishihara; H. Yasuura A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC,878-883 ,878-883 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC,878-883 2007 英語 公開
Y. Ishitobi; T. Ishihara; H. Yasuura Y. Ishitobi; T. Ishihara; H. Yasuura Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007,13-18 ,13-18 Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007,13-18 2007 英語 公開
M. Sugihara; T. Ishihara; K. Hashimoto; M. Muroyama M. Sugihara; T. Ishihara; K. Hashimoto; M. Muroyama A simulation-based soft error estimation methodology for computer systems A simulation-based soft error estimation methodology for computer systems Proceedings - International Symposium on Quality Electronic Design, ISQED,196-203 ,196-203 Proceedings - International Symposium on Quality Electronic Design, ISQED,196-203 2006 英語 公開
D. Lee; T. Ishihara; M. Muroyama; H. Yasuura; F. Fallah D. Lee; T. Ishihara; M. Muroyama; H. Yasuura; F. Fallah An energy characterization framework for software-based embedded systems An energy characterization framework for software-based embedded systems Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, ESTIMEDIA 2006,59-64 ,59-64 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, ESTIMEDIA 2006,59-64 2006 英語 公開
T. Ishihara; F. Fallah T. Ishihara; F. Fallah A way memoization technique for reducing power consumption of caches in application specific integrated processors A way memoization technique for reducing power consumption of caches in application specific integrated processors Proceedings -Design, Automation and Test in Europe, DATE \\'05,I,358-363 ,I,358-363 Proceedings -Design, Automation and Test in Europe, DATE \\'05,I,358-363 2005 英語 公開
T. Ishihara; F. Fallah T. Ishihara; F. Fallah A cache-defect-aware code placement algorithm for improving the performance of processors A cache-defect-aware code placement algorithm for improving the performance of processors IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD,2005,992-998 ,2005,992-998 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD,2005,992-998 2005 英語 公開
T. Ishihara; F. Fallah T. Ishihara; F. Fallah A non-uniform cache architecture for low power system design A non-uniform cache architecture for low power system design Proceedings of the International Symposium on Low Power Electronics and Design,363-368 ,363-368 Proceedings of the International Symposium on Low Power Electronics and Design,363-368 2005 英語 公開
T. Ishihara; H. Yasuura T. Ishihara; H. Yasuura A power reduction technique with object code merging for application specific embedded processors A power reduction technique with object code merging for application specific embedded processors Proceedings -Design, Automation and Test in Europe, DATE,617-623 ,617-623 Proceedings -Design, Automation and Test in Europe, DATE,617-623 2000 英語 公開
Koji Inoue; Tohru Ishihara; Kazuaki Murakami Koji Inoue; Tohru Ishihara; Kazuaki Murakami Way-predicting set-associative cache for high performance and low energy consumption Way-predicting set-associative cache for high performance and low energy consumption Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers,273-275 ,273-275 Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers,273-275 1999 英語 公開
H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura Instruction scheduling for power reduction in processor-based system design Instruction scheduling for power reduction in processor-based system design Proceedings -Design, Automation and Test in Europe, DATE,855-860 ,855-860 Proceedings -Design, Automation and Test in Europe, DATE,855-860 1998 英語 公開
Tohru Ishihara; Hiroto Yasuura Tohru Ishihara; Hiroto Yasuura Voltage scheduling problem for dynamically variable voltage processors Voltage scheduling problem for dynamically variable voltage processors Proceedings of the International Symposium on Low Power Design,197-202 ,197-202 Proceedings of the International Symposium on Low Power Design,197-202 1998 英語 公開
Tohru Ishihara; Hiroto Yasuura Tohru Ishihara; Hiroto Yasuura Power-Pro: Programmable Power Management Architecture Power-Pro: Programmable Power Management Architecture Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC,321-322 ,321-322 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC,321-322 1998 英語 公開
Tohru Ishihara; Hiroto Yasuura Tohru Ishihara; Hiroto Yasuura Basic experimentation on accuracy of power estimation for CMOS VLSI circuits Basic experimentation on accuracy of power estimation for CMOS VLSI circuits International Symposium on Low Power Electronics and Design, Digest of Technical Papers,117-120 ,117-120 International Symposium on Low Power Electronics and Design, Digest of Technical Papers,117-120 1996 英語 公開

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タイトル言語:
講演・口頭発表等
タイトル タイトル(日本語) タイトル(英語) 会議名 会議名(日本語) 会議名(英語) 主催者 主催者(日本語) 主催者(英語) 開催年月日 記述言語 会議種別 公開
An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation[招待あり] An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation [招待あり] An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation [招待あり] International Forum on MPSoC for Software-defined Hardware International Forum on MPSoC for Software-defined Hardware International Forum on MPSoC for Software-defined Hardware 2016/07/14 英語 口頭発表(招待・特別) 公開
Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors[招待あり] Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors [招待あり] Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors [招待あり] International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore 2015/07/13 英語 口頭発表(招待・特別) 公開
Near-Threshold Computing on Heterogeneous Multicore Architectures[招待あり] Near-Threshold Computing on Heterogeneous Multicore Architectures [招待あり] Near-Threshold Computing on Heterogeneous Multicore Architectures [招待あり] International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore 2014/07/10 英語 口頭発表(招待・特別) 公開
Power Management Techniques for Energy Harvesting Embedded Systems[招待あり] Power Management Techniques for Energy Harvesting Embedded Systems [招待あり] Power Management Techniques for Energy Harvesting Embedded Systems [招待あり] International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore 2013/07/18 英語 口頭発表(招待・特別) 公開
Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems[招待あり] Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems [招待あり] Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems [招待あり] International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore 2012/07/11 英語 口頭発表(招待・特別) 公開
Energy Characterization of Embedded Processors for Software Energy Optimization[招待あり] Energy Characterization of Embedded Processors for Software Energy Optimization [招待あり] Energy Characterization of Embedded Processors for Software Energy Optimization [招待あり] International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore International Forum on Embedded MPSoC and Multicore 2011/07/05 英語 口頭発表(招待・特別) 公開
タイトル言語:
書籍等出版物
著者 著者(日本語) 著者(英語) タイトル タイトル(日本語) タイトル(英語) 出版社 出版社(日本語) 出版社(英語) 出版年月 記述言語 担当区分 公開
宇佐美公良、池田誠、小林和淑(監訳)、石原亨ほか(訳) 宇佐美公良、池田誠、小林和淑(監訳)、石原亨ほか(訳) Tohru Ishihara ウェスト&ハリス CMOS VLSI回路設計 基礎編 ウェスト&ハリス CMOS VLSI回路設計 基礎編 CMOS VLSI Design - A Circuits and Systems Perspective 4th ed. 丸善出版 丸善出版 2014/01 共訳 公開
石原 亨 石原 亨 H. Yasuura, T. Ishihara, M. Muroyama Essential Issues in SOC Design: Designing Complex Systems-on-Chip Essential Issues in SOC Design: Designing Complex Systems-on-Chip Essential Issues in SOC Design: Designing Complex Systems-on-Chip Springer Springer Springer 2006/10 共著 公開
タイトル言語:
特許
発明者 発明者(日本語) 発明者(英語) 発明の名称 発明の名称(日本語) 発明の名称(英語) 審査の段階 番号 年月 公開
小西 哲平、神山 剛、大久保 信三、稲村 浩、石原 亨、久住 憲嗣、部谷 修平 小西 哲平、神山 剛、大久保 信三、稲村 浩、石原 亨、久住 憲嗣、部谷 修平 消費電力分析システムおよびアプリケーション開発ツール 消費電力分析システムおよびアプリケーション開発ツール 特許登録 特許5787259 2015/08/07 公開
神山 剛、宮沢 祐光、石原 亨、久住 憲嗣、金田 裕介、奥平 拓見 神山 剛、宮沢 祐光、石原 亨、久住 憲嗣、金田 裕介、奥平 拓見 消費電力評価装置、電力係数作成システム、消費電力評価方法及び電力係数作成方法 消費電力評価装置、電力係数作成システム、消費電力評価方法及び電力係数作成方法 特許登録 特許5429746 2013/12/13 公開
石原 亨、ファルザン ファラー 石原 亨、ファルザン ファラー プロセッサ設計を特徴付けるための方法、装置、論理プログラム及びシステム プロセッサ設計を特徴付けるための方法、装置、論理プログラム及びシステム 特許登録 特許5298444 2013/06/28 公開
石原 亨、ファルザン ファラー 石原 亨、ファルザン ファラー キャッシュメモリ、演算処理装置およびキャッシュメモリの制御方法 キャッシュメモリ、演算処理装置およびキャッシュメモリの制御方法 特許登録 特許5061523 2012/08/17 公開
タイトル言語:
学術賞等
賞の名称(日本語) 賞の名称(英語) 授与組織名(日本語) 授与組織名(英語) 年月
論文賞 Best Paper Award 電子情報通信学会 IEICE 2018/06/07
優秀論文賞 情報処理学会システムLSI設計技術研究会 IPSJ SIG SLDM 2016/09/14
最優秀論文賞 Best Paper Award IEEE International System-on-Chip Conference IEEE International System-on-Chip Conference 2016/09/07
ISLPED 1st Most Cited Paper Award ISLPED 1st Most Cited Paper Award ACM/IEEE International Symposium on Low Power Electronics and Design ACM/IEEE International Symposium on Low Power Electronics and Design 2015/07/25
優秀論文賞 情報処理学会システムLSI設計技術研究会 IPSJ SIG SLDM 2013/08/21
論文賞 Best Paper Award 電子情報通信学会 IEICE 2013/05/25
外部資金:競争的資金・科学研究費補助金
種別 代表/分担 テーマ(日本語) テーマ(英語) 期間
挑戦的萌芽研究 代表 ニアスレッショルド電圧動作に適したオンチップメモリの研究 (平成26年度分) 2014/04/01〜2016/03/31
基盤研究(B) 代表 環境発電技術を用いた社会に溶け込むコンピューティング基盤の研究 (平成26年度分) 2014/04/01〜2017/03/31
基盤研究(B) 代表 環境発電技術を用いた社会に溶け込むコンピューティング基盤の研究 (平成27年度分) 2015/04/01〜2016/03/31
挑戦的萌芽研究 代表 ニアスレッショルド電圧動作に適したオンチップメモリの研究 (平成27年度分) 2015/04/01〜2016/03/31
挑戦的萌芽研究 代表 ニアスレッショルド電圧動作に適したオンチップメモリの研究 (平成28年度分) 2016/04/01〜2017/03/31
基盤研究(B) 代表 環境発電技術を用いた社会に溶け込むコンピューティング基盤の研究 (平成28年度分) 2016/04/01〜2017/03/31
基盤研究(B) 代表 IoT社会の実現を目指した次世代コンピューティング基盤の研究 2017/04/01〜2020/03/31
挑戦的萌芽研究 代表 フォトニクスとエレクトロニクスの融合による光コンピュータの構成法に関する研究 2017/06/01〜2019/03/31
挑戦的研究(萌芽) 代表 フォトニクスとエレクトロニクスの融合による光コンピュータの構成法に関する研究 (平成29年度分) 2017/04/01〜2018/03/31
基盤研究(B) 代表 IoT社会の実現を目指した次世代コンピューティング基盤の研究 (平成29年度分) 2017/04/01〜2018/03/31
外部資金:競争的資金・科学研究費補助金以外
制度名 代表者名 研究課題(日本語) 研究課題(英語) 期間
最先端・次世代研究開発プログラム 石原 亨 環境エネルギーを使用する情報通信機器の組込みプロセッサアーキテクチャとOS制御による最適エネルギー管理技術の開発 A Study on Embedded Processor Architectures and OS-based Power Management Techniques for Environmental Energy-based Systems 2011/02/10〜2014/03/31
総務省 戦略的情報通信研究開発推進事業 石原亨 エネルギーハーベスティングによる真にユビキタスな情報通信基盤の研究開発 2015/07/27〜2016/03/31
担当科目
講義名(日本語) 講義名(英語) 開講期 学部/研究科 年度
組み込み計算機システム Embedded Computer Systems 後期 工学部 2012/04〜2013/03
計算機工学 Computer Hardware Design 後期 工学部 2012/04〜2013/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2012/04〜2013/03
計算機工学 Computer Hardware Design 後期 工学部 2013/04〜2014/03
電気電子工学実験A Electrical and Electronic Engineering Practice A 前期 工学部 2013/04〜2014/03
電気電子工学実験B Electrical and Electronic Engineering Practice B 後期 工学部 2013/04〜2014/03
電気電子工学実習A Electrical and Electronic Engineering Advanced Practice A 前期 工学部 2013/04〜2014/03
電気電子工学実習B Electrical and Electronic Engineering Advanced Practice B 後期 工学部 2013/04〜2014/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2013/04〜2014/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2013/04〜2014/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2013/04〜2014/03
計算機工学 Computer Hardware Design 後期 工学部 2014/04〜2015/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2014/04〜2015/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2014/04〜2015/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2014/04〜2015/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2014/04〜2015/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2015/04〜2016/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2015/04〜2016/03
計算機工学 Computer Hardware Design 後期 工学部 2015/04〜2016/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2015/04〜2016/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2015/04〜2016/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2016/04〜2017/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2016/04〜2017/03
計算機工学 Computer Hardware Design 後期 工学部 2016/04〜2017/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2016/04〜2017/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2016/04〜2017/03
電気電子工学概論 Introducion to Elecrical and Electronic Engineering 後期 工学部 2016/04〜2017/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2017/04〜2018/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2017/04〜2018/03
計算機工学 Computer Hardware Design 後期 工学部 2017/04〜2018/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2017/04〜2018/03
集積システム工学特別セミナー Seminar on Integrated Systems Engineering, Advanced 通年 情報学研究科 2017/04〜2018/03
電気電子工学実習 Advanced Practice of Electrical and Electronic Engineering 後期 工学部 2017/04〜2018/03
電気電子工学概論 Introducion to Elecrical and Electronic Engineering 後期 工学部 2017/04〜2018/03
System-Level Design Methodology for SoCs System-Level Design Methodology for SoCs 後期 情報学研究科 2018/04〜2019/03
組み込み計算機システム Embedded Computer Systems 後期 工学部 2018/04〜2019/03
計算機工学 Computer Hardware Design 後期 工学部 2018/04〜2019/03
集積回路工学 Integraged Circuits Engineering 前期 工学部 2018/04〜2019/03
電気電子工学実習 Advanced Practice of Electrical and Electronic Engineering 後期 工学部 2018/04〜2019/03

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部局運営(役職等)
役職名 期間
図書WG委員 2014/04/01〜2016/03/31
ハラスメント窓口相談員 2014/04/01〜2015/03/31
評価WG委員 2016/04/01〜2017/03/31
広報WG委員 2017/04/01〜2018/03/31
広報WG委員 2018/04/01〜2019/03/31